Multi-level deaggregation memory system of data center

Abstract

The invention provides a multi-level memory deaggregation system for a data center, and the system comprises a host side which comprises a CPU, a local memory connected with the CPU, and an operating system connected with the CPU; the DPU unit is connected with the host side, and the DPU unit comprises a DPU control module and a DPU memory module connected with the DPU control module; the far-end memory pool is connected with the DPU unit; wherein the DPU control module is used for controlling the memory interaction between the DPU unit and the host side and the memory interaction between the DPU unit and the far-end memory pool. According to the system, data interaction between the host side and the DPU and between the DPU and the far-end memory pool is realized, so that the host side can obtain an extended memory and has lower memory access delay at the same time.

Description

Technical Field

[0001] The present invention relates to the field of data centers, and in particular to a multi-level de-aggregated memory system for data centers. Background Art

[0002] The increasing popularity of tasks such as deep learning, graph computing, and key-value storage has led to a surge in memory demand in data centers. However, in many cases, the memory resources in data centers generally have problems with low memory utilization and insufficient dynamics. Studies have shown that the percentage of memory actually actively used in data centers is about 50%, while about 30% of the overall memory is allocated but not used. In addition, in the current server architecture, the CPU and physical memory ratio is fixed, which makes it difficult to dynamically expand the memory capacity of a single server to the required size. When the application working set exceeds the main memory capacity, performance may be severely degraded. Therefore, reducing the waste of memory resources and providing additional extended memory for applications with large memory requirements is one of the key factors to improve data center efficiency and reduce costs. The disaggregated memory system can decouple the CPU from memory resources to form a memory pool that can be shared by multiple hosts. The host can apply for memory from the memory pool on demand, thereby reducing the waste of memory resources and dynamically providing extended memory for the host. Therefore, building a disaggregated memory system can effectively solve the memory problem in the data center.

[0003] At present, the methods for building deaggregated memory systems can be mainly divided into two categories. The first method is to use local memory first, use extended memory as the next level storage of local memory, and use extended memory when local memory is about to be exhausted, such as the TPP method; the second method treats local memory and extended memory as two independent spaces, and the use of the two does not affect each other. Usually, extended memory is used directly, such as Kona. The physical location of the extended memory provided by TPP is still local, and its efficiency is limited by the memory capacity of the extended memory node. However, the memory capacity that can be provided locally is often limited, and TPP faces the problem of poor scalability. In addition, the extended memory node can only be accessed by the host connected to it, and cannot be provided to other host nodes, which will lead to a waste of memory resources. For example, due to different tasks running on the hosts, the extended memory of some hosts is exhausted, while the extended memory of some hosts is still idle. The former cannot access the extended memory of the latter, resulting in waste, because they cannot share the extended memory node. Kona cannot use local memory when using extended memory, and the delay of accessing extended memory is greater than that of local memory, so the overall delay of Kona memory access is large. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a data center multi-level de-aggregated memory system, comprising:

[0005] The host side includes: CPU, local memory connected to the CPU, and operating system connected to the CPU;

[0006] A DPU unit is connected to the host side, and the DPU unit includes: a DPU control module, and a DPU memory module connected to the DPU control module;

[0007] A remote memory pool connected to the DPU unit;

[0008] The DPU control module controls the memory interaction between the DPU unit and the host side, and between the DPU unit and the remote memory pool.

[0009] In one embodiment of the present invention, the memory capacity configured by the DPU unit includes the actual capacity of the DPU memory module and the capacity of the remote memory pool, wherein the actual capacity of the DPU memory module corresponds to a real physical address range; the capacity of the remote memory pool corresponds to a virtual physical address range;

[0010] The host side CPU accesses the DPU memory module through the virtual physical address;

[0011] The DPU control module receives a memory access request using the VPA from the host-side CPU and translates the virtual physical address into a real physical address;

[0012] The DPU control module accesses the DPU memory module or the remote memory pool according to the real physical address obtained by translation.

[0013] In one embodiment of the present invention, the DPU unit is configured with a page table recording the mapping relationship between the virtual physical address and the real physical address, and each item of the page table at least includes a virtual physical address number, a real physical address number and a flag bit;

[0014] The flag bit at least includes a present bit and a valid bit, wherein the present bit is used to indicate that the page exists in the DPU memory module or in the remote memory pool, and the valid bit is used to indicate whether the page table entry is valid.

[0015] In one embodiment of the present invention, a cache is used to cache recently used page table entries;

[0016] The DPU control module first accesses the cache to translate the virtual physical address into a real physical address, and when the cache misses, accesses the page table and updates the cache.

[0017] In one embodiment of the present invention, the local memory is configured with a bitmap, which is used to record the allocation of the DPU memory module. Each bit of the bitmap is an idle state flag bit, corresponding to a page of the virtual physical address space, and the idle state flag bit is used to identify the idle state of the corresponding page;

[0018] If a page migration request is received from the host side, the bitmap is queried, an idle page is found according to the idle state flag, and the page migrated from the local memory request on the host side is allocated to the idle page, wherein the page migration request is a request to migrate the page on the host side to the DPU memory module.

[0019] In one embodiment of the present invention, when querying the bitmap, the search starts from the next page of the free page of the last allocated memory, and until a free page is found, the page requested to be migrated by the host side is allocated to the free page.

[0020] In one embodiment of the present invention, upon receiving the page migration request from the host side,

[0021] If it is detected that the DPU memory module is insufficient in memory, the DPU control module filters out the pages in the DPU memory module that need to be replaced to the remote memory pool, and transmits the pages to the remote memory pool storage through the network interface; and migrates the pages requested to be migrated from the host side to the DPU memory module.

[0022] In one embodiment of the present invention, the DPU unit is further configured with a local access count table for recording the number of times the host-side CPU accesses each page of the DPU memory module;

[0023] The DPU control module records the number of visits to each page, and if the number of visits to a page reaches a first threshold, it is identified as a first hotspot page;

[0024] The operating system on the host side accesses the local access count table through the CPU at regular intervals. When the operating system identifies the existence of a first hotspot page, the first hotspot page is migrated from the DPU memory module to the local memory on the host side for storage.

[0025] In one embodiment of the present invention, the DPU unit is further configured with a remote access count table for recording the number of times the DPU unit accesses each page of the remote memory pool;

[0026] When the DPU control module detects that the number of accesses to a page reaches a second threshold, it identifies the page as a second hotspot page and migrates the second hotspot page from the remote memory pool to the DPU memory module for storage.

[0027] In an embodiment of the present invention, the DPU unit is further configured with a cache coherence interface, and the host side is connected to the DPU unit via the cache coherence interface.

[0028] It can be seen from the above scheme that the advantages of the present invention are:

[0029] The multi-level deaggregated memory system of the data center disclosed by the present invention cooperates to realize the data interaction method between the host side and the DPU unit, and the DPU unit and the remote memory pool, and realizes the expansion of the local memory to the DPU memory and then to the remote memory, so that the host can obtain the extended memory while having a lower memory access delay. The method realizes the migration of memory pages in two directions from the host local memory to the DPU memory and from the DPU memory to the host memory, reducing the impact of migrating pages to the DPU memory on the memory access delay; in addition, the method realizes the migration of memory pages in two directions from the DPU memory to the remote memory and from the remote memory to the DPU memory, reducing the impact of migrating pages to the remote memory on the memory access delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural diagram of a multi-level de-aggregated memory system for a data center disclosed in an embodiment of the present invention;

[0031] Figure 2 It is the data structure diagram of the page table;

[0032] Figure 3 The data structure diagram of the bitmap;

[0033] Figure 4 This is the data structure diagram of the local access count table.

[0034] Reference numerals:

[0035] 10: Multi-level de-aggregated memory system for data centers;

[0036] 11: Host side;

[0037] 12: DPU unit;

[0038] 13: Remote memory pool;

[0039] 111:CPU;

[0040] 112: local memory;

[0041] 113: operating system;

[0042] 121: DPU control module;

[0043] 122:DPU memory module;

[0044] 123: network interface;

[0045] 124: cache coherence interface;

[0046] 125:Memory controller. DETAILED DESCRIPTION

[0047] It should be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0048] Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0049] Please refer to Figure 1 As shown in Figure 1 A structural diagram of a multi-level de-aggregated memory system for a data center constructed according to an embodiment of the present invention is shown.

[0050] The data center multi-level deaggregated memory system 10 specifically includes three parts: a host side 11, a DPU (Data Processing Unit) unit 12, and a remote memory pool 13. The host side 11 and the DPU unit 12 are interconnected, and the DPU unit 12 is interconnected with the remote memory pool 13. The host side 11 specifically includes a CPU 111, a local memory 112, and an operating system 113. The local memory 112 is connected to the CPU (Central Processing Unit) 111, and the CPU 111 is connected to the operating system. In one embodiment, the host side is a server, and the data center application runs on the operating system and accesses the local memory during operation.

[0051] The DPU unit 12 includes a DPU control module 121, a DPU memory module 122, a network interface 123, a cache consistency interface 124, a memory controller 125, etc. Among them, the memory controller 125, the network interface 123, and the cache consistency interface 124 are all connected to the DPU control module 121, and the DPU memory module 122 is connected to the memory controller 125. In one embodiment, the DPU memory module 122 uses an off-chip DRAM (Dynamic Random Access Memory). The remote memory pool 125 is composed of a large number of memory units and can be accessed by multiple host-side platforms. Among them, the DPU control module 121 controls the memory interaction between the DPU unit 12 and the host side 11, and between the DPU unit 12 and the remote memory pool 13. In one embodiment, local memory is used first, and pages are migrated to the DPU memory module when the local memory is insufficient, and then migrated to the remote memory pool when the DPU memory module is insufficient.

[0052] In one embodiment, the DPU unit 12 is connected to the host side 11 through the cache consistency interface 124, so that the host side CPU 111 can access the DPU memory module 122 through load / store instructions, just like accessing the local memory 112 of the host side. The DPU control module 121 receives the memory access request sent from the host side CPU through the cache consistency interface 124, and then accesses the DPU memory module through the memory controller 125 of the DPU unit. At the same time, the DPU control module 121 also returns the memory access result to the host side CPU 111 through the cache consistency interface 124.

[0053] In one embodiment, the DPU unit 12 is interconnected and interacts with the remote memory pool 13 via a network interface 123 .

[0054] During the startup phase, the host-side CPU 111 identifies the memory capacity configured by the DPU unit 12 and allocates a physical address range to it. The process is similar to the allocation of the physical address range of the local memory. In one embodiment, by modifying the relevant registers of the DPU unit 12 (CPU 111 knows the memory capacity configured by the DPU unit 12 through the registers), in practice, the physical memory capacity exposed by the DPU unit 12 to the host-side CPU 111 (i.e., the memory capacity configured by the DPU unit 12) is greater than the capacity of the DPU memory module 122 actually carried by the DPU unit 12. For example, the actual memory capacity carried by the DPU memory module 122 is 4GB. By modifying the registers exposed by the DPU unit 12 to the host-side CPU 111, the memory capacity exposed by the DPU unit 12 to the host-side CPU 111 is modified to 8GB, so that the host-side CPU 111 can use a physical memory greater than the actual memory capacity of the DPU memory module 122, solving the problem of limited extended memory capacity. Specifically, the memory capacity configured by the DPU unit 12 includes the actual capacity of the DPU memory module 111 and the capacity of the remote memory pool 13. The storage of the DPU unit 12 is combined with the storage of the remote memory pool 13, and the part of the physical memory that exceeds the actual memory capacity of the DPU memory module 122 is transferred to the remote memory pool 13. The modified larger physical address range is called the virtual physical address (VPA), and the physical address range of the physical memory of the actual memory capacity of the DPU memory module is called the true physical address (TPA). The host-side CPU 111 accesses the DPU memory module 122 through the VPA, and the DPU control module 121 accesses the actual memory through the TPA. Since the memory access request received by the DPU control module 121 from the host-side CPU 111 uses the VPA, the DPU control module 122 needs to perform address translation from the VPA to the TPA. The DPU memory can only be accessed after the DPU control module 122 obtains the corresponding TPA. The address translation process is similar to the process of translating virtual addresses to physical addresses when the host CPU 111 accesses local memory, that is, maintaining a page table that records the mapping relationship between the two. Each entry in the page table consists of a VPA number, a TPA number, and a flag bit, such as Figure 2As shown in . Since 4KB page management is used, the page number is obtained by removing the lower 12 bits of the address. The flag bit includes at least a present bit indicating whether the page is in the DPU memory module and a valid bit whether the page table entry is valid. In one embodiment, the present bit is 1, indicating that the page is in the DPU memory, and 0 indicates that the page is currently in the remote memory pool. The valid bit is 1, indicating that the page table entry is valid, otherwise it is invalid. The complete page table is stored in the specified location of the DPU memory module. In order to speed up the search, a fast table (TLB, Translation Look-aside Buffers) is used to cache some recently used page table entries. The DPU control module 121 first accesses the TLB to convert the VPA into the TPA. When there is a miss in the TLB, it accesses the complete page table and updates the TLB.

[0055] In one embodiment, when the local memory 112 on the host side is tight, the operating system 113 starts memory recycling. Different from the traditional practice of migrating recycled pages to the swap device, in this embodiment, the recycled pages are migrated to the DPU memory module 122 for storage, and the memory migration operation can be implemented using the memory migration function provided by the operating system kernel. Therefore, the migration process is much faster than migrating to the swap device, and thanks to the cache consistency interface, the host side CPU 111 will not trigger a page error interrupt when accessing the page migrated to the DPU memory module 122. When migrating a page from the local memory 112 to the DPU memory module 122, it is necessary to first allocate space in the DPU memory module 122 for the page to be migrated. Therefore, in one embodiment, the operating system kernel also maintains a data structure for recording the DPU memory allocation status. The data structure is a bitmap stored in the local memory 112. As Figure 3 As shown in , each bit corresponds to a page of the VPA address space, which is a page idle state flag. The idle state of the page can be identified by the page idle state flag. For example, if the corresponding idle state flag is 1, it means that the page has been allocated. If the corresponding idle state flag is 0, it means that the page is in an idle state and can be allocated to the page to be migrated.

[0056] When the DPU unit 12 receives a page migration request from the host side, it queries the bitmap, searches for an idle page based on the idle state flag, and allocates the page requested to be migrated by the host side to the idle page. In one embodiment, the next fit algorithm is used when allocating memory, that is, when allocating, the search starts from the next page of the idle page of the last memory allocation until a free page is found for allocation. After the page is allocated, the corresponding VPA address can be obtained directly. For example, the base address of the VPA is BASE_ADDR, and the allocated page is in the Nth position of the bitmap, then the corresponding page address is BASE_ADDR+N*0x1000. After obtaining the VPA address, the page migration function can transfer the page to be migrated to the DPU memory module, and modify the original mapping relationship of the page. After that, the host side CPU111 can access the page in the DPU memory module 122 through the normal address translation process. Afterwards, if these pages migrated to the DPU memory module 122 are released by the application, the corresponding bit of the bitmap needs to be changed to 0 to participate in the subsequent allocation process, and the page table of the DPU unit is modified at the same time. The valid bit of the page table entry corresponding to the page is 0, indicating that the page table entry is invalid.

[0057] In one embodiment, the hotness or coldness of a page can indicate how frequently a page is accessed. The more times a page is accessed per unit time, the hotter the page is. According to the principle of temporal locality, the greater the possibility that the page will continue to be accessed in the future. Through the process of migrating pages from the local memory 112 on the host side to the DPU memory module 122, some pages that would otherwise be recycled can be migrated to the DPU memory module 122. These pages stored on the DPU memory module 122 may also be frequently accessed by the CPU 111 on the host side, thereby becoming hot pages. Although the CPU's access to the DPU memory module is faster than the switching device, it is still slower than accessing the local memory. Therefore, if hot pages reside in the DPU memory module for a long time, it may also cause system performance to degrade. Therefore, in one embodiment, it is considered to migrate the hot pages in the DPU memory module 122 to the local memory 112 on the host side for storage.

[0058] To this end, it is first necessary to determine the hotness or coldness of each page stored in the DPU memory module 122. Due to the use of the cache coherence interface 124, the DPU unit 12 can sense the physical address of each memory access, rather than having to sense it through a page fault interrupt like the TPP and the operating system, so a more accurate page promotion algorithm can be designed accordingly without the overhead of page faults.

[0059] After receiving the memory access request from the cache coherence interface 124, the DPU control module 121 obtains the physical address of the request and then converts it into a physical page number, i.e., a VPA number. The DPU unit 12 is also configured with a local access count table that records the number of accesses to each VPA number. The specific structure of the local access count table is as follows: Figure 4 As shown in . Each entry in the local access count table consists of a VPA number, an access count, and a promotion flag. When the DPU control module 121 receives a memory access request, it parses the corresponding VPA number and then queries the local access count table. If the VPA number exists, the corresponding access count is increased by 1, otherwise the VPA number replaces a certain entry according to the LRU (Least recently used) algorithm. When it is monitored that the number of accesses to a page reaches a first threshold, for example 4, it indicates that the page is hot, and the page is identified as the first hot page, and the promotion flag is set to 1, indicating that it can be promoted to the local memory. Since the host-side CPU 111 can access the DPU memory module 122 through the cache consistency interface 124, the host-side CPU 111 can also access the local access count table. The host side operating system 113 accesses the local access count table through the CPU 111 at regular intervals. When the operating system 113 recognizes that the promotion flag corresponding to a certain VPA number is 1, it indicates that the first hot page is stored, and then the page migration function is used to migrate the first hot page to the local memory 112, and at the same time, the page idle state flag corresponding to the VPA number in the bitmap of the management DPU memory module 122 is modified to indicate the page idle state (for example, 0), and the corresponding page table entry of the DPU unit 12 is modified to invalid. When the hot page migration is completed, the corresponding promotion flag is changed to 0, indicating that the entry can be replaced from the local access count table later.

[0060] In one embodiment, since the VPA address range is larger than the TPA, the pages demoted from the host side 11 to the DPU unit 12 may exceed the actual memory of the DPU memory module 122, and some pages need to be demoted to the remote memory pool 13. Specifically, when it is detected that the actual memory of the DPU memory module 122 of the DPU unit is insufficient, if a page migration request is received at this time (i.e., a request to migrate the page of the host side 11 to the DPU unit 12), the DPU control module 121 filters out the second page that needs to be replaced to the remote memory pool through the LRU algorithm, and transmits the second page to the remote memory pool 13 for storage through the network interface 123. And the present bit of the page table entry corresponding to this page is modified to 0, indicating that the page is now in the remote memory pool 13. At the same time, the DPU control module 121 migrates the first hotspot page requested to be migrated from the host side 11 to the DPU memory module 122, and writes it into the space vacated by the second page in the DPU memory module 122. Later, if the host-side CPU 11 needs to access the second page migrated to the remote memory pool 13, the DPU control module 121 searches the TLB or page table. If the present bit of the page table entry corresponding to the second page is 0, indicating that the corresponding second page has been migrated to the remote memory pool 13, the DPU control module 121 accesses the corresponding page of the remote memory pool 13 through the network interface 123, obtains the return result, and passes it to the host-side CPU 111.

[0061] In one embodiment, if the DPU unit 12 frequently accesses a certain page of the remote memory pool 13, it means that the page is hot and should be migrated to the DPU memory module 122 with a smaller access delay for storage. To this end, the DPU unit 12 is also provided with a remote access count table, which records the number of accesses to each page of the remote memory pool. When the DPU control module 121 detects that the number of accesses to a page reaches a second threshold, it identifies it as a second hotspot page and promotes the second hotspot page to the DPU memory module 122 for storage. The structure of the remote access count table is consistent with the local access count table, such as Figure 4As shown in . When the DPU control module 121 accesses the remote memory pool 13 through the network interface 123, the access count of the corresponding VPA number is increased by 1. If the VPA number is not originally in the remote access count table, it is inserted according to the LRU algorithm. When the access count exceeds the second threshold, it is identified as a second hotspot page, and the promotion flag bit of the second hotspot page is set to 1. The DPU control module 121 queries the remote access count table at regular intervals, filters out the second hotspot pages based on the promotion flag bit being 1, and promotes these pages from the remote memory pool 13 to the DPU memory module 122 through the network interface. After the migration is completed, the corresponding promotion flag bit is modified to 0, and the present bit of the corresponding table entry in the TLB and page table is changed to 1, indicating that the page is currently in the DPU memory module 122.

[0062] In summary, the multi-level deaggregated memory system of the data center disclosed by the present invention cooperates to realize the data interaction method between the host side and the DPU unit, and the DPU unit and the remote memory pool, and realizes the expansion of local memory to DPU memory and then to remote memory, so that the host can obtain the extended memory while having lower memory access latency. The method realizes the migration of memory pages in two directions from the host local memory to the DPU memory and from the DPU memory to the host memory, reducing the impact of migrating pages to the DPU memory on the memory access latency; in addition, the method realizes the migration of memory pages in two directions from the DPU memory to the remote memory and from the remote memory to the DPU memory, reducing the impact of migrating pages to the remote memory on the memory access latency. Compared with the TPP system of the prior art, the present invention can realize memory migration at three levels: local memory, DPU memory, and remote memory, has better scalability, and can avoid the waste of memory resources. Compared with the Kona system, the present invention can make full use of local memory, thereby having a lower memory access latency.

[0063] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A data center multi-level de-aggregated memory system, characterized in that: Include: The host side includes: CPU, local memory connected to the CPU, and operating system connected to the CPU; A DPU unit is connected to the host side, and the DPU unit includes: a DPU control module, and a DPU memory module connected to the DPU control module; A remote memory pool connected to the DPU unit; The DPU control module controls the memory interaction between the DPU unit and the host side, and between the DPU unit and the remote memory pool.

2. The system according to claim 1, characterized in that The memory capacity configured by the DPU unit includes the actual capacity of the DPU memory module and the capacity of the remote memory pool, wherein the actual capacity of the DPU memory module corresponds to the real physical address range; the capacity of the remote memory pool corresponds to the virtual physical address range; The host side CPU accesses the DPU memory module through the virtual physical address; The DPU control module receives a memory access request using the VPA from the host-side CPU and translates the virtual physical address into a real physical address; The DPU control module accesses the DPU memory module or the remote memory pool according to the real physical address obtained by translation.

3. The method according to claim 2, characterized in that The DPU unit is configured with a page table recording the mapping relationship between the virtual physical address and the real physical address, and each item of the page table at least includes a virtual physical address number, a real physical address number and a flag bit; The flag bit at least includes a present bit and a valid bit, wherein the present bit is used to indicate that the page exists in the DPU memory module or in the remote memory pool, and the valid bit is used to indicate whether the page table entry is valid.

4. The system according to claim 3, characterized in that Use the cache to cache recently used page table entries; The DPU control module first accesses the cache to translate the virtual physical address into a real physical address, and when the cache misses, accesses the page table and updates the cache.

5. The system according to claim 2, characterized in that The local memory is configured with a bitmap, which is used to record the allocation of the DPU memory module. Each bit of the bitmap is an idle state flag bit, corresponding to a page of the virtual physical address space, and the idle state flag bit is used to identify the idle state of the corresponding page; If a page migration request is received from the host side, the bitmap is queried, an idle page is found according to the idle state flag, and the page migrated from the local memory request on the host side is allocated to the idle page, wherein the page migration request is a request to migrate the page on the host side to the DPU memory module.

6. The system according to claim 5, characterized in that When querying the bitmap, the search starts from the next page of the free page of the last allocated memory, and until a free page is found, the page requested to be migrated by the host side is allocated to the free page.

7. The system according to claim 5, characterized in that When receiving the page migration request from the host side, If it is detected that the DPU memory module is insufficient in memory, the DPU control module filters out the pages in the DPU memory module that need to be replaced to the remote memory pool, and transmits the pages to the remote memory pool storage through the network interface; and migrates the pages requested to be migrated from the host side to the DPU memory module.

8. The system according to claim 1, characterized in that The DPU unit is also configured with a local access count table for recording the number of times the host side CPU accesses each page of the DPU memory module; The DPU control module records the number of visits to each page, and if the number of visits to a page reaches a first threshold, it is identified as a first hotspot page; The operating system on the host side accesses the local access count table through the CPU at regular intervals. When the operating system identifies the existence of a first hotspot page, the first hotspot page is migrated from the DPU memory module to the local memory on the host side for storage.

9. The system according to claim 1, characterized in that The DPU unit is also configured with a remote access count table for recording the number of times the DPU unit accesses each page of the remote memory pool; When the DPU control module detects that the number of accesses to a page reaches a second threshold, it identifies the page as a second hotspot page and migrates the second hotspot page from the remote memory pool to the DPU memory module for storage.

10. The system according to claim 1, characterized in that The DPU unit is also configured with a cache consistency interface, and the host side is connected to the DPU unit via the cache consistency interface.

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