Cache consistency state maintenance method and device, multi-core processor and server

Abstract

The invention discloses a cache consistency state maintenance method and device, a multi-core processor and a server, and relates to the field of multi-core processors, the method is applied to the multi-core processor, and the method comprises the following steps: a local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor; determining a target directory from an exclusive directory and a shared directory according to a cache consistency state of a target cache line corresponding to the local cache consistency maintenance message; wherein the target directory is an exclusive directory or a shared directory; searching a target directory entry from the target directory, and adjusting the target directory entry; according to the method, the cache consistency catalog is divided into the exclusive catalog and the shared catalog, the exclusive catalog is used for recording the exclusive node information of the exclusive data, and the shared catalog is used for recording the shared node information of the shared data, so that the scale and resource occupation of the cache consistency catalog are reduced, and the query speed and efficiency of the catalog are improved.

Description

Technical Field

[0001] The present invention relates to the field of multi-core processors, and in particular to a method and device for maintaining a cache consistency state, a multi-core processor and a server. Background Art

[0002] As chips develop towards multi-core processor systems (Chip multiprocessors, CMP), the number of cores in the system continues to grow, which makes the hardware design requirements of cache consistency protocols increasingly higher, especially in terms of hardware structure, cache design, and methods to achieve consistency. Compared with bus-based cache consistency protocols, directory-based cache consistency protocols have become the preferred solution for processing multi-core processor systems due to their good scalability.

[0003] In the related technologies, cache-consistent directory design faces two main problems: First, the complexity and overhead of the directory structure. Especially in large multi-core systems, directory maintenance and query become performance bottlenecks. When the number of cores increases, the directory capacity will also increase exponentially, which not only consumes a lot of hardware, but also generates a lot of energy consumption; second, the state processing is not flexible enough, and it is impossible to efficiently use state information to optimize data access paths and reduce unnecessary communications. For example, for traditional cache consistency protocols, such as MESI (an abbreviation of the four states of Modified, Exclusive, Shared, and Invalid) protocol, the information that may be hidden behind some states (such as invalid states) is ignored, such as whether the data is being exclusively used or shared elsewhere. Therefore, how to provide a new cache-consistent directory structure to reduce the resource usage of the directory and improve the query speed and efficiency of the directory is a problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a method, device, computer program product, multi-core processor and server for maintaining cache consistency state, so as to reduce the resource occupation of cache consistency directory and improve the query speed and query efficiency of the directory.

[0005] In order to solve the above technical problems, the present invention provides a method for maintaining cache consistency state, which is applied to a multi-core processor, comprising:

[0006] The local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor;

[0007] According to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message, the target directory is determined from the exclusive directory and the shared directory; wherein the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line;

[0008] The target directory entry is searched from the target directory, and the target directory entry is adjusted.

[0009] On the other hand, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state and an invalid shared state, the invalid exclusive state indicates that the cache data in the target cache line is in an invalid state in the local processor node and the corresponding data is in an exclusive state in a certain remote processor node in the multi-core processor, and the invalid shared state indicates that the cache data in the target cache line is in an invalid state in the local processor node and the corresponding data is not in an exclusive state in a certain remote processor node in the multi-core processor;

[0010] The determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes:

[0011] If the cache coherence state of the target cache line is the invalid exclusive state, determining the exclusive directory as the target directory;

[0012] If the cache coherence state of the target cache line is the invalid shared state, the shared directory is determined to be the target directory.

[0013] On the other hand, the preset cache consistency state further includes a modified state, an exclusive state, and a shared state, and determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes:

[0014] If the cache coherence state of the target cache line is the invalid exclusive state, the modified state or the exclusive state, determining that the exclusive directory is the target directory;

[0015] If the cache coherence state of the target cache line is the shared state or the invalid shared state, the shared directory is determined to be the target directory.

[0016] On the other hand, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid state; and determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes:

[0017] If the cache coherence state of the target cache line is the invalid state, determining whether the cache data in the target cache line is in an exclusive state in a certain remote processor node in the multi-core processor;

[0018] If so, determining the exclusive directory as the target directory;

[0019] If not, the shared directory is determined to be the target directory.

[0020] On the other hand, the data access address in the current directory entry in the exclusive directory is the memory address information in the corresponding cache line in the private cache of the exclusive node corresponding to the current directory entry, and the identifier of the exclusive node in the current directory entry in the exclusive directory is the processor core code; wherein the current directory entry is any directory entry in the exclusive directory.

[0021] On the other hand, the memory address information includes a tag, an index, and an offset.

[0022] On the other hand, the cache consistency state of the exclusive node corresponding to each directory entry in the exclusive directory includes an exclusive state and a modified state; the cache consistency state of the exclusive node in the current directory entry is a 1-bit flag.

[0023] On the other hand, the identifiers and cache consistency states of all shared nodes in the current directory entry in the shared directory are cache consistency states corresponding to all processor nodes in the multi-core processor arranged in a preset node sorting order.

[0024] On the other hand, the preset node sorting order is the order of processor core coding sorting from high byte to low byte or from low byte to high byte.

[0025] On the other hand, determining the target directory from the exclusive directory and the shared directory according to the cache coherence state of the target cache line corresponding to the local cache coherence maintenance message includes:

[0026] If the data access address in the local cache consistency maintenance message does not match the target cache line, query the directory entry corresponding to the data access address in the local cache consistency maintenance message from the exclusive directory and the shared directory, and adjust the queried directory entry;

[0027] If the data access address in the local cache coherence maintenance message matches the target cache line, the target directory is determined from the exclusive directory and the shared directory according to the cache coherence state of the target cache line.

[0028] In another aspect, the method further comprises:

[0029] The local processor node receives a remote cache consistency maintenance message sent by a current remote processor node; wherein the current remote processor node is any processor node other than the local processor node in the multi-core processor;

[0030] Determine a maintenance query directory according to the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message; wherein the maintenance query directory is the exclusive directory and / or the shared directory;

[0031] The directory entry corresponding to the data access address in the remote cache consistency maintenance message is searched from the maintenance query directory, and the found directory entry is adjusted.

[0032] On the other hand, the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state, an invalid shared state, a modified state, an exclusive state, and a shared state. The determining the maintenance query directory according to the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message includes:

[0033] If the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message is the invalid exclusive state, the modified state or the exclusive state, determining that the exclusive directory is the maintenance query directory;

[0034] If the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message is the shared state or the invalid shared state, the shared directory is determined to be the maintenance query directory.

[0035] In another aspect, the target cache line includes a data access address, a cache coherence state, and cache data.

[0036] On the other hand, the number of the exclusive directory and the number of the shared directory in the multi-core processor are both 1.

[0037] In another aspect, the adjusting the target directory item includes:

[0038] Determining whether a directory conversion operation is required according to the adjusted cache coherence state corresponding to the target cache line;

[0039] If the directory conversion operation is required, the target directory entry is deleted in the target directory, and a directory entry corresponding to the target directory entry is added to a non-target directory according to the adjusted cache consistency state; wherein the non-target directory is a directory other than the target directory in the exclusive directory and the shared directory;

[0040] If the directory conversion operation is not required, the target directory entry is adjusted according to the adjusted cache consistency state.

[0041] On the other hand, the cache coherence state of the target cache line is a shared state, and the adjusted cache coherence state corresponding to the target cache line is a modified state;

[0042] The step of deleting the target directory entry in the target directory and adding a directory entry corresponding to the target directory entry in a non-target directory according to the adjusted cache consistency state includes:

[0043] Delete the target directory entry in the shared directory, and add a directory entry corresponding to the target directory entry in the exclusive directory; wherein the data access address in the directory entry corresponding to the target directory entry is the data access address of the target directory entry, the identifier of the exclusive node in the directory entry corresponding to the target directory entry is the processor core code of the local processor node, and the cache consistency state of the exclusive node in the directory entry corresponding to the target directory entry is the modified state.

[0044] The present invention also provides a cache consistency state maintenance device, which is applied to a local processor node in a multi-core processor, comprising:

[0045] A local acquisition module, used to acquire a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor;

[0046] A directory determination module, for determining a target directory from an exclusive directory and a shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message; wherein the target directory is an exclusive directory or a shared directory; each directory entry in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory entry in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory entry is a directory entry in the exclusive directory or the shared directory corresponding to the target cache line;

[0047] The directory maintenance module is used to search for the target directory item from the target directory and adjust the target directory item.

[0048] The present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the cache consistency state maintenance method as described above when executed by a processor.

[0049] The present invention also provides a multi-core processor, comprising: a preset number of processor nodes, an exclusive directory, and a shared directory; wherein the preset number is greater than or equal to 2, and the processor node comprises a processor core and a private cache;

[0050] The processor node is used to obtain a local cache consistency maintenance message; determine the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message; search for the target directory item from the target directory, and adjust the target directory item; wherein the target directory is the exclusive directory or the shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of the exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the local private cache of the processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line.

[0051] On the other hand, the exclusive directory and the shared directory are both set in the shared cache of the preset number of processor nodes.

[0052] In addition, the present invention also provides a server, comprising: the multi-core processor as described above.

[0053] A method for maintaining a cache consistency state provided by the present invention is applied to a multi-core processor, comprising: a local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor; according to the cache consistency state of a target cache line corresponding to the local cache consistency maintenance message, a target directory is determined from an exclusive directory and a shared directory; wherein the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line; searching for the target directory item from the target directory, and adjusting the target directory item.

[0054] It can be seen that the present invention divides the cache consistency directory into an exclusive directory and a shared directory, uses the exclusive directory to record the information of the exclusive nodes that occupy the data alone, and uses the shared directory to record the information of the shared nodes that share the data, which can reduce the size and resource occupation of the cache consistency directory and improve the query speed and efficiency of the directory. In addition, the present invention also provides a cache consistency state maintenance device, a computer program product, a multi-core processor and a server, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0056] Figure 1 A flowchart of a method for maintaining cache consistency state provided by an embodiment of the present invention;

[0057] Figure 2 A schematic diagram of the structure of a cache line provided by an embodiment of the present invention;

[0058] Figure 3 A schematic diagram of the structure of an exclusive directory provided by an embodiment of the present invention;

[0059] Figure 4 A schematic diagram of the structure of a shared directory provided by an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of a partial architecture of a multi-core processor provided by an embodiment of the present invention;

[0061] Figure 6 A schematic diagram of a process for local maintenance of a cache consistency state provided by an embodiment of the present invention;

[0062] Figure 7 A flowchart of another method for maintaining cache consistency state provided by an embodiment of the present invention;

[0063] Figure 8 A schematic diagram of a process of remote maintenance of a cache consistency state provided by an embodiment of the present invention;

[0064] Fig. 9 A structural block diagram of a cache consistency state maintenance device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Please refer to Figure 1 , Figure 1 A flow chart of a method for maintaining cache consistency state provided by an embodiment of the present invention. The method is applied to a multi-core processor and includes:

[0067] Step 101: A local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in a multi-core processor.

[0068] Among them, the local processor node in this embodiment can be any processor node in a multi-core processor, and each processor node can include one or more processor cores or a processor core and a private cache (such as a first-level L1 cache), that is, each processor node of the multi-core processor can complete the process of locally maintaining cache consistency through the method provided in this embodiment.

[0069] Correspondingly, the local cache consistency maintenance message in this embodiment can be a message generated or triggered by a local processor node for maintaining the cache consistency state of a cache line. The specific content of the local cache consistency maintenance message in this embodiment can be set by the designer according to practical scenarios and user needs. For example, the local cache consistency maintenance message can include the address of the data that needs to be maintained (i.e., the data access address); for example, the address in the storage device (such as the memory) of the cache data (such as the memory block) stored in the cache line (i.e., the target cache line) in the private cache of the local processor node. Each processor node in the multi-core processor can access the memory and read the data in the memory into its own private cache. Figure 2 As shown, the data access address 110 may include a tag, an index, and an offset of the cache data in a storage device (such as a memory). The local cache consistency maintenance message may also include data adjustment control information and / or state adjustment information (such as adjusted cache consistency state) for the cache data in the target cache line. As long as the local processor node can adjust and maintain the cache consistency of the corresponding data according to the acquired local cache consistency maintenance message, this embodiment does not impose any restrictions on this.

[0070] Correspondingly, the specific method for the local processor node to obtain the local cache consistency maintenance message in this embodiment can be set by the designer according to the practical scenario and user needs. For example, it can be implemented in the same or similar manner as the method for each processor node in the multi-core processor in the prior art to obtain the local cache consistency maintenance message. This embodiment does not impose any restrictions on this.

[0071] Step 102: According to the cache coherence state of the target cache line corresponding to the local cache coherence maintenance message, a target directory is determined from the exclusive directory and the shared directory.

[0072] Among them, the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes its corresponding data access address, the identifier of the exclusive node and the cache consistency state of the exclusive node, and each directory item in the shared directory includes its corresponding data access address and the identifiers and cache consistency state of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory item is the directory item in the exclusive directory or shared directory corresponding to the target cache line.

[0073] It can be understood that the target cache line in this embodiment can be the cache line corresponding to the local cache consistency maintenance message stored in the private cache of the local processor node, such as the cache line matched by the data access address in the local cache consistency maintenance message. The specific structure of the target cache line in this embodiment, that is, the specific structure of the cache line in the private cache of each processor core of the multi-core processor, can be set by the designer according to practical scenarios and user needs, such as Figure 2 As shown, the target cache line may include a data access address 110 (such as memory address information), a cache consistency state, and cache data; wherein the data access address 110 may be an address in a storage device (such as a memory) corresponding to the cache data, such as the data access address 110 may include a tag, an index, and an offset, so that the corresponding memory block in the memory can be accessed through the tag, the index, and the offset; accordingly, according to different cache design methods, the degree of association is different, and the structure of the data access address 110 can be set accordingly.

[0074] Correspondingly, the cache data in the target cache line may be the data content (such as original data or modified data) corresponding to the data block (such as memory block) read from the storage (such as memory). The cache consistency state in the target cache line may be the state in the cache consistency protocol corresponding to the cache data in the target cache line. The specific setting of the cache consistency state in this embodiment, that is, the specific type of cache consistency protocol used in this embodiment, can be set by the designer according to the practical scenario and user needs. For example, the cache consistency protocol can adopt ESI (abbreviation of Exclusive, Shared and Invalid), MESI, MOESI (abbreviation of Modified, Owned, Exclusive, Shared and Invalid), CHI (Cache Hub Interface, consistency hub interface), CCIX (Cache Coherent Interconnect for Accelerators, a high-performance interconnect protocol) or ACE (AXI Coherency Extensions, an advanced cache consistency protocol) and other protocols and related protocols. For example, when the cache coherence protocol adopts the ESI protocol, the cache coherence state in the target cache line can be a modified state (M state), a shared state (S state), or an invalid state (I state); when the cache coherence protocol adopts the MESI protocol, the cache coherence state in the target cache line can be a modified state (M state), an exclusive state (E state), a shared state (S state), or an invalid state (I state).

[0075] Furthermore, since the cache consistency protocol in the related art fails to fully consider the cache line states of the remaining processor cores that may exist in the local invalid state (such as the above-mentioned I state), it is necessary to record a large number of states of all processor cores, thereby increasing the directory capacity; and for 5 or more cache consistency state designs, 3 bits of capacity are often required to distinguish each state, and 3 bits often have redundant codes that are not used. In this embodiment, the invalid state can be further expanded into two invalid states, namely, the invalid exclusive state (IU) and the invalid shared state (IE), so as to achieve more precise control of the cache line state; wherein, the invalid exclusive state can represent a local invalid state and a processor core uses it alone (such as an exclusive state or a modified state); the invalid shared state can represent an invalid state other than the invalid exclusive state, such as representing a local invalid state and being shared by at least one processor core. For example, when the cache data in the target cache line is in an invalid exclusive state, it may indicate that the cache data is in an invalid state in the local processor node and the corresponding data (such as a memory block) is in an exclusive state (or a modified state) in a remote processor node in the multi-core processor; when the cache data in the target cache line is in an invalid shared state, it may indicate that the cache data in the target cache line is in an invalid state in the local processor node and the corresponding data is not in an exclusive state (or a modified state) in a remote processor node in the multi-core processor, such as the corresponding data is in a shared state in at least one remote processor node in the multi-core processor.

[0076] It can be understood that in this embodiment, for the cache consistency environment of a multi-core processor, the cache consistency directory is divided into an exclusive directory (U Dir) and a shared directory (S Dir). Among them, the exclusive directory can be used to record the cache line corresponding to the data block used exclusively by a processor core, that is, the directory structure of the exclusive directory can only record the cache line of the processor node (or processor core) with an exclusive state. Since it is in an exclusive state, it means that the cache line state can only be a unique and clean (Unique Clean, UC) state or a unique and dirty (Unique Dirty, UD) state; accordingly, except for UC and UD, the cache consistency state that records the unique state in other cache consistency protocols and belongs to the exclusive category can be recorded by this directory structure. Since nearly 70% of the cache line data states in the data blocks generated during the execution of the program by the processor core are exclusive, the exclusive state of the local processor core, as well as the invalid state of the local core and the exclusive state of the remaining cores are fully considered, and recorded uniformly in the exclusive directory, can greatly reduce the directory capacity.

[0077] The specific directory structure of the exclusive directory in this embodiment can be set by the designer according to practical scenarios and user needs, such as Figure 3As shown, each directory entry of the exclusive directory can include a data access address (addr), an exclusive node identifier (exclusive state node) and a cache consistency state (Uni) of the exclusive node; the data access address in the current directory entry in the exclusive directory is the memory address information in the corresponding cache line in the private cache of the exclusive node corresponding to the current directory entry, such as Figure 2 The data access address 110 shown includes a label, an index and an offset; the exclusive node can be a processor node that exclusively uses the data block corresponding to the memory address information; the identifier of the exclusive node in the current directory entry in the exclusive directory is the processor core code; wherein the current directory entry is any directory entry in the exclusive directory.

[0078] Correspondingly, the cache consistency state of the exclusive node in the current directory entry in the exclusive directory can be used to indicate the cache consistency state of the data block corresponding to the data access address in the current directory entry in the exclusive node; for example, when the cache consistency state of the exclusive node corresponding to each directory entry in the exclusive directory includes an exclusive state (E state) and a modified state (M state); the cache consistency state of the exclusive node in the current directory entry is a 1-bit identifier (i.e., 1 or 0) to record whether the cache consistency state of the exclusive node is in the E state or the M state.

[0079] Correspondingly, the shared directory can be used to record cache lines outside the exclusive directory, such as recording the cache lines of all processor cores that share a data block. The specific directory structure of the shared directory in this embodiment can be set by the designer according to practical scenarios and user needs. For example, each directory item in the shared directory includes its corresponding data access address and the identifier and cache consistency status of all shared nodes; wherein the shared node can be the processor node that shares the data block corresponding to the data access address. Figure 4As shown, each directory entry of the shared directory may include a data access address (addr) and a cache consistency state (node ​​state) corresponding to each of the processor nodes in the multi-core processor arranged in a preset node sorting order. That is to say, in this embodiment, the corresponding cache consistency state of all the processor nodes arranged in a preset node sorting order can be set to indicate the identification and cache consistency state of all the corresponding shared nodes, so as to reduce the occupied space of the shared directory; for example, when the cache consistency state of the cache line includes a modified state, an exclusive state, a shared state, and an invalid state, each directory entry in the shared directory not only records the cache consistency state of all the processor nodes in the cache line corresponding to the corresponding data access address, but also uses 1 bit to mark whether each processor node is in a shared state or an invalid state; in other embodiments, 2 bits can also be used to mark which shared state or invalid state each processor node is in, so as to realize the record of the precise state division of the relevant cache consistency protocol. That is, each cache consistency state in the cache consistency state corresponding to each of the processor nodes arranged in a preset node sorting order in each directory entry in the shared directory can be 1 bit or 2 bits.

[0080] Accordingly, the preset node sorting order can be set by the designer, such as the order of sorting according to the codes of each processor core (i.e., the processor core code), such as the order of sorting the processor core code from high byte to low byte or from low byte to high byte. In other words, each directory entry in the shared directory can record the cache consistency state corresponding to all processor nodes in the corresponding fields in the order of sorting the processor core code, so that the cache consistency state (such as shared state or invalid state) of each processor node and the corresponding cache line owned by each processor node can be quickly located in this order.

[0081] It can be understood that in this step 102, when the local processor node matches the data access address in the local cache consistency maintenance message to a cache line in its own private cache (i.e., the target cache line), and needs to maintain the corresponding cache consistency directory (i.e., the exclusive directory or the shared directory), the target directory is determined from the exclusive directory and the shared directory based on the cache consistency state of the matched cache line to avoid the need to query the exclusive directory and the shared directory, thereby improving query efficiency.

[0082] Correspondingly, for the local processor node in this step, according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message, the specific method of determining the target directory from the exclusive directory and the shared directory can be set by the designer according to practical scenarios and user needs. For example, in order to facilitate the determination of the target directory, the invalid state (I state) is divided into an invalid exclusive state (IU state) and an invalid shared state (IS state). That is, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state and an invalid shared state. In this step, the processor can determine the exclusive directory as the target directory when the cache consistency state of the target cache line is an invalid exclusive state; and determine the shared directory as the target directory when the cache consistency state of the target cache line is an invalid shared state. For example, if Figure 3 and Figure 4 As shown, in this embodiment, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state, an invalid shared state, a modified state, an exclusive state and a shared state. That is to say, the MESI protocol can be adopted in this embodiment, and the invalid state of the MESI protocol is divided into an invalid exclusive state and an invalid shared state. The local processor node can determine that the exclusive directory is the target directory when the cache consistency state of the target cache line is an invalid exclusive state (IU state), a modified state (M state) or an exclusive state (E state); when the cache consistency state of the target cache line is a shared state (S state) or an invalid shared state (IS state), the shared directory is determined as the target directory.

[0083] Correspondingly, in other embodiments, in this step, the local processor node may also determine the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line and the cache consistency states of other processor nodes corresponding to the cache data in the target cache line. For example, when the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid state, the local processor node may determine whether the cache data in the target cache line is in an exclusive state in a remote processor node in the multi-core processor when the cache consistency state of the target cache line is in an invalid state, that is, whether the data block (such as a memory block) corresponding to the cache data is in an exclusive state in a remote processor node; if so, the exclusive directory is determined to be the target directory; if not, the shared directory is determined to be the target directory.

[0084] It should be noted that, for the case where the data access address in the local cache consistency maintenance message in this embodiment does not match the target cache line, the designer can set it by himself, such as directly querying the directory item corresponding to the data access address in the local cache consistency maintenance message from the exclusive directory and the shared directory, and adjusting the queried directory item. That is to say, in this step, the local processor can query the directory item corresponding to the data access address in the local cache consistency maintenance message from the exclusive directory and the shared directory when the data access address in the local cache consistency maintenance message does not match the target cache line, and adjust the queried directory item; when the data access address in the local cache consistency maintenance message matches the target cache line, if the cache consistency maintenance of the directory is required, the target directory is determined from the exclusive directory and the shared directory according to the cache consistency state of the target cache line; if the cache consistency maintenance of the directory is not required, the remaining operations can be completed on the target cache line.

[0085] Step 103: Search the target directory item from the target directory and adjust the target directory item.

[0086] It can be understood that in this step, the local processor node can use the local cache consistency maintenance message or the data access address in the target cache line to search for the corresponding directory entry (i.e., the target directory entry) from the target directory, and adjust the found target directory entry to complete the cache consistency maintenance of the directory.

[0087] Correspondingly, the specific method of adjusting the target directory entry in this step can be set by the designer according to practical scenarios and user needs. For example, it can be implemented in the same or similar manner as the cache consistency directory adjustment method in the related technology. For example, the local processor node can determine whether a directory conversion operation is required based on the adjusted cache consistency state corresponding to the target cache line; if a directory conversion operation is required, the target directory entry is deleted from the target directory, and according to the adjusted cache consistency state, a directory entry corresponding to the target directory entry is added to the non-target directory; wherein the non-target directory is a directory other than the target directory in the exclusive directory and the shared directory; if a directory conversion operation is not required, the target directory entry is adjusted according to the adjusted cache consistency state.

[0088] That is to say, the local processor node can determine whether the directory entry needs to be converted and stored between the exclusive directory and the shared directory (i.e., the directory conversion operation) according to the state to which the target cache line in the target directory entry needs to be adjusted, and thus perform corresponding operations to complete the cache consistency maintenance of the directory. For example, the cache consistency state of the target cache line is a shared state, and the adjusted cache consistency state corresponding to the target cache line is a modified state, that is, the directory entry corresponding to the target cache line in the shared directory needs to be converted to the exclusive directory for storage, and the local processor node can delete the target directory entry in the shared directory and add the directory entry corresponding to the target directory entry in the exclusive directory; wherein, the data access address in the directory entry corresponding to the target directory entry is the data access address of the target directory entry, the identifier of the exclusive node in the directory entry corresponding to the target directory entry is the processor core code of the local processor node, and the cache consistency state of the exclusive node in the directory entry corresponding to the target directory entry is a modified state.

[0089] For example, in some embodiments, Figure 5 As shown, a processor node of a multi-core processor may include two processor cores (cores) and respective private caches L1 and a shared cache L2, and may also include two independent cache consistency directories, namely, a unique directory (U Dir) and a shared directory (S Dir). Figure 5 The solid line portion shown may represent the path taken by a cache consistency maintenance message or operation, while the dashed line portion may represent the path taken by a non-cache consistency maintenance message or operation. The node may communicate cache consistency maintenance messages or non-cache consistency maintenance messages with other remote processor nodes or cores by connecting to the interconnect structure. In other embodiments, Figure 5 The structure shown can be designed with more cores and a more complex multi-level cache structure; at the same time, in the structure of the above cache consistency directory, after the cache consistency state is updated or modified due to the cache consistency maintenance operation, the cache consistency state recorded in the exclusive directory (U Dir) and the shared directory (S Dir) will be converted or re-written through the connection between the two directories.

[0090] like Figure 6As shown, when the local cache consistency maintenance message searches for cache data at the private cache L1, when the cache line of a certain address does not hit, if the message needs to maintain cache consistency, it will enter the exclusive directory and the shared directory for query at the same time, and the local processor node can perform other operations based on whether the matching address is queried. When the cache line hits, if there is no need to perform cache consistency maintenance, the remaining operations are completed at the cache. If cache consistency needs to be further maintained, the cache line state recorded by the corresponding address in the message is further judged, and the corresponding directory is entered according to different states: when the state is M, E, and IU, the exclusive directory is entered for cache consistency maintenance; when the state is S and IS, the shared directory is entered for cache consistency maintenance. After entering and accessing the above directory, consistency maintenance is performed according to the query results, and the matching directory items are updated or modified, that is, according to the state characteristics of the updated or modified directory items, it is necessary to determine whether the directory item needs to be converted and stored between the exclusive directory and the shared directory. If all directory items are not matched and the directory item is missing, the next level or the remaining cache structure or directory structure can be entered to perform corresponding operations to complete the processing of the missing directory item.

[0091] It should be noted that this embodiment is demonstrated by taking the cache consistency directory structure setting of an exclusive directory and a shared directory in a multi-core processor as an example. For the setting of multiple directory structures in a multi-level cache architecture, or the distributed directory structure setting of on-chip interconnected nodes (such as setting an exclusive directory and a shared directory in each processor node), the corresponding settings can be made in a manner similar to the method provided in this embodiment, and this embodiment does not impose any restrictions on this.

[0092] In this embodiment, the embodiment of the present invention divides the cache consistency directory into an exclusive directory and a shared directory, uses the exclusive directory to record the exclusive node information that exclusively occupies the data, and uses the shared directory to record the shared node information that shares the data, which can reduce the scale and resource occupancy of the cache consistency directory and improve the query speed and efficiency of the directory.

[0093] Based on the above embodiment, the embodiment of the present invention also provides another cache consistency state maintenance method to implement cache consistency state maintenance of remote cache consistency maintenance messages. Figure 7 , Figure 7 A flowchart of another cache consistency state maintenance method provided by an embodiment of the present invention. The method can be applied to a multi-core processor, including:

[0094] Step 201: A local processor node receives a remote cache consistency maintenance message sent by a current remote processor node; wherein the current remote processor node is any processor node other than the local processor node in a multi-core processor.

[0095] It should be noted that the remote cache consistency maintenance message can be a cache consistency maintenance message sent by any remote processor node (i.e., the current remote processor node) to the local processor node. The remote cache consistency maintenance message can include the data access address and can also include the cache consistency state corresponding to the current remote processor node, i.e., the cache consistency state of the data block corresponding to the data access address in the current remote processor node (such as the cache consistency state before modification).

[0096] Step 202: Determine a maintenance query directory according to the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message; wherein the maintenance query directory is an exclusive directory and / or a shared directory.

[0097] It can be understood that in this step, the local processor node can determine the maintenance query directory from the exclusive directory and the shared directory according to the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message. For example, when the cache consistency state is M state, E state or IU state, the exclusive directory can be determined as the maintenance query directory to enter the exclusive directory for cache consistency maintenance; when the cache consistency state is S state or IS state, the shared directory can be determined as the maintenance query directory to enter the shared directory for cache consistency maintenance. In adopting certain cache consistency protocols, certain cache consistency states may require parallel queries of the above two directories to perform corresponding cache consistency maintenance; for example, when the cache consistency state is I state (invalid state), the exclusive directory and the shared directory can be determined as the maintenance query directory. This embodiment does not impose any restrictions on this.

[0098] Step 203: Search the maintenance query directory for a directory entry corresponding to the data access address in the remote cache consistency maintenance message, and adjust the found directory entry.

[0099] Among them, in this step, the local processor node can use the data access address in the remote cache consistency maintenance message to find the corresponding directory entry from the maintenance query directory, and adjust the found directory entry to complete the remote maintenance of the cache consistency of the directory.

[0100] Correspondingly, the specific method for adjusting the found directory items in this step can be set by the designer, such as setting it in the same or similar manner as the method for adjusting the target directory items in the target directory in the above embodiment. For example, the local processor node can determine whether a directory conversion operation is required based on the adjusted cache consistency state in the remote cache consistency maintenance message; if a directory conversion operation is required, the found directory item is deleted from the maintenance query directory, and according to the adjusted cache consistency state, a directory item corresponding to the found directory item is added to another directory; if a directory conversion operation is not required, the found directory item is adjusted according to the adjusted cache consistency state.

[0101] like Figure 8 As shown, when the remote cache consistency maintenance message enters the local processor node, the local processor node determines the type of directory entered through the remote core state in the message (i.e., the cache consistency state corresponding to the current remote processor node). For example, when the remote core state carried in the message is M, E, or IU, the exclusive directory is entered for query; when the state is S or IS, the shared directory is entered for query. Afterwards, consistency maintenance is performed based on the query results in the directory, such as updating or modifying the matching directory items, and determining whether the directory items need to be converted and stored between the exclusive directory and the shared directory. If all directory items are not matched and the directory items are missing, the next level or the remaining cache structure or directory structure can be entered to perform corresponding operations to complete the processing of the missing directory items.

[0102] In this embodiment, the embodiment of the present invention divides the cache consistency directory into an exclusive directory and a shared directory, thereby improving the directory query speed and query efficiency of remote cache consistency maintenance.

[0103] Corresponding to the above method embodiment, an embodiment of the present invention further provides a cache consistency state maintenance device. The cache consistency state maintenance device described below and the cache consistency state maintenance method described above can refer to each other.

[0104] Please refer to Fig. 9 , Fig. 9 A structural block diagram of a cache consistency state maintenance device provided by an embodiment of the present invention. The device is applied to a local processor node in a multi-core processor and may include:

[0105] A local acquisition module 10 is used to acquire a local cache consistency maintenance message; wherein the local processor node is any processor node in a multi-core processor;

[0106] The directory determination module 20 is used to determine the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message; wherein the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line;

[0107] The directory maintenance module 30 is used to search for a target directory item in the target directory and adjust the target directory item.

[0108] In some embodiments, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state and an invalid shared state. The invalid exclusive state indicates that the cache data in the target cache line is invalid in the local processor node and the corresponding data is exclusive in a certain remote processor node in the multi-core processor. The invalid shared state indicates that the cache data in the target cache line is invalid in the local processor node and the corresponding data is not exclusive in a certain remote processor node in the multi-core processor.

[0109] The directory determination module 20 may be specifically configured to determine the exclusive directory as the target directory if the cache coherence state of the target cache line is an invalid exclusive state; and to determine the shared directory as the target directory if the cache coherence state of the target cache line is an invalid shared state.

[0110] In some embodiments, the preset cache consistency state also includes a modified state, an exclusive state and a shared state. The directory determination module 20 can be specifically used to determine the exclusive directory as the target directory if the cache consistency state of the target cache line is an invalid exclusive state, a modified state or an exclusive state; if the cache consistency state of the target cache line is a shared state or an invalid shared state, determine the shared directory as the target directory.

[0111] In some embodiments, the cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid state; the directory determination module 20 can be specifically used to determine whether the cache data in the target cache line is in an exclusive state in a remote processor node in the multi-core processor if the cache consistency state of the target cache line is an invalid state; if so, determine the exclusive directory as the target directory; if not, determine the shared directory as the target directory.

[0112] In some embodiments, the data access address in the current directory entry in the exclusive directory is the memory address information in the corresponding cache line in the private cache of the exclusive node corresponding to the current directory entry, and the identifier of the exclusive node in the current directory entry in the exclusive directory is the processor core code; wherein the current directory entry is any directory entry in the exclusive directory.

[0113] In some embodiments, the memory address information includes a tag, an index, and an offset.

[0114] In some embodiments, the cache consistency state of the exclusive node corresponding to each directory entry in the exclusive directory includes an exclusive state and a modified state; the cache consistency state of the exclusive node in the current directory entry is a 1-bit identifier.

[0115] In some embodiments, the identifiers and cache consistency states of all shared nodes in the current directory entry in the shared directory are cache consistency states corresponding to all processor nodes in the multi-core processor arranged in a preset node sorting order.

[0116] In some embodiments, the preset node sorting order is the order of processor core encoding sorting from high byte to low byte or from low byte to high byte.

[0117] In some embodiments, the directory determination module 20 may include:

[0118] A direct query submodule is used to query the directory entry corresponding to the data access address in the local cache consistency maintenance message from the exclusive directory and the shared directory if the data access address in the local cache consistency maintenance message does not match the target cache line, and adjust the queried directory entry;

[0119] The directory determination submodule is used to determine the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line if the data access address in the local cache consistency maintenance message matches the target cache line.

[0120] In some embodiments, the apparatus may further include:

[0121] A remote receiving submodule, used for receiving a remote cache consistency maintenance message sent by a current remote processor node; wherein the current remote processor node is any processor node other than a local processor node in a multi-core processor;

[0122] A remote query submodule, used to determine a maintenance query directory according to a cache consistency state corresponding to a current remote processor node in a remote cache consistency maintenance message; wherein the maintenance query directory is an exclusive directory and / or a shared directory;

[0123] The remote adjustment submodule is used to search the maintenance query directory for the directory entry corresponding to the data access address in the remote cache consistency maintenance message, and adjust the found directory entry.

[0124] In some embodiments, the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state, an invalid shared state, a modified state, an exclusive state, and a shared state;

[0125] The remote query submodule can be specifically used to determine the exclusive directory as the maintenance query directory if the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message is an invalid exclusive state, a modified state or an exclusive state; if the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message is a shared state or an invalid shared state, then determine the shared directory as the maintenance query directory.

[0126] In some embodiments, the target cache line includes a data access address, a cache coherency state, and cache data.

[0127] In some embodiments, the number of exclusive directories and shared directories in a multi-core processor is both 1.

[0128] In some embodiments, the directory maintenance module 30 may include:

[0129] A conversion determination submodule, used to determine whether a directory conversion operation is required according to the adjusted cache coherence state corresponding to the target cache line;

[0130] A conversion submodule, for deleting a target directory entry in a target directory if a directory conversion operation is required, and adding a directory entry corresponding to the target directory entry in a non-target directory according to the adjusted cache consistency state; wherein the non-target directory is a directory other than the target directory in the exclusive directory and the shared directory;

[0131] The adjustment submodule is used to adjust the target directory entry according to the cache consistency state after the adjustment if the directory conversion operation is not required.

[0132] In some embodiments, the cache coherence state of the target cache line is a shared state, and the adjusted cache coherence state corresponding to the target cache line is a modified state;

[0133] The conversion submodule can be specifically used to delete the target directory entry in the shared directory and add a directory entry corresponding to the target directory entry in the exclusive directory; wherein the data access address in the directory entry corresponding to the target directory entry is the data access address of the target directory entry, the identifier of the exclusive node in the directory entry corresponding to the target directory entry is the processor core code of the local processor node, and the cache consistency state of the exclusive node in the directory entry corresponding to the target directory entry is a modified state.

[0134] In this embodiment, the embodiment of the present invention divides the cache consistency directory into an exclusive directory and a shared directory, uses the exclusive directory to record the exclusive node information that exclusively occupies the data, and uses the shared directory to record the shared node information that shares the data, which can reduce the scale and resource occupancy of the cache consistency directory and improve the query speed and efficiency of the directory.

[0135] Corresponding to the above method embodiment, an embodiment of the present invention further provides a multi-core processor. The multi-core processor described below and the method for maintaining a cache consistency state described above can refer to each other.

[0136] A multi-core processor, comprising: a preset number of processor nodes, an exclusive directory, and a shared directory; wherein the preset number is greater than or equal to 2, and the processor node comprises a processor core and a private cache;

[0137] The processor node is used to obtain a local cache consistency maintenance message; according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message, the target directory is determined from the exclusive directory and the shared directory; the target directory item is searched from the target directory, and the target directory item is adjusted; wherein the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes its corresponding data access address, the identifier of the exclusive node and the cache consistency state of the exclusive node, and each directory item in the shared directory includes its corresponding data access address and the identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the local private cache of the processor node, and the target directory item is the directory item in the exclusive directory or the shared directory corresponding to the target cache line.

[0138] It is understandable that any processor node in the multi-core processor in this embodiment can be used as the local processor node in the above embodiment to maintain the cache consistency state. This embodiment does not limit the number of processor cores in the processor node. For example, the processor node can include 1 processor core; Figure 6 The illustrated embodiment includes two processor cores (Core 1 and Core 2) or may include more processor cores.

[0139] In some embodiments, both the exclusive directory and the shared directory are set in the shared cache of a preset number of processor nodes, such as in the last level cache of a multi-core processor.

[0140] In some embodiments, the number of exclusive directories and shared directories may both be 1.

[0141] Corresponding to the above method embodiment, the embodiment of the present invention further provides a server. The server described below and the method for maintaining a cache consistency state described above can refer to each other.

[0142] A server includes: a multi-core processor as provided in the above embodiment.

[0143] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer program product. The computer program product described below and the method for maintaining a cache consistency state described above can refer to each other.

[0144] A computer program product includes a computer program / instruction, which, when executed by a processor, implements the steps of the cache consistency state maintenance method provided by the above method embodiment.

[0145] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium described below and the cache coherence state maintenance method described above can refer to each other.

[0146] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for maintaining the cache consistency state of the above method embodiment.

[0147] The computer-readable storage medium may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program codes.

[0148] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device, computer program product, multi-core processor, server and computer-readable storage medium disclosed in the embodiment, since they correspond to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0149] The above is a detailed introduction to a cache consistency state maintenance method, device, computer program product, multi-core processor and server provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A method for maintaining cache consistency state, characterized in that: Applications for multi-core processors, including: The local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor; According to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message, the target directory is determined from the exclusive directory and the shared directory; wherein the target directory is an exclusive directory or a shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line; The target directory entry is searched from the target directory, and the target directory entry is adjusted.

2. The method for maintaining cache consistency state according to claim 1, characterized in that: The cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state and an invalid shared state, wherein the invalid exclusive state indicates that the cache data in the target cache line is in an invalid state in the local processor node and the corresponding data is in an exclusive state in a certain remote processor node in the multi-core processor, and the invalid shared state indicates that the cache data in the target cache line is in an invalid state in the local processor node and the corresponding data is not in an exclusive state in a certain remote processor node in the multi-core processor; The determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes: If the cache coherence state of the target cache line is the invalid exclusive state, determining the exclusive directory as the target directory; If the cache coherence state of the target cache line is the invalid shared state, the shared directory is determined to be the target directory.

3. The method for maintaining cache consistency state according to claim 2, characterized in that: The preset cache consistency state also includes a modified state, an exclusive state and a shared state, and the determining of the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes: If the cache coherence state of the target cache line is the invalid exclusive state, the modified state or the exclusive state, determining that the exclusive directory is the target directory; If the cache coherence state of the target cache line is the shared state or the invalid shared state, the shared directory is determined to be the target directory.

4. The method for maintaining cache consistency state according to claim 1, characterized in that: The cache consistency state of the target cache line is any preset cache consistency state, and the preset cache consistency state includes an invalid state; and determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message, comprising: If the cache coherence state of the target cache line is the invalid state, determining whether the cache data in the target cache line is in an exclusive state in a certain remote processor node in the multi-core processor; If so, determining the exclusive directory as the target directory; If not, the shared directory is determined to be the target directory.

5. The method for maintaining cache consistency state according to claim 1, characterized in that: The data access address in the current directory entry in the exclusive directory is the memory address information in the corresponding cache line in the private cache of the exclusive node corresponding to the current directory entry, and the identifier of the exclusive node in the current directory entry in the exclusive directory is the processor core code; wherein the current directory entry is any directory entry in the exclusive directory.

6. The method for maintaining cache consistency state according to claim 4, characterized in that: The memory address information includes a tag, an index, and an offset.

7. The method for maintaining cache consistency state according to claim 4, characterized in that: The cache consistency state of the exclusive node corresponding to each directory entry in the exclusive directory includes an exclusive state and a modified state; the cache consistency state of the exclusive node in the current directory entry is a 1-bit identifier.

8. The method for maintaining cache consistency state according to claim 1, characterized in that: The identifiers and cache consistency states of all shared nodes in the current directory entry in the shared directory are cache consistency states corresponding to all processor nodes in the multi-core processor arranged in a preset node sorting order.

9. The method for maintaining cache consistency state according to claim 8, characterized in that: The preset node sorting order is the order of processor core code sorting from high byte to low byte or from low byte to high byte.

10. The method for maintaining cache consistency state according to claim 1, characterized in that: The determining the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message includes: If the data access address in the local cache consistency maintenance message does not match the target cache line, query the directory entry corresponding to the data access address in the local cache consistency maintenance message from the exclusive directory and the shared directory, and adjust the queried directory entry; If the data access address in the local cache coherence maintenance message matches the target cache line, the target directory is determined from the exclusive directory and the shared directory according to the cache coherence state of the target cache line.

11. The method for maintaining cache coherence state according to claim 1, characterized in that: Also includes: The local processor node receives a remote cache consistency maintenance message sent by a current remote processor node; wherein the current remote processor node is any processor node other than the local processor node in the multi-core processor; Determine a maintenance query directory according to the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message; wherein the maintenance query directory is the exclusive directory and / or the shared directory; The directory entry corresponding to the data access address in the remote cache consistency maintenance message is searched from the maintenance query directory, and the found directory entry is adjusted.

12. The method for maintaining cache consistency state according to claim 11, characterized in that: The cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message is any preset cache consistency state, and the preset cache consistency state includes an invalid exclusive state, an invalid shared state, a modified state, an exclusive state, and a shared state. The maintenance query directory is determined according to the cache consistency state corresponding to the current remote processor node in the remote cache consistency maintenance message, including: If the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message is the invalid exclusive state, the modified state or the exclusive state, determining that the exclusive directory is the maintenance query directory; If the cache coherence state corresponding to the current remote processor node in the remote cache coherence maintenance message is the shared state or the invalid shared state, the shared directory is determined to be the maintenance query directory.

13. The method for maintaining cache consistency state according to claim 1, characterized in that: The target cache line includes a data access address, a cache coherence state and cache data.

14. The method for maintaining cache coherence state according to claim 1, characterized in that: The number of the exclusive directory and the number of the shared directory in the multi-core processor are both 1.

15. The method for maintaining cache coherence state according to any one of claims 1 to 14, characterized in that: The adjusting the target directory item includes: Determining whether a directory conversion operation is required according to the adjusted cache coherence state corresponding to the target cache line; If the directory conversion operation is required, the target directory entry is deleted in the target directory, and a directory entry corresponding to the target directory entry is added to a non-target directory according to the adjusted cache consistency state; wherein the non-target directory is a directory other than the target directory in the exclusive directory and the shared directory; If the directory conversion operation is not required, the target directory entry is adjusted according to the adjusted cache consistency state.

16. The method for maintaining cache coherence state according to claim 15, characterized in that: The cache coherence state of the target cache line is a shared state, and the adjusted cache coherence state corresponding to the target cache line is a modified state; The step of deleting the target directory entry in the target directory and adding a directory entry corresponding to the target directory entry in a non-target directory according to the adjusted cache consistency state includes: Delete the target directory entry in the shared directory, and add a directory entry corresponding to the target directory entry in the exclusive directory; wherein the data access address in the directory entry corresponding to the target directory entry is the data access address of the target directory entry, the identifier of the exclusive node in the directory entry corresponding to the target directory entry is the processor core code of the local processor node, and the cache consistency state of the exclusive node in the directory entry corresponding to the target directory entry is the modified state.

17. A cache consistency state maintenance device, characterized in that: Applicable to local processor nodes in multi-core processors, including: A local acquisition module, used to acquire a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor; A directory determination module, for determining a target directory from an exclusive directory and a shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message; wherein the target directory is an exclusive directory or a shared directory; each directory entry in the exclusive directory includes a corresponding data access address, an identifier of an exclusive node and a cache consistency state of the exclusive node, and each directory entry in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the private cache of the local processor node, and the target directory entry is a directory entry in the exclusive directory or the shared directory corresponding to the target cache line; The directory maintenance module is used to search for the target directory item from the target directory and adjust the target directory item.

18. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the cache coherence state maintenance method as claimed in any one of claims 1 to 17 are implemented.

19. A multi-core processor, characterized in that: include: A preset number of processor nodes, exclusive directories, and shared directories; wherein the preset number is greater than or equal to 2, and the processor node includes a processor core and a private cache; The processor node is used to obtain a local cache consistency maintenance message; determine the target directory from the exclusive directory and the shared directory according to the cache consistency state of the target cache line corresponding to the local cache consistency maintenance message; search for the target directory item from the target directory, and adjust the target directory item; wherein the target directory is the exclusive directory or the shared directory; each directory item in the exclusive directory includes a corresponding data access address, an identifier of the exclusive node and a cache consistency state of the exclusive node, and each directory item in the shared directory includes a corresponding data access address and identifiers and cache consistency states of all shared nodes; the target cache line is any cache line in the local private cache of the processor node, and the target directory item is a directory item in the exclusive directory or the shared directory corresponding to the target cache line.

20. The multi-core processor according to claim 19, characterized in that: The exclusive directory and the shared directory are both set in the shared cache of the preset number of processor nodes.

21. A server, characterized in that: include: A multi-core processor as claimed in claim 19 or 20.

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