Memory management method and device and storage equipment
By cross-arrangement of bit lines and word line addresses in memory management, the bias drift problem caused by the equalization wear algorithm is solved, and a more balanced distribution of memory particles is achieved and a longer service life is achieved.
Patent Information
- Application Number
- CN202411977728.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
In the equalization wear algorithm, since a large number of memory particles are located on the same word line or bit line, the bias drift effect caused by data transfer is significantly increased.
By remapping the system addresses of memory particles, crossing the bit line BL addresses and word line WL addresses in turn, forming cross-arranged addresses, and managing memory particles to reduce the impact of bias drift.
Spread the accessed addresses in different WLs or BLs, significantly reducing the impact of bias drifts, extending the life of memory particles and improving the reliability of storage devices.
Smart Images
Figure CN119883959A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage technology, and in particular to a memory management method, apparatus and storage device. Background Art
[0002] In the wear-leveling (WL) algorithm, frequently operated data blocks are dynamically moved to free data blocks according to the logical block address, and even the data in the same data block is occasionally repositioned or moved according to certain rules (page leveling, PL).
[0003] If a large number of memory cells in a logic block address are located on the same word line (WL) or bit line (BL), data movement caused by WL management will bring about a more obvious problem of increased bias drift. Summary of the invention
[0004] The present application provides a memory management method, apparatus and storage device, which can reduce the influence of bias drift. The technical solution is as follows.
[0005] In a first aspect, a memory management method is provided, which is applied to a controller of a memory particle, and the method comprises:
[0006] Determine a bit line BL address and a word line WL address from the system address of the memory particle;
[0007] Crossing the M-bit BL address and the M-bit WL address in sequence to obtain cross-arranged BL addresses and WL addresses, any two adjacent addresses in the cross-arranged BL addresses and WL addresses are located on the BL or the WL, respectively, and M is a positive integer greater than or equal to 2;
[0008] The memory particles are managed based on the cross-arranged BL addresses and WL addresses.
[0009] In some implementations, the sequentially interleaving the BL address and the WL address comprises:
[0010] All the BL addresses of the memory cells and all the WL addresses of the memory cells are sequentially crossed with each other.
[0011] In some implementations, managing the memory granules based on the cross-arranged BL addresses and WL addresses includes:
[0012] A position swap or PL move task, a wear leveling WL task, or a sequential read / write task is performed based on the cross-arranged BL address and WL address.
[0013] In some implementations, managing the memory granules based on the cross-arranged BL addresses and WL addresses includes:
[0014] Access the interleaved BL addresses and WL addresses simultaneously.
[0015] In some implementations, after sequentially crossing the BL address and the WL address, the method further includes:
[0016] If the bit width of the BL address is greater than the bit width of the WL address, configuring the remaining addresses in the BL address that are not intersected with the WL address as the highest bits of the intersecting BL address and WL address;
[0017] If the bit width of the WL address is greater than the bit width of the BL address, the remaining addresses in the WL address that do not intersect with the BL address are configured as the highest bits of the interleaved BL address and WL address.
[0018] In some embodiments, the memory particles are memory particles in a three-dimensional phase change memory 3D-PCM or memory particles in a selector memory SOM.
[0019] In a second aspect, a memory management device is provided, which is disposed in a controller of a memory particle, and the device includes:
[0020] A determination unit, used to determine a bit line BL address and a word line WL address from the address of the memory particle;
[0021] A crossover unit, used for sequentially crossovering the M-bit BL address and the M-bit WL address to obtain cross-arranged BL addresses and WL addresses, where M is a positive integer greater than or equal to 2;
[0022] A management unit is used to manage the memory particles based on the cross-arranged BL addresses and WL addresses.
[0023] In some implementations, the crossover unit is used to sequentially crossover all the BL addresses of the memory cells and all the WL addresses of the memory cells.
[0024] In some implementations, the management unit is configured to perform a position swap or PL move task, a wear leveling WL task, or a sequential read / write task based on the cross-arranged BL addresses and WL addresses.
[0025] In some implementations, the management unit is configured to simultaneously access the cross-arranged BL addresses and WL addresses.
[0026] In some embodiments, the crossover unit is configured to configure the remaining addresses in the BL address that are not crossed with the WL address as the highest bits of the cross-arranged BL address and WL address if the bit width of the BL address is greater than the bit width of the WL address;
[0027] If the bit width of the WL address is greater than the bit width of the BL address, the remaining addresses in the WL address that do not intersect with the BL address are configured as the highest bits of the interleaved BL address and WL address.
[0028] According to a third aspect, a storage device is provided, comprising: a controller and memory particles, wherein the controller is coupled to the memory particles, and the controller is used to execute the first aspect or any optional method of the first aspect to manage the memory particles.
[0029] According to a fourth aspect, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, and when the instruction is executed on a computer, the computer executes the first aspect or any optional method of the first aspect.
[0030] The embodiment of the present application remaps the system address of the memory particle and cross-arranges the WL address and the BL address as the system address, so that the accessed addresses can be evenly distributed in different WLs or BLs, thereby reducing the impact of bias drift. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 is a threshold voltage distribution diagram provided in an embodiment of the present application;
[0032] Figure 2 It is a schematic diagram of a PCM WL BL pressurization condition provided in an embodiment of the present application;
[0033] Figure 3 This is a schematic diagram of address distribution provided in an embodiment of the present application;
[0034] Figure 4 is a flow chart of a memory management method provided by an embodiment of the present application;
[0035] Figure 5 is a schematic diagram of an M-bit BL address and an M-bit WL address intersecting each other in sequence provided by an embodiment of the present application;
[0036] Figure 6 It is a schematic diagram of all BL addresses and all WL addresses sequentially crossing each other provided by an embodiment of the present application;
[0037] Figure 7 This is a schematic diagram of the access order when the BL address and WL address are not interleaved;
[0038] Figure 8 It is a schematic diagram of an access sequence when a BL address and a WL address are crossed, provided in an embodiment of the present application;
[0039] Fig. 9 It is a schematic diagram of an access sequence when a BL address and a WL address are crossed, provided in an embodiment of the present application;
[0040] Fig.10 is a structural diagram of a memory management device provided in an embodiment of the present application;
[0041] Fig.11 It is a structural schematic diagram of a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0043] In three-dimensional phase-change memory (3D-PCM) and selector-only memory (SOM), OST is used as a gating switch. According to the characteristics of OTS gating devices, when a voltage smaller than the threshold voltage is applied to both ends of the cell, the cell will not be turned on, but there will be a small subthreshold conduction current, which will cause a certain drift problem of the threshold of the OTS, resulting in a phenomenon that the threshold voltage (Vth) in the set and reset states drifts with time, which is called the bias drift effect.
[0044] When there is no voltage bias, the threshold voltage distribution of set and reset is as follows: Figure 1 As shown in the figure, the blue curve represents the vt distribution of the set state, and the red curve represents the vt distribution of the reset state. B0 represents the case where there is no bias drift. As the number of operations on the same WL or BL increases, the threshold voltage distribution of the corresponding set and reset states is as follows: Figure 1 As shown in B1 and B2 in FIG. Due to the existence of bias drift, the RWM (read window margin) that can accurately distinguish the set and reset states is greatly reduced.
[0045] When performing read and write operations on a certain memory cell (cell), relatively high bias voltages V1 and V3 are applied to the corresponding WL (word line) or BL (bit line); for unselected WLs and BLs, zero bias or low bias voltages V2 and V4 are maintained to ensure a non-conducting state. For other cells on the selected WL, as shown by C3 in Figure 2 and for other cells on the selected BL, as shown by C2 in Figure 2 . These cells on the same WL or BL as the operating cell will not be selected for conduction, but there will be a certain bias voltage across the cell, and these cells will have the problem of bias drift.
[0046] If the logical addresses are arranged in the order of WL address and BL address, please refer to Appendix Figure 3 . For an n-row and m-column array, addr_wl[k-1:0]addr_bl[j-1:0], 2^k = n, 2^j = m. Assume that k addresses (k < n & k < m) are read and written. If they are read and written continuously in sequence, in the worst case, the k addresses are concentrated on the same WL or BL, and a cell may have k - 1 times of BL bias drift or k - 1 times of WL bias drift.
[0047] The lifespan of 3D-PCM is limited by its write count. Continuously programming and writing the same memory cell will more easily cause permanent damage to the memory cell. To avoid this situation, an algorithm of wear-leveling (WL) needs to be configured into the system.
[0048] The method flow provided by the embodiments of the present application is illustrated below by way of example.
[0049] When wear leveling or page leveling is performed in the system, n*n addresses are continuously read and written. In the current address map, continuously reading and writing n*n addresses will hit the same BL or WL, and the influence of bias drift is very obvious. In view of this, the embodiments of the present application remap the system addresses, cross the BL addresses and WL addresses with each other in sequence. In this way, when continuously reading and writing n*n addresses, all addresses can be dispersed to n WLs and n BLs.
[0050] For example, please refer to Appendix Figure 4 . Appendix Figure 4 is a flowchart of a memory management method provided by the embodiments of the present application. Appendix Figure 4The method shown is executed by a controller of a memory particle, which is used to control the memory particle to perform data reading and writing. The memory particle is, for example, a memory particle in a 3D-PCM, or a memory particle in a SOM, or other memory particles that need to avoid continuous access to the same BL or WL. Figure 4 The method shown includes the following steps S610 to S630.
[0051] Step S610: determining a BL address and a WL address from the system address of the memory particle.
[0052] The BL address is used to identify the corresponding bit line. The WL address is used to identify the corresponding word line. The BL address and the WL address are both physical addresses, for example.
[0053] Step S620 , sequentially cross the M-bit BL address and the M-bit WL address to obtain cross-arranged BL addresses and WL addresses, where M is a positive integer greater than or equal to 2.
[0054] Any two adjacent addresses in the cross-arranged BL addresses and WL addresses are located on the BL or WL, respectively. For example, each BL address is followed by a WL address, and each WL address is followed by a BL address. Compared with the prior art method of continuously arranging multiple BL addresses and continuously arranging multiple WL addresses, the cross-arrangement method of the BL address and the WL address makes the accessed addresses evenly distributed in different WLs or BLs.
[0055] Optionally, adjacent BL addresses and WL addresses in the cross-arranged BL addresses and WL addresses have the same number. For example, BL[0] and WL[0] are adjacent, BL[1] and WL[1] are adjacent, and so on, BL[i] and WL[i] are adjacent. Alternatively, adjacent BL addresses and WL addresses in the cross-arranged BL addresses and WL addresses have different numbers. For example, BL[0] and WL[3] are adjacent, and BL[1] and WL[4] are adjacent.
[0056] M can be determined based on the storage capacity of the memory chip. Figure 5 , attached Figure 5 1 is a schematic diagram of an M-bit BL address and an M-bit WL address intersecting each other in sequence provided by an embodiment of the present application, and Figure 5 Here, ADDR_BL represents the bit line address, and ADDR_WL represents the word line address.
[0057] In other implementations, all BL addresses of the memory cells and all WL addresses of the memory cells are sequentially interleaved. Figure 6 , attached Figure 6 It is a schematic diagram provided by an embodiment of the present application in which all BL addresses and all WL addresses are sequentially crossed with each other.
[0058] Step S630 , managing memory particles based on the cross-arranged BL addresses and WL addresses.
[0059] As an example, a position shift or move (PL) task, a wear leveling (WL) task, or a sequential read / write task is performed based on the interleaved BL address and WL address.
[0060] As an example, based on the cross-arranged BL address and WL address, the M-bit BL address and the M-bit WL address that cross each other in sequence are accessed simultaneously to obtain data stored on the BL address and the WL address, or write data to be stored to the BL address and the WL address.
[0061] Among them, the bit width of the BL address and the bit width of the WL address can be the same or different. In the case where the bit width of the BL address and the bit width of the WL address are different, the redundant addresses can be placed in the highest bit after the addresses are crossed. For example, if the bit width of the BL address is greater than the bit width of the WL address, the remaining addresses in the BL address that are not crossed with the WL address are configured as the highest bits of the crossed BL address and the WL address; if the bit width of the WL address is greater than the bit width of the BL address, the remaining addresses in the WL address that are not crossed with the BL address are configured as the highest bits of the crossed BL address and the WL address. As a specific example, the bit width of the WL address is 4 and the bit width of the BL address is 5. After the 4-bit BL address and the 4-bit WL address are crossed with each other in sequence, there are still remaining BL addresses, and the remaining BL addresses are placed in the highest bits of the crossed BL address and the WL address.
[0062] In the wear leveling algorithm, frequently operated data blocks need to be dynamically moved to free data blocks according to the logical block address, and even the data in the same data block may be swapped or moved according to certain rules from time to time (page leveling, PL). If a large number of PCM units in a logical block address are located on the same WL or the same BL, the data movement caused by wear leveling management will bring about a more obvious increase in the bias drift effect.
[0063] Assuming that the size of the maximum operation block of PL management, WL management or sequential reading and writing is n, if n<=2^(2M), when the method of crossing the BL address and the WL address provided in this embodiment is not used, the data will be concentrated in the same WL; when the method of crossing the BL address and the WL address provided in this embodiment is used, the data will be scattered on 2^M WLs and 2^M BLs. The impact of the biasdrift phenomenon will be more balanced and significantly reduced.
[0064] For example, please refer to the attached Figure 7 , attached Figure 7 This is a schematic diagram of the access sequence when the BL address and WL address are not interleaved. Figure 7 The contents of the table are the logical addresses to be accessed. Logical addresses 0-63 are distributed in the same root WL or the same root BL. Figure 7 As shown, according to the prior art, the system address is arranged, PL management, WL management or sequential reading and writing of several addresses may focus on the same WL or the same BL, and the influence of bias drift will be obvious. According to the embodiment of the present application, all or part of the WL address and BL address are cross-arranged as the system address, PL management, WL management or sequential reading and writing of several addresses will evenly distribute the accessed addresses in different WLs or BLs, thereby reducing the influence of bias drift.
[0065] Attached Figure 7 In the example shown, M takes the value of 3, and 2^(2M) = 64. When this access method is not used, 64 consecutive addresses are distributed in the same root WL, and the bias drift effect is more obvious.
[0066] Please refer to the attached Figure 8 , attached Figure 8 1 is a schematic diagram of an access sequence when a BL address and a WL address are interleaved, as provided in an embodiment of the present application. Figure 8 The yellow row represents a WL, the yellow column represents a BL, and the attached Figure 8 The blue grid represents the selected address. If 64 consecutive addresses are accessed, 8 WLs and 8 BLs will be selected, and the addresses will be more evenly distributed on the WLs and BLs. Figure 8 The blank cells in the middle represent storage cells that are not located in the 8 WLs and 8 BLs.
[0067] Please refer to the attached Fig. 9 , attached Fig. 9 is a schematic diagram of a cross-arranged BL address and WL address provided in an embodiment of the present application. Figure 8 And attached Fig. 9 In the example shown, M takes the value of 3, and 2^(2M) = 64. When accessing by interleaving BL addresses with WL addresses, 64 consecutive addresses are distributed in 8 WLs and 8 BLs, and the impact of the bias drift phenomenon will be more balanced and significantly reduced.
[0068] The method provided in the embodiment of the present application remaps the system address. M-bit BL addresses and M-bit WL addresses are sequentially crossed or all BL addresses and WL addresses are sequentially crossed. When n*n addresses are read and written continuously, all addresses can be dispersed to n WLs and n BLs. This can reduce the impact of bias drift, reduce product delivery requirements, and thereby reduce costs, and improve yield and particle life.
[0069] Fig.10 is a structural diagram of a memory management device 600 provided in an embodiment of the present application. The memory management device 600 is provided in a controller of a memory particle. The device 600 includes:
[0070] A determination unit 610, configured to determine a bit line BL address and a word line WL address from the address of the memory particle;
[0071] The crossover unit 620 is used to sequentially cross the M-bit BL address and the M-bit WL address to obtain a cross-arranged BL address and WL address, where M is a positive integer greater than or equal to 2;
[0072] The management unit 630 is configured to manage the memory particles based on the cross-arranged BL addresses and WL addresses.
[0073] In some implementations, the crossover unit 620 is configured to sequentially crossover all the BL addresses of the memory cells and all the WL addresses of the memory cells.
[0074] In some implementations, the management unit 630 is configured to perform a position swap or PL move task, a wear leveling WL task, or a sequential read / write task based on the cross-arranged BL addresses and WL addresses.
[0075] In some implementations, the management unit 630 is configured to simultaneously access the cross-arranged BL addresses and WL addresses.
[0076] In some embodiments, the cross unit 620 is used to configure the remaining addresses in the BL address that are not crossed with the WL address as the highest bits of the cross-arranged BL address and WL address if the bit width of the BL address is greater than the bit width of the WL address; if the bit width of the WL address is greater than the bit width of the BL address, configure the remaining addresses in the WL address that are not crossed with the BL address as the highest bits of the cross-arranged BL address and WL address.
[0077] In some embodiments, the cross unit 620 is used to configure the remaining addresses in the BL address that are not crossed with the WL address as the highest bits of the cross-arranged BL address and WL address if the bit width of the BL address is greater than the bit width of the WL address; if the bit width of the WL address is greater than the bit width of the BL address, configure the remaining addresses in the WL address that are not crossed with the BL address as the highest bits of the cross-arranged BL address and WL address.
[0078] Fig.11 7 is a schematic diagram of a storage device provided in an embodiment of the present application. The storage device 700 includes a controller 710 and a memory particle 720. The controller 710 is coupled to the memory particle 720. The controller 710 is used to execute Figure 4 The method shown is used to manage the memory particles 720.
[0079] In some embodiments, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, which, when executed on a computer, causes the computer to execute Figure 4 The method shown.
[0080] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0081] A refers to B, which means that A is the same as B or A is a simple variant of B.
[0082] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk SolidState Disk (SSD)), etc.
[0083] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A memory management method, characterized in that: A controller applied to a memory particle, the method comprising: Determine a bit line BL address and a word line WL address from the system address of the memory particle; Crossing the M-bit BL address and the M-bit WL address in sequence to obtain a cross-arranged BL address and WL address, where M is a positive integer greater than or equal to 2; The memory particles are managed based on the cross-arranged BL addresses and WL addresses.
2. The method according to claim 1, characterized in that The step of sequentially interleaving the M-bit BL address and the M-bit WL address comprises: All the BL addresses of the memory cells and all the WL addresses of the memory cells are sequentially crossed with each other.
3. The method according to claim 1, characterized in that The managing the memory granules based on the cross-arranged BL addresses and WL addresses includes: A position swap or PL move task, a wear leveling WL task, or a sequential read / write task is performed based on the cross-arranged BL address and WL address.
4. The method according to claim 1, characterized in that: The managing the memory granules based on the cross-arranged BL addresses and WL addresses includes: The M-bit BL address and the M-bit WL address that are sequentially interleaved with each other are accessed simultaneously.
5. The method according to claim 1, characterized in that After sequentially crossing the M-bit BL address and the M-bit WL address, the method further includes: If the bit width of the BL address is greater than the bit width of the WL address, configuring the remaining addresses in the BL address that are not intersected with the WL address as the highest bits of the intersecting BL address and WL address; If the bit width of the WL address is greater than the bit width of the BL address, the remaining addresses in the WL address that do not intersect with the BL address are configured as the highest bits of the interleaved BL address and WL address.
6. The method according to claim 1, characterized in that The memory particles are memory particles in a three-dimensional phase change memory or memory particles in a selector memory.
7. A memory management device, characterized in that: A controller provided in a memory chip, the device comprising: A determination unit, used to determine a bit line BL address and a word line WL address from the address of the memory particle; A crossover unit, used for sequentially crossovering the M-bit BL address and the M-bit WL address to obtain cross-arranged BL addresses and WL addresses, where M is a positive integer greater than or equal to 2; A management unit is used to manage the memory particles based on the cross-arranged BL addresses and WL addresses.
8. The device according to claim 7, characterized in that The crossover unit is used to sequentially cross the M-bit BL address and the M-bit WL address, where M is a positive integer greater than or equal to 2; or All the BL addresses of the memory cells and all the WL addresses of the memory cells are sequentially crossed with each other.
9. A storage device, characterized in that: The storage device comprises: a controller and a memory particle, wherein the controller is coupled to the memory particle, and the controller is used to execute the method according to any one of claims 1 to 6 to manage the memory particle.
10. A computer-readable storage medium, characterized in that: The storage medium stores at least one instruction, and when the instruction is executed on a computer, the computer executes the method according to any one of claims 1 to 6.