Server and control method

Abstract

The invention provides a server and a control method, and relates to the technical field of server architecture design, and the server is characterized in that a mainboard is provided with a CPU and a Switch chip which are connected with each other; the Switch chip is connected to the double-control backboard; the double-control backboard is also connected with a plurality of storage peripherals; the Switch chip is used for connecting a plurality of pluggable control peripherals; the Switch chip, the pluggable control peripheral and the storage peripheral jointly form a virtual Ethernet attached flash cluster to provide storage service; the Switch chip is further used for configuring an uplink port of the Switch chip so as to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to achieve the storage function, and the effect that the server can be used as a set of complete high-availability storage server while completing the calculation task is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of server architecture design, and in particular to a server and a control method. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, how to make the computing power and storage capacity of AI servers work together more efficiently has become a key factor in improving overall performance. At present, AI servers, such as high-performance servers represented by NVIDIA DGX H100 / H200, have largely exerted the powerful computing power of GPUs.

[0003] However, in the process of building intelligent computing centers or supercomputing centers, existing solutions generally believe that the storage reliability within the node is insufficient and it is difficult to meet the requirements of high availability and isolation from computing resources. Therefore, many solutions tend to adopt the design idea of ​​separating the storage network from the computing network, that is, to achieve higher reliability and flexibility by physically separating the storage device from the computing device. Although such a design can improve the stability and maintainability of the system, it also brings problems with network latency and data transmission efficiency. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a server and a control method, so as to realize that the server can be used as a complete high-availability storage server while completing computing tasks. In order to achieve the above object, the technical solution adopted in the embodiment of the present invention is as follows: In a first aspect, the present invention provides a server, comprising: a mainboard and a dual-control backplane; the mainboard is provided with a CPU and a Switch chip connected to each other; the Switch chip is connected to the dual-control backplane; the dual-control backplane is also connected to a plurality of storage peripherals; the Switch chip is used to connect a plurality of pluggable control peripherals; the Switch chip, the pluggable control peripherals and the storage peripherals together constitute a virtual Ethernet attached flash memory cluster to provide storage services; the Switch chip is also used to configure its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to implement a storage function.

[0005] In an optional implementation, the Switch chip is specifically used to: when it is determined that no pluggable control peripheral is inserted, configure the upstream port to be connected to the CPU, so that the storage peripheral communicates with the CPU through the Switch chip; when it is determined that a pluggable control peripheral is inserted, configure the upstream port to be connected to the pluggable control peripheral, so that the storage peripheral communicates with the pluggable control peripheral through the Switch chip.

[0006] In an optional implementation manner, the pluggable control peripheral is used to send a configuration instruction to the Switch chip after being inserted into the Switch chip, so as to instruct the Switch chip to configure the upstream port.

[0007] In an optional implementation manner, the pluggable control peripheral is further configured to load a new storage peripheral if it is detected that a new storage peripheral is connected when the uplink port is configured as the pluggable control peripheral itself.

[0008] In an optional implementation manner, the Switch chip is further configured to switch the upstream port to another pluggable control peripheral plugged into the Switch chip itself if the pluggable control peripheral currently controlling the storage peripheral fails.

[0009] In an optional implementation, the number of the Switch chips is one or two.

[0010] In an optional implementation, the number of the CPUs is one or two.

[0011] In an optional implementation, when there are two CPUs and two Switch chips, each CPU is connected to a Switch chip via a pluggable backplane or a data bus.

[0012] In an optional implementation manner, the pluggable control peripheral is any one of the following: a DPU, an IPU, or a device of an upstream port of the Switch chip.

[0013] In a third aspect, the present invention provides a control method, which is applied to a server, wherein the server comprises: a main board and a dual-control backplane; the main board is provided with a CPU and a Switch chip connected to each other; the Switch chip is connected to the dual-control backplane; the dual-control backplane is also connected to a plurality of storage peripherals; the Switch chip is used to connect a plurality of pluggable control peripherals; the Switch chip, the pluggable control peripherals and the storage peripherals together constitute a virtual Ethernet attached flash memory cluster to provide storage services; the method comprises: the Switch chip detects whether the pluggable control peripheral is inserted into itself; the Switch chip configures its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to realize the storage function.

[0014] The present invention provides a server and control method, the server includes: a mainboard and a dual-control backplane; the mainboard is provided with a CPU and a Switch chip connected to each other; the Switch chip is connected to the dual-control backplane; the dual-control backplane is also connected to a number of storage peripherals; the Switch chip is used to connect a number of pluggable control peripherals; the Switch chip, the pluggable control peripherals and the storage peripherals together form a virtual Ethernet attached flash memory cluster to provide storage services; the Switch chip is used to configure its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to implement the storage function. The server architecture provided by the embodiment of the present invention achieves the effect that the server can be used as a complete set of high-availability storage servers while completing computing tasks through the high-availability design of the dual-control backplane, the dynamic allocation of control rights of the Switch chip and the virtualization integration of storage peripherals.

[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 An architecture diagram of a server provided in an embodiment of the present invention; Figure 2 An example diagram of an embodiment of the present invention when no pluggable control peripheral is inserted; Figure 3 An example diagram of inserting a pluggable control peripheral provided by an embodiment of the present invention; Figure 4 An example diagram of a plug-in control peripheral failure provided by an embodiment of the present invention; Figure 5 An exemplary diagram of a server provided in an embodiment of the present invention; Figure 6 Another architecture diagram of a server provided in an embodiment of the present invention; Figure 7 This is a diagram showing an example of a dual switch chip scenario provided by an embodiment of the present invention; Figure 8 Another architecture diagram of a server provided in an embodiment of the present invention; Fig. 9 Another architecture diagram of a server provided in an embodiment of the present invention is shown in FIG. 3 ; Fig.10 Another architecture diagram of a server provided in an embodiment of the present invention; Fig.11 A schematic flow chart of a control method provided by an embodiment of the present invention.

[0018] Icons: server-10; motherboard-101; first motherboard-101-1; second motherboard-101-2; dual-control backplane-102; CPU-103; first CPU-103-1; second CPU-103-2; Switch chip-104; first Switch chip-104-1; second Switch chip-104-2; first pluggable control peripheral-105-1; second pluggable control peripheral-105-2; third pluggable control peripheral-105-3; fourth pluggable control peripheral-105-4; first storage peripheral-106-1; second storage peripheral-106-2; Nth storage peripheral-106-N; EP-107. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0021] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0022] In the prior art, it is generally believed that the storage reliability inside the node is not enough to meet the requirements of high availability and isolation from computing resources. Therefore, a design that separates computing devices from storage devices is adopted to improve the reliability of the system. However, considering that this separation architecture is prone to increase network latency and reduce data transmission efficiency. An embodiment of the present invention provides a server architecture that can ensure the high availability of the node's internal storage while the node provides external computing power.

[0023] See also Figure 1 , Figure 1 An architecture diagram of a server provided in an embodiment of the present invention, the server 10 includes: a mainboard 101 and a dual-control backplane 102; the mainboard 101 is provided with a CPU 103 and a Switch chip 104 connected to each other; the Switch chip 104 is connected to the dual-control backplane 102; the dual-control backplane 102 is connected with a first storage peripheral 106-1 to an N-th storage peripheral 106-N; the Switch chip 104 is used to connect a first pluggable control peripheral 105-1 and a second pluggable control peripheral 105-2; the Switch chip 104, the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2, the first storage peripheral 106-1, the second storage peripheral 106-2 to the N-th storage peripheral 106-N together constitute a virtual Ethernet attached flash memory cluster to provide storage services.

[0024] It should be understood that Figure 1 Only two first pluggable control peripherals 105-1 and second pluggable control peripherals 105-2 connected to the Switch chip 104 are shown, but this does not limit the number of pluggable control peripherals provided in the embodiment of the present invention. In fact, a Switch chip can be connected to multiple pluggable control peripherals. In addition, Figure 1 The structure shown is only a sample architecture for the server. The actual configuration of the server may include more Figure 1 More or fewer components as shown, or with Figure 1 There are different configuration methods. I will not go into details here.

[0025] exist Figure 1 In the embodiment, the CPU 103 can be used to provide computing power, and can also be used to take over the first storage peripheral 106-1, the second storage peripheral 106-2 to the Nth storage peripheral 106-N to form a virtual Ethernet attached flash memory cluster to provide storage services when the Switch chip 104 configures the up stream port to the CPU 103 itself.

[0026] In one embodiment of the present invention, the Switch chip has the ability to dynamically allocate control rights, which is used to configure and set the uplink port according to the pluggable control peripherals inserted into the Switch chip itself, so as to determine whether the CPU or the pluggable control peripherals will take over the storage peripherals. Specifically: When it is determined that no pluggable control peripheral is inserted, the upstream port is configured to be connected to the CPU so that the storage peripheral communicates with the CPU through the Switch chip; When it is determined that a pluggable control peripheral is inserted, the upstream port is configured to be connected to the pluggable control peripheral, so that the storage peripheral communicates with the pluggable control peripheral through the Switch chip.

[0027] In the embodiment of the present invention, there are two situations where no pluggable control peripheral is inserted: the first is that no peripheral is inserted into the Switch chip; the second is that although a peripheral is inserted, the peripheral does not have control capability, for example, an ordinary graphics card is inserted. In this case, the Switch chip will configure the upstream port to connect to the CPU. Of course, no matter which of the above situations it is, the CPU is required to be in the power-on state so that it can take over the storage peripheral in time.

[0028] In one embodiment of the present invention, when a pluggable control peripheral is inserted into the Switch chip, the uplink port can be configured to be connected to the pluggable control peripheral. In this case, no matter whether CPU103 is in the power-on state, the non-power-on state, or the standby state, the pluggable control peripheral will independently run in the controller mode and take over the storage peripheral as an independent controller. Meanwhile, other servers in the network can still access all disks and storage services normally and are not affected. Of course, even if a pluggable control peripheral is inserted, the Switch chip can also configure the uplink port to be connected to the CPU, which depends on the actual configuration and control requirements.

[0029] from Figure 1It can be seen in the server 10 that the Switch chip 104, the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2, the first storage peripheral 106-1, the second storage peripheral 106-2 to the Nth storage peripheral 106-N together form a virtual Ethernet attached flash cluster to provide efficient and flexible storage services. It can be understood that when the virtual EBOF is not connected to CPU1, its function is more reliable than the traditional NVMe EBOF, and it has the ability to communicate directly with the computing node and transmit data. Through a pluggable control peripheral with NVMe over Fabric (NVMe oF) offload function, such as DPU or smart network card control, the virtual EBOF can provide standard NVMe block storage functions to the outside, similar to a group of independent disk machine frames. When the virtual EBOF is connected to the CPU, it can work with the motherboard as a component of the motherboard, or it can run independently of the motherboard, thereby fully realizing the storage function. This design not only retains the high efficiency of traditional NVMe EBOF, but also greatly improves the flexibility, scalability and reliability of the system by running in collaboration with the CPU or independently.

[0030] To understand the above process, see Figure 2 and Figure 3 , Figure 2 This is an example diagram of an architecture when no pluggable control peripheral is inserted, provided in an embodiment of the present invention. Figure 3 This is a diagram showing an example of an architecture when a pluggable control peripheral is inserted according to an embodiment of the present invention.

[0031] exist Figure 2 In the example of the first storage peripheral 106-1, the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2 are not plugged into the Switch chip 104. At this time, the Switch chip 104 configures the uplink port to be connected to the CPU 103, thereby forming a communication link between the CPU 103, the Switch chip 104 and the first storage peripheral 106-1. In this case, the CPU 103 directly takes over the first storage peripheral 106-1 and provides storage services.

[0032] exist Figure 3In the example, still taking the first storage peripheral 106-1 as an example, the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2 are both inserted into the Switch chip 104. Assuming that the Switch chip 104 configures the uplink port to be connected to the first pluggable control peripheral 105-1, a communication link will be formed between the first pluggable control peripheral 105-1, the Switch chip 104 and the first storage peripheral 106-1, and the first pluggable control peripheral 105-1 takes over the first storage peripheral 106-1 to provide storage services. Of course, if the Switch chip 104 configures the uplink port to be connected to the second pluggable control peripheral 105-2, the second pluggable control peripheral 105-2 takes over the first storage peripheral 106-1 to provide corresponding storage services.

[0033] As can be seen from the above examples, in an embodiment of the present invention, a Switch chip can be connected to multiple pluggable control peripherals. When multiple pluggable control peripherals are plugged in at the same time, the uplink port can be flexibly configured to connect to any one of them. In this way, if the pluggable control peripheral currently responsible for controlling the storage peripheral fails, the system can quickly switch the uplink port to other pluggable control peripherals that are working normally, thereby achieving high availability of the storage service and ensuring stable operation of the system.

[0034] To understand the above process more clearly, Figure 3 Based on reference Figure 4 . Figure 4 An example scenario of a pluggable control peripheral device failure in an embodiment of the present invention is shown. Figure 4 In the example, it is assumed that the first pluggable control peripheral 105-1 currently responsible for controlling the first storage peripheral 106-1 fails. At this time, the Switch chip 104 will automatically reconfigure the uplink port to connect to the second pluggable control peripheral 105-2. Subsequently, a new communication link will be quickly established between the second pluggable control peripheral 105-2, the Switch chip 104 and the first storage peripheral 106-1, and the second pluggable control peripheral 105-2 will take over the first storage peripheral 106-1 and continue to provide storage services. This mechanism effectively ensures the continuity and high availability of storage services.

[0035] In one embodiment of the present invention, in order to facilitate the Switch chip to switch the upstream port in time, the pluggable control peripheral is used to send a configuration instruction to the Switch chip after being inserted into the Switch chip, so as to instruct the Switch chip to configure the upstream port. Figure 3, when the first storage peripheral 106-1 is being taken over by the CPU 103, after the first pluggable control and unplug peripheral 105-1 is inserted into the Switch chip 104, it will complete the power-on process and load the operating system before the mainboard 101. After powering on, the mainboard 101 will identify the first pluggable control and unplug peripheral 105-1 as an external device and load it. Subsequently, the first pluggable control and unplug peripheral 105-1 will send a configuration instruction to the control circuit of the Switch chip 104. After receiving the instruction, the Switch chip 104 will reconfigure the upstream port to connect to the first pluggable control and unplug peripheral 105-1, thereby taking over the first storage peripheral 106-1.

[0036] In another embodiment of the present invention, the configuration instruction may not be sent by the pluggable control peripheral device, but may be sent by other circuits or chips after detecting that the pluggable control peripheral device is plugged in.

[0037] In one embodiment of the present invention, the pluggable control peripheral is further configured to load the new storage peripheral if it is detected that a new storage peripheral is connected when the uplink port is configured as the pluggable control peripheral itself.

[0038] Optionally, the pluggable control peripheral device may be, but is not limited to, a PCIe peripheral device, and has an independent control mode, and can act as an independent controller to take over the storage peripheral device. For example, the pluggable control peripheral device may be, but is not limited to, a DPU (data processing unit), an IPU, or a device of the upstream port of the Switch chip, where the device refers to an external device that can be disconnected as the upstream of the Switch chip.

[0039] In one embodiment of the present invention, the storage peripheral device may be, but is not limited to, an NVMe SSD.

[0040] In one embodiment of the present invention, each link in the server may be, but is not limited to, a PCIe link.

[0041] For example, as an example, Figure 5 An example diagram of a server provided in an embodiment of the present invention. Figure 5 In the embodiment, DPU1 and DPU2 are respectively used as the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2, which can be inserted into the PCIe Switch chip as the Switch chip 104. In addition, the connection links between the PCIe Switch chip and the dual-control backplane 102, and between the dual-control backplane 102 and the NVMe SSD1 to NVMeSSDN as the first storage peripheral 106-1 to the Nth storage peripheral 106-N, can all be implemented using PCIe links. This design not only ensures efficient data transmission of the system, but also improves the flexibility and scalability of the overall architecture.

[0042] In one embodiment of the present invention, the number of the switch chips may be one or two. When two switch chips are used, each switch chip is connected to the CPU and the dual-control backplane to form a redundant architecture to improve the reliability and performance of the system.

[0043] To understand the above architecture more clearly, please refer to Figure 6 , Figure 6 Another architecture diagram of a server provided in an embodiment of the present invention. Figure 6 The illustration of the virtual Ethernet-attached flash cluster is omitted. Figure 6 In the figure, the blue line indicates the link connected to the first Switch chip 104-1; the red line indicates the link connected to the second Switch chip 104-2. The first Switch chip 104-1 and the second Switch chip 104-2 are connected to the CPU 103 respectively. At the same time, the first Switch chip 104-1 is connected to the dual-control backplane 102 through link 0, and the second Switch chip 104-2 is connected to the dual-control backplane 102 through link 1. Under this architecture, there are two independent links between each storage peripheral and the dual-control backplane, which are connected to the two Switch chips respectively. This design not only realizes load balancing between the two Switch chips, but also improves the high availability of the system through redundant links.

[0044] It should be understood that Figure 6 In the example, the first Switch chip 104-1 is connected to the first pluggable control peripheral 105-1 and the second pluggable control peripheral 105-2, while the second Switch chip 104-2 is connected to the third pluggable control peripheral 105-3 and the fourth pluggable control peripheral 105-4. However, this does not limit the number of pluggable control peripherals connected to each Switch chip. In fact, designers can flexibly configure the number of pluggable control peripherals that can be inserted into each Switch chip according to actual needs to meet the system scalability and functional requirements in different application scenarios.

[0045] Similarly, when the system contains two switch chips, the same storage peripheral can be taken over by any pluggable control peripheral on each switch chip. To show this architecture more clearly, please refer to Figure 7 , Figure 7 This is an example diagram of a dual switch chip architecture provided by an embodiment of the present invention. Figure 7The illustration of the virtual Ethernet-attached flash cluster is omitted. The blue lines represent the links connected to the first Switch chip 104-1; the red lines represent the links connected to the second Switch chip 104-2.

[0046] exist Figure 7 In the embodiment, a communication link is formed between the second pluggable control peripheral 105-2, the first Switch chip 104-1 and the first storage peripheral 106-1, and the second pluggable control peripheral 105-2 takes over the first storage peripheral 106-1 to provide storage services. At the same time, another communication link can be formed between the third pluggable control peripheral 105-3, the second Switch chip 104-2 and the first storage peripheral 106-1, and the third pluggable control peripheral 105-3 takes over the first storage peripheral 106-1 to provide the same storage services. This design further enhances the redundancy and high availability of the system.

[0047] In one embodiment of the present invention, the number of CPUs is one or two. When there are two CPUs, Figure 6 , the embodiment of the present invention further provides an optimized system architecture. Figure 8 , Figure 8 Another architecture diagram of the server provided in the embodiment of the present invention is shown in FIG. 2 . Figure 8 The virtual Ethernet attached flash memory cluster is omitted in the figure, and the blue line represents the link connected to the first Switch chip 104-1; the red line represents the link connected to the second Switch chip 104-2. Figure 8 The first CPU 103-1 and the second CPU 103-2 are shown, both of which are arranged on the same motherboard 101. The first CPU 103-1 is connected to the first Switch chip 104-1, and the second CPU 103-2 is connected to the second Switch chip 104-2. At the same time, the first CPU 103-1 and the second CPU 103-2 achieve high-speed communication through a UPI (UltraPathInterconnect) interface.

[0048] By connecting the Switch chip to another CPU, the system can achieve a higher level of redundancy design. In this architecture, even if one CPU (such as the first CPU 103-1) fails, the other CPU (such as the second CPU 103-2) can still take over and manage all storage peripherals on the dual-control backplane to ensure the continuous operation of the system. In addition, when the pluggable control peripheral is inserted, the system can still seamlessly take over the storage peripheral and continue to provide stable storage services.

[0049] exist Figure 8 Based on Fig. 9 , Fig. 9 Another architecture diagram of the server provided in the embodiment of the present invention is shown in FIG. 3 . Fig. 9 The virtual Ethernet-attached flash memory cluster and the motherboard where the Switch chip is located are omitted in the figure. The blue line represents the link connected to the first Switch chip 104-1; the red line represents the link connected to the second Switch chip 104-2. Fig. 9 In the embodiment, the first CPU 103-1 is set on the first motherboard 101-1, the second CPU 103-2 is set on the second motherboard 101-2, and each CPU is connected to a Switch chip through a pluggable backplane or a data bus, for example, through a PCIe expansion cable. This design can still effectively control storage peripherals and provide stable storage services. By distributing the CPU and Switch chips on independent motherboards, the system achieves higher isolation and flexibility in physical architecture, further enhancing the reliability and scalability of the system.

[0050] In one embodiment of the present invention, Fig.10 As shown, Fig.10 Another architecture diagram of a server provided by an embodiment of the present invention is shown in Figure 4. In this architecture, the CPU 103 can be additionally connected to a Switch chip 104, and multiple EPs 107 can be connected to the Switch chip 104. In this way, the CPU 103, the Switch chip 104 and the multiple EPs 107 together constitute a complete motherboard architecture.

[0051] exist Fig.10 In the EP107, various peripherals that comply with the PCIe specification can be included but are not limited to GPU (Graphics Processing Unit), DPU (Data Processing Unit), IPU (Intelligent Processing Unit), network card and other devices. This design enables the system to flexibly expand and configure different types of peripherals to meet diverse computing and storage needs.

[0052] In summary, the server provided by the embodiment of the present invention integrates a set of detachable, replaceable, highly available, dynamically configurable peripheral systems. The system can not only support the server to efficiently complete computing tasks, but also enable it to be used as a complete set of high-availability storage servers. Specifically: First, the embodiment of the present invention dynamically configures the uplink port of the Switch chip where the dual-control storage peripherals are located. When the CPU on the server is not turned on, it forms a virtual EBOF together with the pluggable control peripherals and the Switch chip. When the storage software is run in the pluggable control peripherals, it is a dual-control dual-active storage server. When the CPU on the server is not turned on, if the pluggable control peripherals are not inserted, or other peripherals that do not have a controller mode are inserted, the uplink port of the Switch chip is configured as the CPU, and the storage peripherals can be directly accessed through the device connected to the CPU. When the CPU on the server is not turned on and a pluggable control peripheral is inserted, the uplink port of the Switch chip where the storage peripheral is located can be dynamically configured as a pluggable control peripheral, so that the network device can directly access the storage peripheral without going through the CPU, so that the storage and computing resources are closest and the storage and computing resources are isolated. Secondly, the storage peripheral is connected to the server through a dual-control backplane to achieve the effect of dual-control and multi-active. When the CPU or pluggable control peripheral fails, storage access is still accessible.

[0053] In general, the embodiments of the present invention directly connect the hardware-level dual-control backplane with the Switch chip, and switch the storage control rights from the software layer to the hardware layer, thereby realizing nanosecond fault switching. The modular design of the pluggable control peripherals allows the replacement of control peripherals with different functions during operation, and the Switch chip automatically synchronizes the storage topology information without restarting or remounting the storage device, thereby realizing the physical decoupling of the storage control logic from the motherboard. While completing the computing tasks, the entire server can also be used as a complete set of high-availability storage servers. Without starting the server motherboard CPU and other peripherals, the storage peripherals on the dual-control backplane can be taken over by the pluggable control peripherals inserted on the motherboard and used as an independent high-availability node. Without inserting the pluggable control peripherals, the storage peripherals are taken over by the CPU, and can still be used as a general server to provide storage services to the outside world.

[0054] Based on the server 10 provided in the above embodiment, the embodiment of the present invention further provides a control method, see Fig.11 , Fig.11 A schematic flow chart of a control method provided by an embodiment of the present invention is described as follows: S110: The Switch chip detects whether a pluggable control peripheral is plugged into it; S120: The Switch chip configures its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to implement the storage function.

[0055] In an optional implementation, the Switch chip determines whether the pluggable control peripheral is plugged into the Switch chip itself by detecting whether the configuration instruction of the pluggable control peripheral is received; if the configuration instruction is received, it is determined that the pluggable control peripheral is plugged into itself, and the uplink port of the Switch chip itself is set according to the peripheral and the configuration. Otherwise, the pluggable control peripheral is not plugged into.

[0056] In an optional embodiment, the control method also includes: when it is determined that no pluggable control peripheral is inserted, the Switch chip configures the upstream port to be connected to the CPU so that the storage peripheral communicates with the CPU through the Switch chip; when it is determined that a pluggable control peripheral is inserted, the Switch chip configures the upstream port to be connected to the pluggable control peripheral so that the storage peripheral communicates with the pluggable control peripheral through the Switch chip.

[0057] In an optional implementation manner, the control method further includes: after the pluggable controller is inserted into the Switch chip, sending a configuration instruction to the Switch chip to instruct the Switch chip to configure an uplink port.

[0058] In an optional implementation, the control method further includes: when the pluggable control peripheral is configured as the pluggable control peripheral itself at the uplink port, if it is detected that a new storage peripheral is connected, loading the new storage peripheral.

[0059] In an optional implementation, the control method further includes: if the Switch chip determines that the pluggable control peripheral currently controlling the storage peripheral is faulty, switching the upstream port to connect to other pluggable control peripherals plugged into the Switch chip itself.

[0060] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0061] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0062] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A server, characterized in that: include: A main board and a dual-control backplane; the main board is provided with a CPU and a Switch chip which are interconnected; the Switch chip is connected to the dual-control backplane; the dual-control backplane is also connected to a number of storage peripherals; the Switch chip is used to connect a number of pluggable control peripherals; the Switch chip, the pluggable control peripherals and the storage peripherals together form a virtual Ethernet attached flash memory cluster to provide storage services; the Switch chip is also used to configure its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to realize the storage function.

2. The server according to claim 1, characterized in that: The Switch chip is specifically used to: when it is determined that no pluggable control peripheral is inserted, configure the upstream port to be connected to the CPU, so that the storage peripheral communicates with the CPU through the Switch chip; When it is determined that a pluggable control peripheral device is inserted, the uplink port is configured to be connected to the pluggable control peripheral device, so that the storage peripheral device communicates with the pluggable control peripheral device through the Switch chip.

3. The server according to claim 1 or 2, characterized in that: The pluggable control peripheral is used to send a configuration instruction to the Switch chip after being inserted into the Switch chip, so as to instruct the Switch chip to configure the uplink port.

4. The server according to claim 1, characterized in that: The pluggable control peripheral is further configured to load the new storage peripheral if it is detected that a new storage peripheral is connected when the uplink port is configured as the pluggable control peripheral itself.

5. The server according to claim 1, characterized in that: The Switch chip is also used for switching the upstream port to connect to other pluggable control peripherals inserted into the Switch chip itself if the pluggable control peripheral currently controlling the storage peripheral fails.

6. The server according to claim 1, characterized in that: The number of the Switch chips is one or two.

7. The server according to claim 1 or 6, characterized in that: The number of the CPUs is one or two.

8. The server according to claim 7, characterized in that: When there are two CPUs and two Switch chips, each CPU is connected to a Switch chip via a pluggable backplane or a data bus.

9. The server according to claim 1, characterized in that: The pluggable control peripheral is any one of the following: DPU, IPU, and a device of the upstream port of the Switch chip.

10. A control method, characterized in that: The method is applied to a server, the server comprising: a mainboard and a dual-control backplane; the mainboard is provided with a CPU and a Switch chip connected to each other; the Switch chip is connected to the dual-control backplane; the dual-control backplane is also connected to a plurality of storage peripherals; the Switch chip is used to connect a plurality of pluggable control peripherals; the Switch chip, the pluggable control peripherals and the storage peripherals together form a virtual Ethernet attached flash memory cluster to provide storage services; the method comprises: The Switch chip detects whether a pluggable control peripheral is inserted into itself; The Switch chip configures its own uplink port to determine whether the CPU or the pluggable control peripheral controls the storage peripheral to implement the storage function.

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