Embedded multi-interface communication system and method based on optical fiber Ethernet

Abstract

The invention relates to an embedded multi-interface communication system and method based on an optical fiber Ethernet, and the system employs the optical fiber Ethernet to replace a conventional bus, enables a main control module to be connected with each interface module through a plurality of groups of one-to-one optical fiber Ethernet arrays, and can achieve the long-distance communication between various interface modules and the main control module. Meanwhile, the same core board can be carried on the main control module and each interface module in the embedded communication system to realize a universal function, and difference parts such as interface expansion and the like are realized on the carrier board, so that the interchangeability of the core boards among different board cards can be realized, and the embedded communication system has better expandability and flexibility. In addition, a communication method between the main control module and each interface module is constructed according to the communication system, and protocol conversion and software processing between different interface data can be realized.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and in particular, relates to an embedded multi-interface communication system and method based on fiber optic Ethernet. Background Art

[0002] An embedded multi-interface communication system is a commonly used communication terminal in industry. Compared with office computers, it has better environmental adaptability and scalability. By plugging in different interface modules, rich interface resources can be realized to connect and communicate with external devices with various different interfaces and protocols. A common embedded multi-interface communication system consists of a main control module and multiple interface modules. Among them, the main control module is mainly used to carry an operating system and provide some interfaces externally; the interface module is used to expand different interfaces and the number of interfaces to meet customized requirements. The main control module and the interface module are usually connected by a backplane. The bus connection between the main control module and the interface module is completed on the backplane, and the module can be directly plugged into the backplane to complete the connection of the communication link between the main control module and the interface module.

[0003] However, in some specific scenarios, devices with different interfaces may be placed at relatively far positions, or even in different equipment rooms. In such scenarios, using a conventional embedded multi-interface communication system will result in a long signal trace for the communication system to communicate with external devices. On the one hand, it may cause signal attenuation and lead to abnormal communication. On the other hand, the external communication cables are generally wide, and a large number of signal lines are covered in the cable. Connecting a long distance will increase the risk of being damaged by humans during use. If the internal signal lines are damaged during use, it is also very difficult to quickly locate and repair.

[0004] Under the current situation, embedded communication systems are developing towards multiple types and a large number of interfaces. It is possible to realize the status control and information collection of rich and flexible interface modules through a main control module, which puts forward higher requirements for long-distance communication between different interface modules. To achieve this goal, it is necessary to break the dependence on the backplane between the main control module and the interface module, and fiber optic Ethernet has the characteristics of fast transmission speed, thin wire diameter, and suitability for long-distance communication. Therefore, realizing the design of an embedded multi-interface communication system based on fiber optic Ethernet will provide more powerful support for the development of the embedded multi-interface communication field and also conform to the general trend of future relevant technology development. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and propose an embedded multi-interface communication system and method based on fiber optic Ethernet, which uses fiber optic Ethernet to replace the traditional bus connection between the main control module and the interface module, breaking the dependence on the backplane between the main control module and the interface module.

[0006] The technical problem solved by the present invention is achieved by adopting the following technical solutions:

[0007] An embedded multi-interface communication system based on fiber optic Ethernet, comprising a main control module, a serial port interface communication module, a CAN interface communication module and a network interface communication module. The main control module is respectively connected to the serial port interface communication module, the CAN interface communication module and the network interface communication module through gigabit fiber optic Ethernet. The main control module, the serial port interface communication module, the CAN interface communication module and the network interface communication module are mounted with the same core board.

[0008] Moreover, the main control module includes a core board, a PHY chip and a power conversion module TPS54A24. Among them, the power conversion module TPS54A24 is connected to the core board, and the core board outputs fiber optic Ethernet through the PHY chip.

[0009] Moreover, the core board includes an FPGA, a high-speed connector, interfaces, and memory. Among them, the main control module is used to control communication, the high-speed connector is used to connect peripherals, the interfaces are used for multi-interface input and output, the power conversion module is used to convert the power into various powers used by the system, and the memory is used for data storage. The main control module is respectively connected to the high-speed connector, the interfaces, the power conversion module and the memory. The interfaces include a USB-JTAG debugging interface, a USB-serial port debugging interface, a USB interface, an SD card connector, gigabit Ethernet and an HDMI interface.

[0010] Moreover, the FPGA includes a PS and a PL. Among them, the PS is a processor system with software development resources of an ARM processor; the PL is programmable logic with customization and realizes user expansion functions. Among them, the PS and the PL are connected by an AXI bus for internal data transmission. The core board is equipped with a Linux operating system to realize the utilization of system resources. The core board uses 5V on the carrier board as the main power supply through an inter-board high-speed connector, and uses a power conversion module to convert 5V into 1.0V, 1.5V, 1.8V and 3.3V respectively for power supply of the chips on the board. All external debugging interfaces are directly extended from the PS side. Among them, the JTAG signal and the serial port signal are respectively converted into a USB interface through a signal conversion chip and led out for front-out debugging. All external signals are led out from the high-speed connector. The debugging interfaces are all led out through the carrier board, and all GPIO on the PS and PL sides are also led out to the carrier board.

[0011] A communication method for an embedded multi-interface communication system based on fiber optic Ethernet, including a serial port interface communication method, a CAN interface communication method and a network interface communication method.

[0012] Moreover, the specific implementation method of the serial port interface communication method is as follows: The serial port interface communication module has one gigabit fiber Ethernet interface and four RS422 serial ports. The gigabit fiber Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed connector between boards. This chip converts the gigabit Ethernet signal into a fiber Ethernet signal and outputs it through the front-mounted optical module. The four 422 serial ports directly instantiate 4 232 signals through the FPGA and input them into the carrier board through the high-speed connector between boards. Then, the isolated 232 signals are connected to the 422 transceiver chip to be converted into RS422 signals. Finally, the 4 RS422 signals are connected to the front-mounted high-speed connector to achieve interaction with the external interface.

[0013] Moreover, the specific implementation method of the CAN interface communication method is as follows: The CAN interface communication module has one gigabit fiber Ethernet interface and two CAN interfaces. The gigabit fiber Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed connector between boards. This chip converts the gigabit Ethernet signal into a fiber Ethernet signal and outputs it through the front-mounted optical module. The two CAN interfaces directly instantiate 2 CAN signals through the FPGA and input them into the carrier board through the high-speed connector between boards. Then, the CAN signals are isolated and level protocol-converted by the isolated CAN transceiver chip. Finally, the 2 CAN signals are connected to the front-mounted high-speed connector to achieve interaction with the external interface.

[0014] Moreover, the specific implementation method of the network interface communication method is as follows: The network interface communication module has one gigabit fiber Ethernet interface and two 100M Ethernet interfaces. The gigabit fiber Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed connector between boards. This chip converts the gigabit Ethernet signal into a fiber Ethernet signal and outputs it through the front-mounted optical module. The two 100M Ethernet interfaces directly instantiate 2 network signals through the FPGA and input them into the carrier board through the high-speed connector between boards. The network signals are level protocol-converted by the 100M Ethernet PHY chip, then the network signals are output to the network transformer, and finally the 2 Ethernet signals are connected to the front-mounted high-speed connector to achieve interaction with the external interface.

[0015] The advantages and positive effects of the present invention are:

[0016] The present invention includes a main control module and various interface modules. Each of the interface modules includes a serial port interface communication module, a CAN interface communication module, and a network interface communication module. The main control module is connected to each of the interface modules through multiple groups of one-to-one fiber optic Ethernet arrays, enabling long-distance communication between various interface modules and the main control module. The same core board is installed on both the main control module and each of the interface modules to achieve general functions, thereby enabling the interchangeability of the core boards between different boards, and thus making it have better scalability and flexibility. The present invention can perform signal processing and protocol forwarding for each interface module by installing a large number of fiber optic Ethernet communication links, and at the same time can achieve protocol conversion and software processing between different interface data. Description of the Drawings

[0017] Figure 1 It is a structural diagram of the core board of the present invention;

[0018] Figure 2 It is a structural diagram of the main control module of the present invention;

[0019] Figure 3 It is a structural diagram of the optical port implementation unit of the core board of the present invention;

[0020] Figure 4 It is a flowchart of the serial port interface communication method of the present invention;

[0021] Figure 5 It is a flowchart of the CAN interface communication method of the present invention;

[0022] Figure 6 It is a flowchart of the network interface communication method of the present invention. Detailed Description of the Invention

[0023] The following further describes the present invention in conjunction with the drawings.

[0024] An embedded multi-interface communication system based on fiber optic Ethernet includes a main control module, a serial port interface communication module, a CAN interface communication module, and a network interface communication module. The main control module is connected to the serial port interface communication module, the CAN interface communication module, and the network interface communication module respectively through gigabit fiber optic Ethernet, and all received data are transmitted to the main control module through their respective fiber optic links. After data processing and protocol conversion by the main control module, they are transmitted to the corresponding interface modules through their respective fiber optic links, and data sending operations are performed through the external interfaces of the interface modules. The same core board can be installed on both the main control module and each of the interface modules to achieve general functions, and the differential parts such as interface expansion are implemented on the carrier board, thereby enabling the interchangeability of the core boards between different boards, and thus making it have better scalability and flexibility.

[0025] The main control module includes a core board, a PHY chip, and a power conversion module TPS54A24. Among them, the power conversion module TPS54A24 is connected to the core board, and the core board outputs fiber optic Ethernet through the PHY chip. The main control module is a data management module, which is internally equipped with a large number of fiber optic Ethernet communication links and is connected to each interface module through multiple groups of one-to-one fiber optic Ethernet arrays to achieve signal processing and protocol forwarding for each interface module. Its principle block diagram is as Figure 2 shown. This module provides six-way fiber optic Ethernet externally to achieve information interaction between multiple modules. This part is mainly implemented by a gigabit Ethernet PHY chip, which can achieve optoelectronic signal conversion. The core board inputs six-way gigabit Ethernet signals to six gigabit Ethernet PHY chips respectively through the high-speed connector between boards. Each gigabit Ethernet PHY chip can convert one-way gigabit Ethernet signal into one-way fiber optic Ethernet signal internally. Finally, the fiber optic Ethernet signal is output through the front-mounted optical module and connected to the external fiber optic connection line to achieve fiber optic Ethernet communication.

[0026] Such as Figure 3As shown, its software part mainly includes an optical port implementation unit. This module has a total of six gigabit Ethernet fiber interfaces, which are implemented by the PS-side MIO, PS-side EMIO, and PL-side respectively. When the PS-side MIO receives data, under the operating system, after the fiber interface obtains the optical signal from the data management board, the data is processed by the PHY chip, and the data is converted from an optical signal to an electrical signal. This system uses the RGMII interface with a clock frequency of 125 MHz. After the system receives the data from the PHY, the data is processed by the MAC integrated on the PS-side and transmitted to the operating system, and the network interface under the operating system can then process the received data. When sending data, under the operating system, data is sent to the network interface. The MAC on the PS-side encapsulates the data and sends it to the PHY on the data management board. After being processed by the PHY, the data is converted from an electrical signal to an optical signal and sent to an external device. When the PS-side EMIO receives data, under the operating system, after the integrated fiber interface obtains the optical signal from the external device, the data is processed by the PHY chip, and the data is converted from an optical signal to an electrical signal. This system uses the RGMII interface with a clock frequency of 125 MHz. The Ethernet MAC implemented by the PS-side EMIO uses the GMII interface, which is different from the RGMII. Therefore, an IP core for signal conversion needs to be designed to convert the RGMII signal to the GMII. After the conversion is completed, the GMII signal is transmitted to the PS-side of the data management board. After being processed, it is transmitted to the operating system, and the network interface under the operating system can then further process the data. When sending data, under the operating system, data is sent to the network interface. The MAC on the PS-side encapsulates the data, processes the signal into a GMII signal, and then converts the GMII signal into an RGMII through the IP core for signal conversion. After the conversion is completed, it is transmitted to the PHY. After being processed by the PHY, the data is converted from an electrical signal to an optical signal and sent to an external device. When the PL-side receives data, under the operating system, after the integrated fiber interface obtains the optical signal from the external device, the data is processed by the PHY chip, and the data is converted from an optical signal to an electrical signal. This system uses the RGMII interface with a clock frequency of 125 MHz. Since the PL-side does not have a built-in MAC like the PS-side, we need to add an IP core for Ethernet MAC and DMA on the PL-side and transmit data through the AXI HP and GP interfaces on the PS-side. Because the speed of the gigabit network is very high and using the AXI GP cannot meet the transmission requirements, the HP interface on the PS-side needs to be opened, and then the MAC on the PL-side is connected to the PS-side through the AXI interconnect for data processing. Since the PS-side supports 16 external interrupts, and the PL-side MAC and DMA each occupy 2 interrupts, 4 Ethernet modules can be built on the PL-side. After the data is processed by the PL-side MAC, it is transmitted to the PS-side through the AXI interconnect. After being processed, it is transmitted to the operating system, and the network interface under the operating system can then further process the data.When sending data, under the operating system, data is sent to the network interface. The PS transfers the data to the MAC through the DMA and AXI interconnect structures. The MAC on the PL side encapsulates the data and sends it to the PHY. After being processed by the PHY, the data is converted from an electrical signal to an optical signal and sent to an external device.

[0027] As Figure 1 shown, the core board includes an FPGA, high-speed connectors, interfaces, and memory. Among them, the main control module is used to control communication, the high-speed connectors are used to connect peripherals, the interfaces are used for multi-interface input and output, the power conversion module is used to convert the power into various powers used by the system, and the memory is used for data storage. The main control module is respectively connected to the high-speed connectors, interfaces, power conversion module, and memory. The interfaces include a USB-JTAG debug interface, a USB-serial port debug interface, a USB interface, an SD card connector, a gigabit Ethernet, and an HDMI interface.

[0028] The core board takes the FPGA as the core. This chip is mainly composed of two parts, the PS and the PL. Among them, the PS is the processor system, which has the efficiency, generality, and rich software development resources of the ARM processor; the PL is the programmable logic, which has a high degree of customization, and rich user extension functions can be realized by using IP cores. The PS and the PL are closely connected through the AXI bus to achieve internal data transmission. At the same time, the core board is equipped with the Linux operating system to realize the utilization of system resources. Its principle block diagram is as shown in the appendix Figure 1 shown. The core board uses 5V on the carrier board as the main power supply through the high-speed connectors between boards. A power conversion chip is used to convert 5V into 1.0V, 1.5V, 1.8V, and 3.3V respectively for power supply to the chips on the board. Its external debug interfaces are all directly extended from the PS side. Among them, the JTAG signal and the serial port signal are respectively converted into USB interfaces through signal conversion chips and led out for convenient front-out debugging. At the same time, all its external signals are led out from the high-speed connectors, and the debug interfaces are all led out through the carrier board. All the GPIO on the PS and PL sides are also led out to the carrier board. According to the different functions of the carrier board, the GPIO can be instantiated into the required specific interfaces through the software in the SD card carried on the carrier board to achieve the generality of the core board and the functional differences of the carrier board.

[0029] Its software part is used to implement the operation of the operating system and the running of the automatic test program. It is equipped with a Linux operating system based on POSIX, which is multi-user, multi-tasking, supports multi-threading and multi-CPUs. It has the characteristics of open source code and a large number of technical community users. The open source code allows users to freely customize, with high flexibility, powerful functions and low cost. Its hardware layer includes a CPU, memory, storage devices, network devices, and peripherals, etc. The kernel layer is the core foundation of the system. It is directly attached to the hardware platform, controls and manages the hardware resources and software resources within the system, effectively organizes the operation of processes, thereby expanding the functions of the hardware and improving the utilization efficiency of resources. It supports multiple file systems such as FAT, FAT32, ext2 / 3 / 4, etc.; The Shell layer is the human-computer interaction interface, which supports entering command lines under the prompt. It is interpreted and executed by the Shell and outputs the corresponding results or relevant information, and realizes diverse system functions by using the rich commands provided by the system. During the startup process, first, U-Boot initializes the ZYNQ chip, memory, etc., then copies the kernel image to the memory, jumps to the corresponding address and starts the system startup process. After that, the system will be responsible for initializing all hardware and loading hardware drivers, loading the system kernel, and finally executing the initialization of the operating system and running the power-on self-start test program to complete the entire startup and automatic test process of the system.

[0030] A communication method for an embedded multi-interface communication system based on fiber optic Ethernet, including a serial port interface communication method, a CAN interface communication method, and a network interface communication method.

[0031] As Figure 4 shown, the specific implementation method of the serial port interface communication method is as follows: The serial port interface communication module has one gigabit fiber optic Ethernet interface and four RS422 serial ports. Among them, the gigabit fiber optic Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed connector between boards. This chip converts the gigabit Ethernet signal into a fiber optic Ethernet signal and outputs it through the front optical module; The four 422 serial ports directly instantiate 4 232 signals through the FPGA, input them into the carrier board through the high-speed connector between boards, then connect the isolated 232 signals to the 422 transceiver chip to convert them into RS422 signals, and finally connect the 4 RS422 signals to the front high-speed connector to achieve interaction with external interfaces.

[0032] As Figure 5As shown in the figure, the specific implementation method of the CAN interface communication method is as follows: The CAN interface communication module has one gigabit fiber Ethernet interface and two CAN interfaces. Among them, the gigabit fiber Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed inter-board connector. This chip converts the gigabit Ethernet signal into a fiber Ethernet signal and outputs it through the front-mounted optical module. The two CAN interfaces directly instantiate 2 CAN signals through the FPGA and input them into the carrier board through the high-speed inter-board connector. Then, the CAN signals are isolated and level protocol-converted by the isolated CAN transceiver chip. Finally, the 2 CAN signals are connected to the front-mounted high-speed connector to achieve interaction with the external interface.

[0033] As Figure 6 As shown in the figure, the specific implementation method of the network interface communication method is as follows: The network interface communication module has one gigabit fiber Ethernet interface and two hundred-megabit Ethernet interfaces. Among them, the gigabit fiber Ethernet interface is implemented by a gigabit Ethernet PHY chip. The core board inputs the gigabit Ethernet signal to the gigabit Ethernet PHY chip through the high-speed inter-board connector. This chip converts the gigabit Ethernet signal into a fiber Ethernet signal and outputs it through the front-mounted optical module. The two hundred-megabit Ethernet interfaces directly instantiate 2 network signals through the FPGA and input them into the carrier board. The network signals are level protocol-converted by the hundred-megabit Ethernet PHY chip, then the network signals are output to the network transformer, and then the 2 Ethernet signals are connected to the front-mounted high-speed connector to achieve interaction with the external interface.

[0034] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manners. Any other implementation manners obtained by those skilled in the art based on the technical solutions of the present invention also belong to the scope of protection of the present invention.

Claims

1. An embedded multi-interface communication system based on optical fiber Ethernet, characterized in that: It includes a main control module, a serial port interface communication module, a CAN interface communication module and a network interface communication module, wherein the main control module is connected to the serial port interface communication module, the CAN interface communication module and the network interface communication module respectively through Gigabit fiber-optic Ethernet, and the main control module, the serial port interface communication module, the CAN interface communication module and the network interface communication module are equipped with the same core board.

2. The embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The main control module includes a core board, a PHY chip and a power conversion module TPS54A24, wherein the power conversion module TPS54A24 is connected to the core board, and the core board outputs optical fiber Ethernet through the PHY chip.

3. The embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The core board includes FPGA, high-speed connector, interface, and memory, wherein the main control module is used to control communication, the high-speed connector is used to connect peripherals, the interface is used for multi-interface input and output, the power conversion module is used to convert the power into various power supplies used by the system, and the memory is used for data storage. The main control module is connected to the high-speed connector, interface, power conversion module and memory respectively, and the interface includes USB-JTAG debugging interface, USB-serial port debugging interface, USB interface, SD card connector, Gigabit Ethernet and HDMI interface.

4. The embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The FPGA includes PS and PL, wherein PS is a processor system with software development resources of an ARM processor; PL is a programmable logic with customization and user expansion functions; wherein PS and PL are connected via an AXI bus for internal data transmission; a core board is equipped with a Linux operating system for realizing the utilization of system resources, and the core board uses the 5V on the carrier board as the main power supply through an inter-board high-speed connector, and uses a power conversion module to convert the 5V into 1.0V, 1.5V, 1.8V and 3.3V respectively, which are used to power the chips on the board; external debugging interfaces are directly extended from the PS side, wherein JTAG signals and serial port signals are converted to USB interfaces respectively via signal conversion chips for output, which is convenient for front-end debugging; all external signals are output from high-speed connectors, and debugging interfaces are all output through the carrier board, and all GPIOs on the PS and PL sides are also output to the carrier board.

5. A communication method of an embedded multi-interface communication system based on optical fiber Ethernet according to any one of claims 1 to 4, characterized in that: It includes a serial port interface communication method, a CAN interface communication method and a network interface communication method.

6. The communication method of the embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The specific implementation method of the serial port interface communication method is as follows: the serial port interface communication module has one Gigabit fiber-optic Ethernet interface and four RS422 serial port interfaces, wherein the Gigabit fiber-optic Ethernet interface is implemented by a Gigabit Ethernet PHY chip, and the core board inputs the Gigabit Ethernet signal to the Gigabit Ethernet PHY chip through an inter-board high-speed connector, and the chip converts the Gigabit Ethernet signal into a fiber-optic Ethernet signal and outputs it through a front optical module; the four-channel 422 serial port directly instantiates four-channel 232 signals through an FPGA, and inputs them into a carrier board through an inter-board high-speed connector, and then the isolated 232 signals are connected to a 422 transceiver chip to be converted into RS422 signals, and finally the four-channel RS422 signals are connected to the front high-speed connector to realize interaction with an external interface.

7. The communication method of the embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The specific implementation method of the CAN interface communication method is as follows: the CAN interface communication module has one Gigabit fiber-optic Ethernet interface and two CAN interfaces, wherein the Gigabit fiber-optic Ethernet interface is implemented by a Gigabit Ethernet PHY chip, and the core board inputs the Gigabit Ethernet signal to the Gigabit Ethernet PHY chip through an inter-board high-speed connector, and the chip converts the Gigabit Ethernet signal into a fiber-optic Ethernet signal and outputs it through a front optical module; the two CAN interfaces directly instantiate two CAN signals through FPGA, and input them into the carrier board through the inter-board high-speed connector, and then isolate the CAN signals and convert the level protocol through the isolation CAN transceiver chip, and finally connect the two CAN signals to the front high-speed connector to realize interaction with the external interface.

8. The communication method of the embedded multi-interface communication system based on optical fiber Ethernet according to claim 1, characterized in that: The specific implementation method of the network interface communication method is as follows: the network interface communication module has one Gigabit fiber optic Ethernet interface and two 100M Ethernet interfaces, wherein the Gigabit fiber optic Ethernet interface is implemented by a Gigabit Ethernet PHY chip, the core board inputs the Gigabit Ethernet signal to the Gigabit Ethernet PHY chip through an inter-board high-speed connector, the chip converts the Gigabit Ethernet signal into a fiber optic Ethernet signal, and outputs it through a front optical module; the two 100M Ethernet interfaces directly instantiate two network signals through FPGA, and input them into the carrier board through the inter-board high-speed connector, perform level protocol conversion on the network signal through the 100M Ethernet PHY chip, and then output the network signal to the network transformer, and then connect the two Ethernet signals to the front high-speed connector to realize interaction with the external interface.

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