Optical fiber sensing high-speed data acquisition and processing method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an optical fiber sensing high-speed data collecting and processing method based on an FPGA. The method comprises the steps that a user side server initializes configuration register information; the ADC module samples the optical fiber sensing signal according to the register information to obtain first signal data; the data processing module performs data processing on the first signal data according to the register information to obtain second signal data; the data caching module caches the second signal data; the client server reads the cache data information through the data state register and reads the second signal data through the PCIE; when the working mode needs to be switched or collection is stopped, the user side server closes working enabling through PCIE, and a cache clearing register is configured to clear cache data. According to the technical scheme provided by the embodiment of the invention, the inside of the FPGA can be automatically switched to the working mode required by the user according to the configuration register and starts to work, so that the flexible switching of the working mode is realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of optical fiber signal acquisition, and in particular to an optical fiber sensing high-speed data acquisition and processing method based on FPGA. Background Art

[0002] Fiber optic sensing technology has risen rapidly in recent years along with the rapid development of fiber optic communication technology, and has the advantages of wide working frequency band and large dynamic range. In addition, the optical fiber itself is non-electrical, small in size, light in weight, easy to bend, and has strong anti-electromagnetic interference ability. It is particularly suitable for use in harsh environments such as flammable and explosive environments, strictly restricted spaces, and strong electromagnetic interference. It has gradually been widely used in smart grids, environmental monitoring, medical diagnosis, industrial automation and other fields.

[0003] FPGA has the ability to process data in real time at high speed and in parallel, and has become an important part of the acquisition and processing of optical fiber sensor signals. However, when FPGA is performing data acquisition, it is not possible to switch the acquired data sensitively, nor is it possible to switch the data acquisition channel and data processing method, and thus cannot meet the needs of different working modes for optical fiber sensor data.

[0004] Therefore, how to flexibly switch between different working modes during the acquisition process of optical fiber sensing signals is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present invention provides a method for collecting and processing high-speed data of optical fiber sensing based on FPGA, which realizes the needs for optical fiber sensing data in different working modes.

[0006] In order to achieve the purpose of this application, this application provides a high-speed data acquisition and processing method for optical fiber sensing based on FPGA, including:

[0007] S101: The user-side server initializes configuration register information, and after the initialization configuration is completed, turns on the work enable; the register information is information required for the FPGA operation process; the FPGA is provided with an ADC module, a data processing module, and a data cache module;

[0008] S102: the ADC module samples the optical fiber sensing signal according to the register information to obtain first signal data, and transmits the first signal data to the data processing module;

[0009] S103: the data processing module processes the first signal data according to the register information to obtain second signal data;

[0010] S104: The data cache module caches the second signal data, and sends the cached data information to the user-side server through the data status register;

[0011] S105: The user-side server reads the cached data information, and reads the second signal data through PCIE;

[0012] S106: When it is necessary to switch the working mode or stop the collection, the user-side server turns off the working enable through PCIE and configures the cache clearing register to clear the cache data.

[0013] Optionally, the register information includes: register parameters, register acquisition mode, register sampling rate;

[0014] The register parameters include: frequency control word, phase control word, pulse width, and pulse frequency of DDS;

[0015] The register acquisition mode includes: switching the mode according to the data that the host computer needs to collect; the data that the host computer needs to collect includes: one or more of original data, IQ demodulated data, IQ demodulated filtered data, amplitude phase data, and phase unwrapped data;

[0016] The register sampling rate includes: Data downsampling, N is a positive integer.

[0017] Optionally, the ADC module includes: an ADC acquisition module, an ADC zero point calibration module, and a synchronous sampling module;

[0018] The ADC module data sampling, processing and sending process is as follows:

[0019] S201: The ADC acquisition module acquires the optical fiber sensing signal to obtain ADC acquisition data;

[0020] S202: The ADC zero point calibration module performs zero point calibration on the ADC collected data to obtain ADC zero point calibration data;

[0021] S203: The synchronous sampling module samples the ADC zero point calibration data to obtain first signal data.

[0022] Optionally, the workflow of the ADC zero point calibration module is specifically as follows:

[0023] S301: The ADC zero point calibration module calculates the average value of the 2 seconds of data collected by the ADC acquisition module, and writes the average value into the EEPROM as an offset;

[0024] S302: The ADC zero point calibration module subtracts the offset from the optical fiber sensing signal acquired by the ADC acquisition module to obtain ADC zero point calibration data.

[0025] Optionally, the workflow of the synchronous sampling module is specifically as follows:

[0026] S401: Determine whether synchronous sampling is used, if not, execute S4011; if yes, execute S4012;

[0027] S4011: Turn on the acquisition enable and continuously collect data;

[0028] S4012: Select the synchronization mode and the synchronization trigger acquisition mode, and execute S4013;

[0029] S4013: Turn on sampling enable and collect data synchronously.

[0030] Optionally, the synchronous trigger acquisition mode includes: rising edge trigger acquisition and falling edge trigger acquisition; the rising edge trigger acquisition and the falling edge trigger acquisition are synchronized through a synchronous trigger pulse;

[0031] The synchronous trigger pulse includes: an internal synchronous pulse and an external synchronous pulse;

[0032] The internal synchronization pulse uses the register information configured by the user-side server to generate a synchronization pulse inside the FPGA;

[0033] The external synchronization pulse is connected to the external synchronization pulse signal through the SMA radio frequency connector.

[0034] Optionally, the data processing module includes: a DDS module, a digital orthogonal mixing module, a FIR filtering module, a CORDIC module, a dewrapping module, a data selection module, and a downsampling module;

[0035] The workflow of the data processing module is specifically as follows:

[0036] S501: The DDS module generates a SIN signal and a COS signal and sends them to a digital quadrature mixing module;

[0037] S502: The digital orthogonal mixing module performs orthogonal mixing on the first signal data, the SIN signal and the COS signal to obtain IQ data;

[0038] S503: The FIR filter module filters the IQ data to generate filtered IQ data;

[0039] S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data;

[0040] S505: The de-wrapping module de-wrappes the amplitude phase data to obtain de-wrapped phase data;

[0041] S506: the data selection module uses the original data, IQ data, filtered IQ data, amplitude phase data, and unwrapped phase data as optional data, and selects corresponding data from the optional data according to the register acquisition mode configured by the user end server and sends them to the downsampling module;

[0042] S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user-side server.

[0043] Optionally, the data cache module is composed of a first FIFO, a DDR3 controller and DDR3;

[0044] The first FIFO converts the data bit width;

[0045] The DDR3 controller writes data into DDR3 or reads data from DDR3;

[0046] The DDR3 performs data caching.

[0047] Optionally, the data sending module is composed of a second FIFO and an XDMA;

[0048] The second FIFO is used to convert the clock domain between the DDR3 and PCIE interfaces;

[0049] The XDMA reads the cache data in the first FIFO and DDR3 according to the read operation of the client server.

[0050] Optionally, when it is necessary to switch the working mode, the user-side server first stops the current working mode, and configures the cache clear register to clear the FIFO cache, DDR3 cache, and data status register in sequence, then configures the parameters of the next working mode, and finally configures the working enable; the FIFO cache includes: a first FIFO cache and a second FIFO cache.

[0051] Compared with the prior art, the FPGA-based optical fiber sensing high-speed data acquisition and processing method provided by the present invention uses an FPGA optical fiber sensing high-speed acquisition card as a platform, based on PCIE, ADC module, and data cache module, pre-configures register information required during FPGA operation, performs data acquisition and processing according to the register information, and switches the register information when the working mode needs to be switched to realize the needs of different working modes for optical fiber sensing data.

[0052] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a flow chart of a high-speed data acquisition and processing method for optical fiber sensing based on FPGA provided by the present invention;

[0055] Figure 2 It is a structural block diagram of an FPGA internal sampling processing and sending module provided by the present invention;

[0056] Figure 3 It is a flow chart of an ADC zero point calibration module provided by the present invention;

[0057] Figure 4 It is a schematic diagram of a synchronous work process provided by the present invention;

[0058] Figure 5 It is a workflow diagram of a data processing module provided by the present invention;

[0059] Figure 6 It is a schematic diagram of a mode switching process provided by the present invention. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0062] Embodiment 1

[0063] Before introducing the technical solution of the embodiment of the present invention, it should be noted that the prior art has at least the following problems when performing data collection:

[0064] 1. There is no flexible switching between original data, IQ demodulated data, low-pass filtered data, phase demodulated data, and amplitude demodulated data;

[0065] 2. The sampling rate of the fiber optic sensor acquisition channel is not flexibly configured;

[0066] 3. The low-pass filter coefficients were not reconfigured.

[0067] To this end, an embodiment of the present invention proposes a high-speed data acquisition and processing method for optical fiber sensing based on FPGA, the purpose of which is to at least solve the above-mentioned known problems.

[0068] The following describes the FPGA-based optical fiber sensing high-speed data acquisition and processing method according to an embodiment of the present invention in conjunction with the accompanying drawings.

[0069] Figure 1 A flow chart of a FPGA-based fiber optic sensor high-speed data acquisition and processing method provided in an embodiment of the present invention is provided. This embodiment is applicable to the situation of high-speed acquisition of fiber optic sensor data in different working modes. The method can be executed by the FPGA fiber optic sensor high-speed acquisition card in the embodiment of the present invention. The FPGA fiber optic sensor high-speed acquisition card used in this embodiment has 1 x8 PCIE client server interface, 4 250Mhz sampling rate fiber optic sensor signal acquisition channels, 2 clock synchronization or pulse synchronization interfaces, 2 500Mhz conversion rate high-speed digital-to-analog conversion interfaces, 1 SFP+10Gbps high-speed fiber optic network interface and 2 1Gbps power grid ports.

[0070] like Figure 1 As shown, the method specifically comprises the following steps:

[0071] S101: The user-side server initializes configuration register information, and after the initialization configuration is completed, turns on the work enable.

[0072] Among them, the register information is the information required for the FPGA operation process; the FPGA is provided with an ADC module, a data processing module, a data cache module, etc.

[0073] The register information includes: register parameters, register acquisition mode, register sampling rate, etc.

[0074] Furthermore, the register parameters include: frequency control word, phase control word, pulse width, pulse frequency, etc. of DDS.

[0075] Furthermore, the register acquisition mode includes: switching modes according to the data that the host computer needs to collect, etc.; wherein, the data that the host computer needs to collect includes: one or more of: original data, IQ demodulated data, IQ demodulated filtered data, amplitude phase data, phase unwrapping data, etc.

[0076] In an embodiment of the present invention, by setting the register acquisition mode, 1 to 4 channels of original data, 1 to 4 channels of IQ demodulated data, 1 to 4 channels of low-pass filtered data, 1 to 4 channels of phase demodulated data, and 1 to 4 channels of amplitude demodulated data can be flexibly switched, so that different host computer configurations can flexibly switch modes to meet the needs of the system.

[0077] Furthermore, the register sampling rate includes: Data downsampling, N is a positive integer. By setting the register sampling rate, the sampling rate of the 4-channel fiber optic sensor acquisition channel can be flexibly configured.

[0078] After the user-side server completes the initialization configuration and turns on the work enable, the FPGA starts working.

[0079] Figure 2 The present invention provides a block diagram of a FPGA internal sampling processing and sending module, and specifically relates to a process of ADC data sampling processing and sending. Figure 2 , the ADC data sampling process is as follows:

[0080] S201: The ADC acquisition module acquires the optical fiber sensor signal to obtain ADC acquisition data;

[0081] S202: The ADC zero point calibration module performs zero point calibration on the ADC collected data to obtain ADC zero point calibration data;

[0082] S203: The synchronous sampling module samples the ADC zero point calibration data to obtain first signal data.

[0083] Specifically, the optical fiber sensing signal is collected through the ADC acquisition module, that is, 4-channel AD9642. The collected data is calibrated through the ADC zero point calibration module to calibrate the DC bias of the signal to obtain ADC zero point calibration data. The calibrated data enters the synchronous sampling module, and continuous collection, rising edge triggered collection or falling edge triggered collection are performed in the synchronous sampling module according to the register parameter configuration to obtain the first signal data.

[0084] Continuous acquisition does not require a synchronization signal, while rising edge triggered acquisition or falling edge triggered acquisition needs to be synchronized according to the synchronization trigger pulse.

[0085] The synchronization trigger pulse can use an internal synchronization pulse or an external synchronization pulse: the internal synchronization pulse uses the pulse width and pulse frequency configured by the user-side server to generate a synchronization pulse inside the FPGA; external synchronization requires access to an external synchronization pulse signal through an SMA RF connector.

[0086] Furthermore, the data sampled by the synchronous trigger pulse flows into the data processing module, in which the data is IQ demodulated and phase amplitude data, etc. are generated. The corresponding data type is output according to the register acquisition mode configured by the user-side server, and the output data enters the data cache module. The data output by the data processing module is the second signal data.

[0087] Furthermore, the data cache module caches the second signal data. The data cache module is mainly composed of a first FIFO, a DDR3 controller and a DDR3. The first FIFO converts the data bit width, for example, the first FIFO is responsible for converting the data bit width from 16-bit or 32-bit data to 512-bit bit width. The DDR3 controller writes data to the DDR3, or reads data from the DDR3, for example, the DDR3 controller writes 512-bit bit width data to the DDR3 or reads 512-bit bit width data from the DDR3, and then converts the 512-bit bit width data into 128-bit bit width data through the first FIFO. DDR3 performs data cache.

[0088] Furthermore, when the user-side server needs to read the second signal data, the data sending module obtains the second signal data from the data buffer module and sends the second signal data to the user-side server through PCIE, and the user-side server reads the second signal data through PCIE.

[0089] The data sending module is called by the PCIE driver to inform the user-side server of the amount of data written to DDR3 through the data status register, and informs the user-side server through the data status register when DDR3 is almost full. The user-side server can clear the data cached in the first FIFO and DDR3 through the cache clear register.

[0090] The data sending module is mainly composed of the second FIFO and XDMA. The second FIFO is mainly used to convert the clock domain between the DDR3 and PCIE interfaces. At the same time, it can cache a certain amount of data to prevent errors in the data read by PCIE through XDMA. XDMA reads the cached data in the first FIFO and DDR3 according to the read operation of the user-side server.

[0091] Furthermore, the register module is mounted on XDMA through AXI LITE, and the user-side server configures the registers to control the parameters and operating status of all modules.

[0092] S102: The ADC module samples the optical fiber sensing signal according to the register information to obtain first signal data, and transmits the first signal data to the data processing module.

[0093] Specifically, the internal ADC module includes: ADC acquisition module, ADC zero point calibration module, synchronous sampling module and the like.

[0094] The ADC acquisition module acquires the optical fiber sensing signal, the ADC zero point calibration module calibrates the acquired signal, and the synchronous sampling module synchronously acquires the calibrated data.

[0095] Figure 3 This is a flow chart of an ADC zero calibration module provided by the present invention. The specific flow is as follows:

[0096] S301: The ADC zero point calibration module calculates the average value of the 2 seconds of data collected by the ADC acquisition module, and writes the average value into the EEPROM as an offset;

[0097] S302: The ADC zero point calibration module subtracts the offset from the optical fiber sensing signal acquired by the ADC acquisition module to obtain ADC zero point calibration data.

[0098] Specifically, the user-side server turns on the zero-point calibration enable, and the ADC zero-point calibration module calculates the average value of the 2-second data collected by the ADC acquisition module as the offset, and writes the offset into the EEPROM; the user-side server turns off the zero-point calibration enable, turns on the ADC acquisition enable, the ADC acquisition module collects the optical fiber sensor signal, and reads the offset in the EEPROM; the ADC zero-point calibration module subtracts the offset from the optical fiber sensor signal collected by the ADC acquisition module to obtain the ADC zero-point calibration data.

[0099] Furthermore, when performing ADC zero-point calibration, the front-end SMA interface of the internal ADC module cannot receive any signal. After the user-side server sends the zero-point calibration enable command, the zero-point calibration module turns on the ADC acquisition module to collect 2 seconds of data and calculates the average value. This average value is the zero-point offset of the ADC. This average value is written into the EEPROM. When the data acquisition enable is turned on later, the collected data will be automatically calibrated according to the zero-point offset read from the EEPROM to eliminate the zero-point offset of the hardware itself.

[0100] In an embodiment of the present invention, an ADC zero point calibration function is provided, which can automatically calibrate the zero point drift of the ADC and record it in the EEPROM. When the ADC collects data, it will automatically read the zero point drift amount from the EEPROM to perform zero point calibration on each ADC to ensure the accuracy of the sampling signal.

[0101] Figure 4 This is a schematic diagram of a synchronous work process provided by the present invention, and the process is as follows:

[0102] S401: Determine whether synchronous sampling is adopted, if not, execute S4011; if yes, execute S4012.

[0103] S4011: Turn on the acquisition enable and continuously collect data.

[0104] S4012: Select the synchronization mode and the synchronization trigger acquisition mode, and execute S4013.

[0105] S4013: Turn on sampling enable and collect data synchronously.

[0106] Specifically, when the synchronization enable is not turned on, the acquisition enable is turned on, and the acquisition mode is continuous acquisition. At this time, the collected data is continuous data collected according to the sampling rate. There is no breakpoint in the middle of the data, and the collected signal should be a complete signal;

[0107] When the synchronization is enabled, the rising edge of the synchronization pulse triggers the acquisition according to the set number of sampling points and the sampling rate. For example, if the sampling rate is set to 250Mhz and 10,000 points are sampled according to the rising edge trigger, the synchronous sampling module will start collecting data at a sampling rate of 250Mhz based on the rising edge of the synchronization pulse, stop after collecting 10,000 points, and start sampling 10,000 points at the next rising edge at a collection rate of 250Mhz, and repeat this process. The synchronization mode (synchronization source) can select an external synchronization pulse or an internally generated synchronization pulse.

[0108] In the embodiment of the present invention, two-way synchronization pulse input or output can be controlled. If an external synchronization pulse is used, the internal synchronization acquisition is synchronized using the external synchronization signal. If an internal pulse synchronization is used, the synchronization acquisition is synchronized using the internal pulse signal.

[0109] S103: The data processing module processes the first signal data according to the register information to obtain second signal data.

[0110] Among them, the data processing module includes: DDS module, digital orthogonal mixing module, FIR filtering module, CORDIC module, de-wrapping module, data selection module, downsampling module and so on.

[0111] Figure 5 This is a workflow diagram of a data processing module provided by the present invention. The specific workflow is as follows:

[0112] S501: The DDS module generates a SIN signal and a COS signal and sends them to a digital quadrature mixing module;

[0113] S502: The digital orthogonal mixing module performs orthogonal mixing on the first signal data, the SIN signal and the COS signal to obtain IQ data;

[0114] S503: The FIR filter module filters the IQ data to generate filtered IQ data;

[0115] S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data;

[0116] S505: The de-wrapping module de-wrappes the amplitude phase data to obtain de-wrapped phase data;

[0117] S506: the data selection module uses the original data, IQ data, filtered IQ data, amplitude phase data, and unwrapped phase data as optional data, and selects corresponding data from the optional data according to the register acquisition mode configured by the user end server and sends them to the downsampling module;

[0118] S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user-side server.

[0119] Specifically, the first signal data enters the data processing module and the SIN and COS generated by the DDS module are orthogonally mixed in the digital orthogonal mixing module, and IQ data is generated after digital orthogonal mixing. The frequency and phase of the SIN and COS generated by the DDS are generated by the frequency control word and phase control word configured by the user-side server.

[0120] The IQ data is digitally FIR filtered to generate filtered IQ data, where the FIR filter order is fixed and the low-pass cutoff frequency can be configured. By reconfiguring the low-pass filter coefficients, a higher signal-to-noise ratio can be ensured after the collected signal is processed according to the usage scenario.

[0121] The filtered IQ data is sent to the CORDIC module to calculate the corresponding amplitude and phase to obtain amplitude and phase data.

[0122] The amplitude and phase data are sent to the unwinding module to calculate the amplitude and phase data after unwinding, that is, the unwinding phase data.

[0123] The original data, IQ data, filtered IQ data, amplitude phase data, and unwrapped phase data enter the data selection module as optional data; the data selection module selects corresponding data from the optional data according to the register acquisition mode configured by the user-side server and sends it to the downsampling module.

[0124] The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user-side server, and the corresponding data is sent out after being downsampled, and the entire data processing process in the data processing module is completed.

[0125] S104: The data cache module caches the second signal data, and sends the cache data information to the user-side server through the data status register.

[0126] There are many control registers inside the FPGA, such as work enable register, synchronization mode register, synchronization pulse frequency control register, synchronization pulse width register, data type control register, data status register and many other registers. These registers are mounted on the PCIE port through the AXI bus of pcie_axi_apb.

[0127] The cache data information includes: the data volume and data status of the second signal data.

[0128] S105: The user-side server reads the cache data information and reads the second signal data through PCIE.

[0129] In an embodiment of the present invention, the ADC module inside the FPGA obtains the first signal data according to the register parameters configured by the user-side server, and the data processing module performs data processing according to the register acquisition mode and register sampling rate configured by the user-side server to obtain the second signal data, and sends the second signal data to the DDR3 cache, and informs the user-side server of the total amount of data currently cached through the data status register. The user-side server periodically scans the status register and reads the data cached in the DDR3 according to the status register.

[0130] S106: When it is necessary to switch the working mode or stop the collection, the user-side server turns off the working enable through PCIE and configures the cache clearing register to clear the cache data.

[0131] Figure 6 It is a flow chart of a mode switching provided by the present invention. When switching the working mode, the user-side server must first send a stop command to stop the current working mode, and then send a clear command to clear the first FIFO and the second FIFO cache data, clear the DDR3 cache data, and clear the status register. The user-side server then configures the parameters required for the next working mode, including synchronization pulse control parameters, parameters required for data processing, and parameters required for data buffering, and then configures the working enable, so that it will work according to the current configuration mode.

[0132] In summary, the user-side server of the embodiment of the present invention controls the register mounted on the PCIE end to initialize the relevant parameters that need to be configured during the operation of the FPGA, such as data type, number of working channels, DDS frequency control word required for IQ demodulation, filtering parameters, etc. After the configuration is completed, the work enable is started, the ADC will start to collect data, and the collected data will be processed later according to the configured working mode, and the processed data will be read to the user-side server by PCIE after being cached. If the acquisition mode needs to be changed, the user-side server can turn off the work enable, call the cache clear register to clear the FPGA internal FIFO cache and DDR3 internal cache data, and configure the required acquisition mode register, turn on the work enable, and the FPGA can automatically switch to the user's required working mode according to the configuration register and start working.

[0133] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0134] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for high-speed data acquisition and processing of optical fiber sensing based on FPGA, characterized in that: include: S101: The user-side server initializes configuration register information, and after the initialization configuration is completed, turns on the work enable; the register information is information required for the FPGA operation process; the FPGA is provided with an ADC module, a data processing module, and a data cache module; S102: the ADC module samples the optical fiber sensing signal according to the register information to obtain first signal data, and transmits the first signal data to the data processing module; S103: the data processing module processes the first signal data according to the register information to obtain second signal data; S104: The data cache module caches the second signal data, and sends the cached data information to the user-side server through the data status register; S105: The user-side server reads the cached data information, and reads the second signal data through PCIE; S106: When it is necessary to switch the working mode or stop the collection, the user-side server turns off the working enable through PCIE and configures the cache clearing register to clear the cache data.

2. The method according to claim 1, characterized in that The register information includes: register parameters, register acquisition mode, and register sampling rate; The register parameters include: frequency control word, phase control word, pulse width, and pulse frequency of DDS; The register acquisition mode includes: switching the mode according to the data that the host computer needs to collect; the data that the host computer needs to collect includes: one or more of original data, IQ demodulated data, IQ demodulated filtered data, amplitude phase data, and phase unwrapped data; The register sampling rate includes: Data downsampling, N is a positive integer.

3. The method according to claim 1, characterized in that The ADC module includes: an ADC acquisition module, an ADC zero point calibration module, and a synchronous sampling module; The ADC module data sampling, processing and sending process is as follows: S201: The ADC acquisition module acquires the optical fiber sensing signal to obtain ADC acquisition data; S202: The ADC zero point calibration module performs zero point calibration on the ADC collected data to obtain ADC zero point calibration data; S203: The synchronous sampling module samples the ADC zero point calibration data to obtain first signal data.

4. The method according to claim 3, characterized in that The specific working process of the ADC zero point calibration module is as follows: S301: The ADC zero point calibration module calculates the average value of the 2 seconds of data collected by the ADC acquisition module, and writes the average value into the EEPROM as an offset; S302: The ADC zero point calibration module subtracts the offset from the optical fiber sensing signal acquired by the ADC acquisition module to obtain ADC zero point calibration data.

5. The method according to claim 3, characterized in that: The workflow of the synchronous sampling module is specifically as follows: S401: Determine whether synchronous sampling is used, if not, execute S4011; if yes, execute S4012; S4011: Turn on the acquisition enable and continuously collect data; S4012: Select the synchronization mode and the synchronization trigger acquisition mode, and execute S4013; S4013: Turn on sampling enable and collect data synchronously.

6. The method according to claim 5, characterized in that The synchronous trigger acquisition mode includes: rising edge trigger acquisition and falling edge trigger acquisition; the rising edge trigger acquisition and the falling edge trigger acquisition are synchronized through a synchronous trigger pulse; The synchronous trigger pulse includes: an internal synchronous pulse and an external synchronous pulse; The internal synchronization pulse uses the register information configured by the user-side server to generate a synchronization pulse inside the FPGA; The external synchronization pulse is connected to the external synchronization pulse signal through the SMA radio frequency connector.

7. The method according to claim 1 or 3, characterized in that: The data processing module includes: a DDS module, a digital orthogonal mixing module, a FIR filtering module, a CORDIC module, a de-wrapping module, a data selection module, and a down-sampling module; The workflow of the data processing module is specifically as follows: S501: The DDS module generates a SIN signal and a COS signal and sends them to a digital quadrature mixing module; S502: The digital orthogonal mixing module performs orthogonal mixing on the first signal data, the SIN signal and the COS signal to obtain IQ data; S503: The FIR filter module filters the IQ data to generate filtered IQ data; S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data; S505: The de-wrapping module de-wrappes the amplitude phase data to obtain de-wrapped phase data; S506: the data selection module uses the original data, IQ data, filtered IQ data, amplitude phase data, and unwrapped phase data as optional data, and selects corresponding data from the optional data according to the register acquisition mode configured by the user end server and sends them to the downsampling module; S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user-side server.

8. The method according to claim 3, characterized in that The data cache module is composed of a first FIFO, a DDR3 controller and DDR3; The first FIFO converts the data bit width; The DDR3 controller writes data into DDR3 or reads data from DDR3; The DDR3 performs data caching.

9. The method according to claim 8, characterized in that The data sending module is composed of a second FIFO and an XDMA; The second FIFO is used to convert the clock domain between the DDR3 and PCIE interfaces; The XDMA reads the cache data in the first FIFO and DDR3 according to the read operation of the client server.

10. The method according to claim 9, characterized in that When the working mode needs to be switched, the user-side server first stops the current working mode, and configures the cache clearing register to clear the FIFO cache, DDR3 cache, and data status register in sequence, then configures the parameters of the next working mode, and finally configures the working enable; The FIFO buffer includes: a first FIFO buffer and a second FIFO buffer.

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