Analogue simulation method and device of flash memory device, equipment and medium

Abstract

The invention provides an analogue simulation method and device for flash memory equipment, equipment and a medium, and relates to the technical field of memory equipment emulation.The method comprises the steps that configuration parameters and first test data of to-be-simulated flash memory equipment are obtained; adjusting parameters of a pre-constructed initial flash memory simulation model according to the configuration parameters to obtain a flash memory simulation model; determining a first simulation parameter according to the configuration parameter and a configured simulation requirement; and based on the first simulation parameter and the first test data, performing analogue simulation on the flash memory simulation model to obtain an analogue simulation result of the to-be-simulated flash memory device. According to the method, different flash memory manufacturer particles can be simulated through configuration of different numbers and sizes of blk and pages; according to the invention, the number and distribution of the initial factory bad blocks can be set to simulate the bad block condition in actual production; according to the invention, the end-of-life disk can be simply constructed by modifying the PEC values of all blk.

Description

Technical Field

[0001] The present application relates to the field of memory device simulation technology, and in particular to a flash memory device simulation method, apparatus, device and medium. Background Art

[0002] With the rapid development of information technology and big data, flash memory devices are increasingly used in the field of data storage. However, the performance and reliability of flash memory devices are affected by many factors, such as bad blocks, temperature, ECC capability, UNC, etc. In order to discover and solve potential problems before actual deployment, a flash memory simulation model that can simulate various working conditions and error scenarios is needed.

[0003] Existing flash memory simulation models can only simulate erase operations, and cannot dynamically adjust simulation scenarios and parameters, nor can they simulate flash memory devices of different structures and sizes. At the same time, existing performance testing methods for flash memory devices mostly use actual storage particles in actual systems for long-cycle testing coverage, which is not only time-consuming, but also the results obtained are incomplete and inaccurate. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a simulation method, apparatus, device and medium for a flash memory device, so as to solve the above-mentioned problems existing in the prior art, and to achieve a comprehensive evaluation of the performance, stability and error handling capability of the flash memory device through precise simulation and flexible configuration.

[0005] In a first aspect, a simulation method for a flash memory device is provided, and the method may include:

[0006] Acquire configuration parameters and first test data of the flash memory device to be simulated;

[0007] According to the configuration parameters, the parameters of the pre-built initial flash memory simulation model are adjusted to obtain the flash memory simulation model;

[0008] Determining first simulation parameters according to the configuration parameters and the configured simulation requirements;

[0009] Based on the first simulation parameters and the first test data, the flash memory simulation model is simulated to obtain a simulation result of the flash memory device to be simulated.

[0010] In an optional implementation, the simulation requirement includes: a simulation type and a custom parameter corresponding to the simulation type;

[0011] The simulation types include: read operation simulation, write operation simulation, erase operation simulation, temperature simulation and error correction capability simulation;

[0012] The first simulation parameters include: physical address, number of times and speed.

[0013] In an optional implementation, when the simulation type is a write operation simulation, the physical address, number of times and speed are respectively the write address, write number and write speed of the first test data; the first simulation parameter also includes: write delay time;

[0014] Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes:

[0015] Acquire first test data;

[0016] Based on the write count, write speed and write delay time, write the first test data to the write address of the flash memory simulation model, obtain a write completion result, and obtain a write start time and a write completion time of the first test data;

[0017] Taking the data volume of the first test data as the throughput of the write operation simulation;

[0018] Based on the write start time, the write completion time and the write completion result, a write operation simulation result of the flash memory device to be simulated under the throughput is determined.

[0019] In an optional implementation, when the simulation type is a read operation simulation or an erase operation simulation, the flash memory simulation model is simulated based on the first simulation parameter to obtain a simulation result of the flash memory device to be simulated, including:

[0020] Based on the number of times and the speed, the operation corresponding to the simulation type is performed on the data corresponding to the physical address in the simulated flash memory device to obtain a simulation operation result, and the operation parameters when performing the operation corresponding to the simulation type are obtained; wherein the operation parameters include a time parameter for performing the operation;

[0021] Taking the amount of data corresponding to the physical address as the throughput;

[0022] Based on the time parameter and the simulation operation result, a read operation simulation result of the flash memory device to be simulated at the throughput is generated.

[0023] In an optional implementation, when the simulation type is error correction capability simulation, the physical address is a write address of the first test data; the times and speeds include: write times, read times, write speed, and read speed, respectively;

[0024] Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes:

[0025] Acquire first test data;

[0026] Using the first test data and the first simulation parameters as simulated first test data;

[0027] Based on the write count and the write speed, write the simulated first test data into the write address of the flash memory simulation model, and obtain the write start time of the simulated first test data;

[0028] Performing a balance analysis on the first test data; if a balance analysis result of the first test data is unbalanced, performing a random bit flip on the first test data;

[0029] Based on the number of reads and the read speed, data corresponding to the write address is read from the flash memory device to be simulated, and read parameters for reading the data are obtained; the read parameters include: read completion time and read temperature;

[0030] The sum of the amount of the written simulated first test data and the amount of the read data is used as the throughput of the error correction capability simulation;

[0031] Based on the write start time, the read parameters and the read data, a simulation result of the error correction capability of the flash memory device to be simulated under the throughput is generated.

[0032] In an optional implementation, after writing the simulated first test data into the write address of the flash memory simulation model, the method further includes:

[0033] Performing a balance analysis on the first test data; if a balance analysis result of the first test data is unbalanced, performing a random bit flip on the first test data;

[0034] After reading data corresponding to the write address from the flash memory device to be simulated, the method further includes:

[0035] Extracting a second simulation parameter from the read data; wherein the second simulation parameter includes: a second writing temperature or a second erasure number;

[0036] If the temperature difference between the second writing temperature and the reading temperature, the reading temperature or the number of erasures meets the configured bit flipping rule, then based on the temperature difference, the reading temperature and / or the number of erasures, a bit flipping parameter is generated;

[0037] Extracting second test data from the read data, and performing bit flipping on the extracted second test data based on the bit flipping parameter to obtain a data reading result;

[0038] Based on the write start time, the read parameter and the read data, generating a simulation result of the error correction capability of the flash memory device to be simulated under the throughput, including:

[0039] Compare the data reading result with the first test data to obtain a comparison result;

[0040] Based on the write start time, the read parameter and the comparison result, a simulation result of a corresponding simulation type of the flash memory device to be simulated under the throughput is generated.

[0041] In an optional implementation, when the simulation type is temperature simulation, the first simulation parameter further includes: a first write temperature; the operation parameter further includes: a read temperature or an erase temperature; the read parameter further includes: a read temperature;

[0042] Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes:

[0043] Based on the first simulation parameters, read operation simulation, write operation simulation, erase operation simulation and / or error correction capability simulation are performed on the flash memory simulation model to obtain temperature simulation results of the flash memory device to be simulated under the first simulation parameters.

[0044] In a second aspect, a simulation device for a flash memory device is provided, and the device may include:

[0045] An acquisition unit, used for acquiring configuration parameters and first test data of a flash memory device to be simulated;

[0046] An adjusting unit, configured to adjust the parameters of the pre-built initial flash memory simulation model according to the configuration parameters to obtain the flash memory simulation model;

[0047] A determination unit, configured to determine a first simulation parameter according to the configuration parameter and a configured simulation requirement;

[0048] A simulation unit is used to simulate the flash memory simulation model based on the first simulation parameters and the first test data to obtain a simulation result of the flash memory device to be simulated.

[0049] In a third aspect, an electronic device is provided, the electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0050] Memory, used to store computer programs;

[0051] The processor is used to implement any method step described in the first aspect when executing the program stored in the memory.

[0052] In a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any method step described in the first aspect is implemented.

[0053] This application uses ps as the time granularity, which can accurately simulate the dynamic changes of flash memory devices at a microscopic time scale, and can more accurately analyze performance, latency, and IO path time consumption. This application can simulate the read, write, or erase operations of particles; this application can be flexibly configured, and can simulate particles from different flash memory manufacturers through the configuration of different blk, page numbers and sizes, adapt as early as possible, and shorten the development cycle; this application can set the initial factory bad block number and distribution to simulate the bad block situation in actual production; this application can set the blk / page size to adapt to flash memory devices of different specifications and requirements. This application can simply construct a disk at the end of its life by modifying the PEC value of all blks.

[0054] This application allows users to adjust the delay time of writing and reading to simulate flash memory devices with different performance levels. By adjusting the delay parameters, the performance bottleneck of the storage system can be evaluated and optimized; the simulation results of the flash memory device to be simulated in this application include data such as response time under different throughputs, which can be used by users for performance analysis and tuning.

[0055] This application can configure the time consumed by flash receiving instructions / data and writing / reading data with PS as the granularity. The time consumption data of each stage of the real device can be configured to the model according to the official data provided by each flash manufacturer or using an analyzer. This application can simulate the operation of the real device very well. It can preliminarily understand the performance of the disk and more intuitively discover the time consumption of each stage, the delay of each IO, the throughput per unit time, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1A flowchart of a simulation method for a flash memory device provided in an embodiment of the present application;

[0058] Figure 2 A schematic diagram of a configuration process provided for an embodiment of the present application;

[0059] Figure 3 A schematic diagram of bad block feedback provided in an embodiment of the present application;

[0060] Figure 4 A bit flipping flow chart provided for an embodiment of the present application;

[0061] Figure 5 A schematic diagram of data retention capability simulation provided by an embodiment of the present application;

[0062] Figure 6 A comparison chart of the relationship between the probability of a bit flip and PEC provided in an embodiment of the present application;

[0063] Figure 7 A schematic diagram of temperature-controlled bit flipping provided in an embodiment of the present application;

[0064] Figure 8 A schematic diagram of the structure of a flash memory device simulation method and apparatus provided in an embodiment of the present application;

[0065] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0067] SSD stands for Solid State Disk; PEC stands for program erase cycle; EOL stands for end of life.

[0068] The simulation method of the flash memory device provided in the embodiment of the present application can be applied in a server or in a terminal with strong computing power. The server can be a physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms. The terminal can be a user equipment (User Equipment, UE) such as a mobile phone, a smart phone, a laptop, a digital broadcast receiver, a personal digital assistant (PDA), a tablet computer (PAD), a handheld device, a vehicle-mounted device, a wearable device, a computing device or other processing equipment connected to a wireless modem, a mobile station (Mobile Station, MS), a mobile terminal (Mobile Terminal), etc. The terminal and the server can be directly or indirectly connected by wired or wireless communication, which is not limited in this application.

[0069] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application may be combined with each other if there is no conflict.

[0070] Figure 1 A flowchart of a method for processing business data provided by an embodiment of the present application. Figure 1 As shown, the method may include:

[0071] Step S110, obtaining configuration parameters of the flash memory device to be simulated and first test data; adjusting parameters of the pre-built initial flash memory simulation model according to the configuration parameters to obtain the flash memory simulation model.

[0072] In an embodiment of the present application, before reading and writing begins, a command interface needs to be opened for the flash memory simulation model, which is used externally to call the command interface to write data to the flash memory simulation model or read data from the flash memory simulation model.

[0073] In an embodiment of the present application, the configuration parameters of the flash memory device to be simulated are obtained by parsing a configuration file of the flash memory device to be simulated; the configuration file is obtained by the manufacturer of the flash memory device to be simulated, and can also be obtained by analyzing the flash memory device to be simulated using a data analysis instrument.

[0074] In the embodiment of the present application, the configuration parameters obtained based on the configuration file include: channel (chanle), CE, die (Die), plane (plane), program / read / erase time (program / read / erase time) blk, page number and size, etc.

[0075] This application simulates particles from different flash memory manufacturers by adjusting the configuration parameters of the flash memory simulation model, which can adaptively simulate different objects and improve the application scenarios of the simulation method.

[0076] In an embodiment of the present application, the configuration parameters of the flash memory device to be simulated are configured during the stage of initializing the flash memory simulation model, and modification is not allowed during operation; in actual applications, the configuration parameters can also be modified by the user according to actual needs, but it is recommended to use the data in the configuration file to avoid distortion of the simulation model.

[0077] In the embodiment of the present application, the test data is data used for simulation.

[0078] In the embodiment of the present application, after the test data is acquired, it is further verified whether the test data is reasonable based on the configuration parameters, and the size of the test data cannot exceed the storage capacity of the flash memory.

[0079] Step S120, determining first simulation parameters according to the configuration parameters and the configured simulation requirements; simulating the flash memory simulation model based on the first simulation parameters and the first test data to obtain a simulation result of the flash memory device to be simulated.

[0080] In an embodiment of the present application, the simulation requirements include: simulation type, custom parameters corresponding to the simulation type and simulation temperature; the simulation types include: read operation simulation, write operation simulation, erase operation simulation, read and write operation simulation, temperature simulation and error correction capability simulation.

[0081] In an embodiment of the present application, the custom parameters include: bad blocks, PEC, function / probability relationship between PEC and data flipping, function / probability relationship between temperature and data flipping and / or operating environment (such as temperature), etc.

[0082] In an embodiment of the present application, a test script or UART serial port information is generated according to configuration parameters and simulation requirements, and the test script includes one or more test instructions; specifically, when the UART serial port input method is adopted, it is not necessary to generate a test script, and only the UART serial port information needs to be generated.

[0083] In an embodiment of the present application, the interface module of the flash memory simulation model parses the test script or obtains UART serial port information to obtain the first simulation parameters; the first simulation parameters include simulation temperature, simulation type, physical address, length, number of times and speed; wherein the physical address is an operation address, such as a write address for a write operation, a read address for a read operation, or an erase address for an erase operation.

[0084] In an embodiment of the present application, the simulation requirements also include: a time granularity parameter; the present application sets the time granularity parameter to picoseconds (ps), which can more accurately analyze the performance, latency, and IO path time consumption.

[0085] In an embodiment of the present application, when the simulation type is a write operation simulation, the first simulation parameters include: simulation temperature, a write address of the first test data, a write count, a write speed, and a write delay time.

[0086] In the embodiment of the present application, when the simulation type is a read operation simulation, the first simulation parameters include: simulation temperature, read address, read times, read speed and read delay time.

[0087] In the embodiment of the present application, when the simulation type is an erase operation simulation, the first simulation parameters include: simulation temperature, erase times, erase speed, erase mode and erase address.

[0088] In an embodiment of the present application, when the simulation type is error correction capability simulation, the first simulation parameters include: simulation temperature, write address of the first test data, number of writes, write speed, write delay time and number of erases.

[0089] In the embodiment of the present application, when the simulation type is read operation simulation, write operation simulation, temperature simulation or error correction capability simulation, the first simulation parameter also includes a data address, which is a result address, such as an address for obtaining write data or a write address for reading data; the data address is obtained by the user in the operating system when applying for a buffer. For write operation simulation, the buffer needs to be completely filled with a custom mode. For read operation simulation, the buffer is used to receive data read from the flash memory device. For obtaining instructions, the flash memory device obtains them through the Interface interface and obtains the parameters passed in.

[0090] In the embodiment of the present application, temperature simulation cannot be performed alone, but must rely on read operation simulation, write operation simulation, erase operation simulation and / or error correction capability simulation. By simulating the read operation, write operation, erase operation or error correction capability at different temperatures, the corresponding results are obtained, and the temperature simulation results are obtained by comparison.

[0091] In the embodiment of the present application, the error correction capability simulation and the read-write operation simulation can be regarded as completing a write operation simulation first, and then completing a read operation simulation.

[0092] In the embodiment of the present application, when performing read operation simulation, write operation simulation or erase operation simulation, if it is desired to exclude the influence of temperature, that is, not to affect the behavior of particles due to temperature, the simulation temperature can be set to the default 30°C and not modified during runtime. This temperature is the ideal operating temperature of NAND particles, and basically no bit flipping due to temperature factors will occur at this temperature. In addition to the factors affecting temperature, there will also be the influence of block life and data 01 imbalance.

[0093] In an embodiment of the present application, when the simulation type is a write operation simulation, the flash memory simulation model is simulated based on the first simulation parameter and the first test data to obtain a simulation result of the flash memory device to be simulated, including:

[0094] Based on the number of writes, the write speed and the write delay time, the first test data is written into the write address of the flash memory simulation model, a write completion result is obtained, and a write start time and a write completion time of the first test data are obtained;

[0095] The time difference between the writing start time and the writing completion time is used as the response time of the writing operation simulation; the data volume of the first test data is used as the throughput of the writing operation simulation;

[0096] Based on the response time and the write completion result, a simulation result of a write operation of the flash memory device to be simulated under throughput is determined.

[0097] In an embodiment of the present application, the write completion result includes whether the write operation is successfully completed; whether the write operation is successfully completed can be determined by obtaining the status code returned when the write data is obtained, or it can be determined based on log records, or it can be determined by ECC verification, or it can be determined by delay monitoring or signal monitoring.

[0098] In the embodiment of the present application, when the simulation type is a read operation simulation, the flash memory simulation model is simulated based on the first simulation parameter to obtain a simulation result of the flash memory device to be simulated, including:

[0099] Based on the read address, the number of reads and the read delay time, data is read from the corresponding read address of the flash memory simulation model to obtain the data read result, and the data read start time and the data read completion time are obtained;

[0100] The time difference between the writing and reading start time and the obtaining and completion time is used as the response time of the read operation simulation; the amount of read data is used as the throughput of the read operation simulation;

[0101] Based on the response time and the data reading result, a read operation simulation result of the flash memory device to be simulated under throughput is determined.

[0102] In the embodiment of the present application, the data reading result includes whether the reading is successful and whether the read data is consistent with the data pre-stored at the address.

[0103] In the embodiment of the present application, when the simulation type is an erase operation simulation, the flash memory simulation model is simulated based on the first simulation parameter to obtain a simulation result of the flash memory device to be simulated, including:

[0104] Based on the erasure times, the erasure speed and the erasure mode, erasing the data corresponding to the erase address in the flash memory device to be simulated, obtaining an erasure result, and obtaining an erasure start time and an erasure completion time for erasing the data;

[0105] Taking the amount of data corresponding to the erase address as the throughput of the erase operation simulation;

[0106] Based on the erase start time, the erase completion time and the erase result, an erase operation simulation result of the flash memory device to be simulated under the throughput, the erase address and the erase mode is generated.

[0107] In the embodiment of the present application, the erasure result includes an erasure report and an erasure verification result, so as to determine whether the erasure has achieved the expected effect.

[0108] In an embodiment of the present application, when the simulation type is a read-write operation simulation, the flash memory simulation model is simulated based on the first simulation parameter and the first test data to obtain a simulation result of the flash memory device to be simulated, including:

[0109] The first test data and the first simulation parameter are used as the simulated first test data; based on the number of writes, the write speed and the write delay time, the simulated first test data is written into the write address of the flash memory simulation model, and the write start time of the simulated first test data is obtained;

[0110] The data corresponding to the write address is read from the flash memory device to be simulated, and the read completion time of the read data is obtained; the time difference between the write start time and the read completion time is used as the response time; the sum of the data volume of the simulated first test data written and the data volume of the read data is used as the throughput of the erase operation simulation; based on the response time and the read data, the erase operation simulation result of the flash memory device to be simulated under the throughput is generated.

[0111] In the embodiment of the present application, when the simulation type is temperature simulation, relying on the read and write operation simulation, based on the first simulation parameter and the first test data, the flash memory simulation model is simulated to obtain the simulation result of the flash memory device to be simulated, including:

[0112] The first test data and the first simulation parameter are used as the simulated first test data; based on the number of writes, the write speed, the first write temperature and the write delay time, the simulated first test data is written into the write address of the flash memory simulation model, and the write start time of the simulated first test data is obtained;

[0113] Read data corresponding to the write address from the flash memory device to be simulated, and obtain the read completion time and real-time read temperature of the read data; use the time difference between the write start time and the read completion time as the response time; use the sum of the data volume of the simulated first test data written and the data volume of the read data as the throughput of the erase operation simulation; based on the response time, the read temperature and the read data, generate the temperature simulation result of the flash memory device to be simulated under the throughput.

[0114] In an embodiment of the present application, after writing the first test data into the write address of the flash memory simulation model, the method further includes: performing a balance analysis on the first test data; if the balance analysis result of the first test data is unbalanced, performing a random bit flip on the first test data.

[0115] Due to the characteristics of flash, the data stored in Flash will eventually have a 0, 1 balance, that is, the number of 0 and 1 in the flash data in binary observation is basically 1:1; therefore, the flash memory simulation model of the present application can simulate this characteristic to detect whether the number of 0 and 1 in the first test data is balanced. If not, some bits are randomly flipped.

[0116] In the embodiment of the present application, after reading the data corresponding to the write address from the flash memory device to be simulated, the method further includes:

[0117] Extracting a second simulation parameter from the read data; if the temperature difference between the second writing temperature and the reading temperature, the reading temperature or the number of erasures and writes satisfies the configured bit flipping rule, then generating a bit flipping parameter based on the temperature difference, the reading temperature and / or the number of erasures and writes; extracting second test data from the read data, and performing bit flipping on the extracted second test data based on the bit flipping parameter to obtain a data reading result;

[0118] In the embodiment of the present application, the second simulation parameter includes: a second writing temperature or a second erasure number.

[0119] In an embodiment of the present application, the data read from the write address should be the written first test data and the corresponding first simulation parameter; however, since the write address of the flash memory may be a bad block or worn, the data read is not the written data; when the read data cannot extract the second simulation parameter, it proves that the simulation result is a read failure.

[0120] In the embodiment of the present application, based on the write start time, the read parameters and the read data, a simulation result of the flash memory device to be simulated under the throughput is generated, including:

[0121] The data read result is compared with the first test data to obtain a comparison result; based on the write start time, the read parameter and the comparison result, a simulation result of a corresponding simulation type of the flash memory device to be simulated under throughput is generated.

[0122] In an embodiment of the present application, when the simulation type is error correction capability simulation, the flash memory simulation model is simulated based on the first simulation parameter to obtain a simulation result of the flash memory device to be simulated, including:

[0123] Acquire first test data; use the first test data and the first simulation parameters as simulated first test data; based on the number of writes and the write speed, write the simulated first test data to the write address of the flash memory simulation model, and obtain the write start time of the simulated first test data; based on the number of reads and the read speed, read data corresponding to the write address from the flash memory device to be simulated, and obtain read parameters for reading the data; use the sum of the amount of written simulated first test data and the amount of read data as the throughput of the error correction capability simulation; based on the write start time, the read parameters and the read data, generate a simulation result of the error correction capability of the flash memory device to be simulated under the throughput.

[0124] In other embodiments of the present application, the error correction capability may also only perform a write operation or a read operation, and obtain the error correction capability test result by comparing whether the written or read data is consistent with predetermined data.

[0125] In one embodiment of the present application, the flash memory simulation model includes:

[0126] Interface module, used for parsing cmd and data transmission;

[0127] Performance module, when cmd in interface, this module records the time when the command indicator cmd is received, the IO direction of the cmd, and the IO size. When the cmd is completed and a response is returned to the upper layer, the completion time is recorded for subsequent performance calculation and analysis;

[0128] The CFG module is used to configure the current flash device configuration, and when the data is in the direction, the temperature, physical address, PEC and other meta information will be attached to the data. The data in the data out direction will be parsed by the CFG module for additional data, that is, the subsequent data to the modify module can determine whether it needs to be flipped 0,1;

[0129] Modify module, this module is mainly used to implement the 0, 1 flip of data. When data is out, this module will receive the data and additional information passed by the CFG module. The module can use the additional information to determine whether the block corresponding to the data is in a worn state, the temperature difference when the data program has been read, the current temperature, and whether the content of the entire data is balanced between 0 and 1. According to the above conditions, the data to be prepared for data out is flipped between 0 and 1;

[0130] Data module: This module is used to store raw data, receive data after the CFG module adds additional information, and implement erase, program, and read of data through FIO.

[0131] In the embodiment of the present application, the interface module can obtain the first simulation parameter by two methods: by parsing the test script written in advance by the user according to the configuration parameters and the configured simulation requirements; or by obtaining the UART serial port information; for example, if the user wants the nand particle to write data, the write operation simulation instruction is input to the serial port, and the UART parses the received string to the interface to obtain the user instruction. If it is not sent, the particle is always in the idle stage.

[0132] In one embodiment of the present application, the simulation method of the flash memory device includes:

[0133] During initialization, you first need to set the nand configuration that needs to be simulated in the configuration file, such as LUN, PLANE, blk number / size, page number / size. During initialization, the configuration file will be parsed and the rationality of the configuration file and capacity configuration will be determined. Then, for bad block configuration, you can choose to inject bad blocks with fixed physical blks, or you can use random injection to make the total number of bad blocks reach an expected number, such as setting 3% factory bad blocks. The process is as follows Figure 2 shown.

[0134] Working conditions: erase (erase operation), program (write operation), read (read operation):

[0135] 1. Physical blocks need to be erased before they can be used. This model can simulate the erasure of physical blocks. Due to the characteristics of flash, when the ability to maintain 0 and 1 in a block becomes very weak, it will be defined as a bad block. At this time, even after erasing, the program data will not be well maintained. This model can detect the situation of encountering bad blocks and feedback the appropriate error code to the outer module, so that it enters the error handle.

[0136] The model also records the PEC value of each physical blk. The PEC increases every time a physical blk is erased. When the PEC reaches the life cycle of the blk, the bit flip will become more serious. The closer it is to the threshold, the higher the probability of bit flip. The model can set the PEC of each Blk and the blk life cycle threshold to simulate the flash in the state of EOL or excessive wear, such as Figure 3 shown.

[0137] 2. When there is a program command, you need to apply for blk for use. This model can simulate the program situation of the physical block. This model can detect bad blocks and over write situations, and feedback the appropriate error code to the outer module.

[0138] Due to the characteristics of flash, the data stored in flash will eventually reach a balance of 0 and 1, that is, the number of 0 and 1 in the flash data in binary observation is basically 1:1. This model can simulate this characteristic to detect the data of the program and the number of 0 and 1. If the balance is not reached, some bits are randomly flipped, such as Figure 4 shown.

[0139] 3. When there is a read command, the model is also designed with a temperature module, which can simulate the situation under different temperatures\PEC. When the read blk PEC is relatively high, the flash data can be bit-flipped to a certain extent according to the set PEC waterline to simulate the data retention ability of the blk at the end of its life, such as Figure 5 As shown; the probability of bit flipping and PEC example are roughly related as follows Figure 6 As shown, Figure 6 The inflection point in is the preset PEC waterline.

[0140] When the flash is in extreme temperature for a long time, data retention will be affected. Flash will also perform bit flipping according to the duration of the current temperature. The model can also set the ambient temperature and the retention time of the current temperature to perform reasonable bit flipping and simulate this situation.

[0141] The flash memory simulation model provided in the embodiment of the present application can simulate the situation where a large number of IO services cause the flash temperature to rise or the temperature to drop naturally when idle. It can also simulate the particle usage in extreme environments such as temperature box test simulation. When the flash encounters an IO request, the temperature module will record the temperature of the current IO physical address request. When the physical address is accessed next time, it will reasonably perform bit inversion based on the current and previously recorded temperature difference, such as Figure 7 shown.

[0142] Corresponding to the above method, the embodiment of the present application also provides a simulation device for a flash memory device, such as Figure 8 As shown, the simulation device of the flash memory device includes:

[0143] An acquisition unit 810 is used to acquire configuration parameters and first test data of a flash memory device to be simulated;

[0144] An adjusting unit 820, configured to adjust the parameters of the pre-built initial flash memory simulation model according to the configuration parameters to obtain the flash memory simulation model;

[0145] A determining unit 830, configured to determine a first simulation parameter according to the configuration parameter and the configured simulation requirement;

[0146] The simulation unit 840 is used to simulate the flash memory simulation model based on the first simulation parameter and the first test data to obtain a simulation result of the flash memory device to be simulated.

[0147] The functions of each functional unit of the simulation device of the flash memory device provided in the above-mentioned embodiment of the present application can be realized through the above-mentioned method steps. Therefore, the specific working process and beneficial effects of each unit in the simulation device of the flash memory device provided in the embodiment of the present application are not repeated here.

[0148] The present application also provides an electronic device, such as Fig. 9 As shown, it includes a processor 910 , a communication interface 920 , a memory 930 and a communication bus 940 , wherein the processor 910 , the communication interface 920 , and the memory 930 communicate with each other via the communication bus 940 .

[0149] Memory 930, used for storing computer programs;

[0150] The processor 910 is used to execute the program stored in the memory 930 to implement the following steps:

[0151] Acquire configuration parameters and first test data of the flash memory device to be simulated;

[0152] According to the configuration parameters, the parameters of the pre-built initial flash memory simulation model are adjusted to obtain the flash memory simulation model;

[0153] Determining first simulation parameters according to the configuration parameters and the configured simulation requirements;

[0154] Based on the first simulation parameter and the first test data, the flash memory simulation model is simulated to obtain a simulation result of the flash memory device to be simulated.

[0155] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0156] The communication interface is used for communication between the above electronic device and other devices.

[0157] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0158] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0159] The implementation methods and beneficial effects of the components of the electronic device in the above embodiments to solve the problems can be seen in Figure 1 The various steps in the illustrated embodiment are implemented, therefore, the specific working process and beneficial effects of the electronic device provided by the embodiment of the present application are not repeated here.

[0160] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes the simulation method of the flash memory device in any of the above embodiments.

[0161] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the simulation method of a flash memory device in any one of the above embodiments.

[0162] Those skilled in the art will appreciate that the embodiments in the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt a complete hardware embodiment, a complete software embodiment, or a form of an embodiment combining software and hardware. Moreover, the present application may adopt a form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0164] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0166] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0167] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the present application without departing from the spirit and scope of the embodiments in the present application. Thus, if these modifications and variations of the embodiments in the present application fall within the scope of the claims and their equivalents in the embodiments of the present application, the embodiments of the present application are also intended to include these modifications and variations.

Claims

1. A flash memory device simulation method, characterized in that: The method comprises: Obtain configuration parameters of the flash memory device to be simulated; According to the configuration parameters, the parameters of the pre-built initial flash memory simulation model are adjusted to obtain the flash memory simulation model; Determining first simulation parameters according to the configuration parameters and the configured simulation requirements; Based on the first simulation parameters, the flash memory simulation model is simulated to obtain a simulation result of the flash memory device to be simulated.

2. The method according to claim 1, characterized in that The simulation requirements include: a simulation type and custom parameters corresponding to the simulation type; The simulation types include: read operation simulation, write operation simulation, erase operation simulation, temperature simulation and error correction capability simulation; The first simulation parameters include: physical address, number of times and speed.

3. The method according to claim 2, characterized in that When the simulation type is a write operation simulation, the physical address, number of times and speed are respectively a write address, a write number and a write speed of the first test data; The first simulation parameter also includes: write delay time; Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes: Acquire first test data; Based on the write count, write speed and write delay time, write the first test data to the write address of the flash memory simulation model, obtain a write completion result, and obtain a write start time and a write completion time of the first test data; Taking the data volume of the first test data as the throughput of the write operation simulation; Based on the write start time, the write completion time and the write completion result, a write operation simulation result of the flash memory device to be simulated under the throughput is determined.

4. The method according to claim 3, characterized in that When the simulation type is a read operation simulation or an erase operation simulation, the flash memory simulation model is simulated based on the first simulation parameter to obtain a simulation result of the flash memory device to be simulated, including: Based on the number of times and the speed, the operation corresponding to the simulation type is performed on the data corresponding to the physical address in the simulated flash memory device to obtain a simulation operation result, and the operation parameters when performing the operation corresponding to the simulation type are obtained; wherein the operation parameters include a time parameter for performing the operation; Taking the amount of data corresponding to the physical address as the throughput; Based on the time parameter and the simulation operation result, a read operation simulation result of the flash memory device to be simulated at the throughput is generated.

5. The method according to claim 4, characterized in that When the simulation type is error correction capability simulation, the physical address is a write address of the first test data; The times and speeds include: write times, read times, write speed and read speed respectively; Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes: Acquire first test data; Using the first test data and the first simulation parameters as simulated first test data; Based on the write count and the write speed, write the simulated first test data into the write address of the flash memory simulation model, and obtain the write start time of the simulated first test data; Based on the number of reads and the read speed, data corresponding to the write address is read from the flash memory device to be simulated, and read parameters for reading the data are obtained; the read parameters include: read completion time and read temperature; The sum of the amount of the written simulated first test data and the amount of the read data is used as the throughput of the error correction capability simulation; Based on the write start time, the read parameters and the read data, a simulation result of the error correction capability of the flash memory device to be simulated under the throughput is generated.

6. The method according to claim 5, characterized in that After writing the simulated first test data into the write address of the flash memory simulation model, the method further includes: Performing a balance analysis on the first test data; if a balance analysis result of the first test data is unbalanced, performing a random bit flip on the first test data; After reading data corresponding to the write address from the flash memory device to be simulated, the method further includes: Extracting a second simulation parameter from the read data; wherein the second simulation parameter includes: a second writing temperature or a second erasure number; If the temperature difference between the second writing temperature and the reading temperature, the reading temperature or the number of erasures meets the configured bit flipping rule, then based on the temperature difference, the reading temperature and / or the number of erasures, a bit flipping parameter is generated; Extracting second test data from the read data, and performing bit flipping on the extracted second test data based on the bit flipping parameter to obtain a data reading result; Based on the write start time, the read parameter and the read data, generating a simulation result of the error correction capability of the flash memory device to be simulated under the throughput, including: Compare the data reading result with the first test data to obtain a comparison result; Based on the write start time, the read parameter and the comparison result, a simulation result of a corresponding simulation type of the flash memory device to be simulated under the throughput is generated.

7. The method according to claim 6, characterized in that When the simulation type is temperature simulation, the first simulation parameter further includes: a first write temperature; the operation parameter further includes: a read temperature or an erase temperature; the read parameter further includes: a read temperature; Based on the first simulation parameter, simulating the flash memory simulation model to obtain a simulation result of the flash memory device to be simulated includes: Based on the first simulation parameters, read operation simulation, write operation simulation, erase operation simulation and / or error correction capability simulation are performed on the flash memory simulation model to obtain temperature simulation results of the flash memory device to be simulated under the first simulation parameters.

8. A flash memory device simulation device, characterized in that: The device comprises: An acquisition unit, used for acquiring configuration parameters and first test data of a flash memory device to be simulated; An adjusting unit, configured to adjust the parameters of the pre-built initial flash memory simulation model according to the configuration parameters to obtain the flash memory simulation model; A determination unit, configured to determine a first simulation parameter according to the configuration parameter and a configured simulation requirement; A simulation unit is used to simulate the flash memory simulation model based on the first simulation parameters and the first test data to obtain a simulation result of the flash memory device to be simulated.

9. An electronic device, characterized in that: The electronic device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-7 when executing a program stored in a memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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