Oscillation detection and optimization method and system for strongly connected components of combinational logic circuit

Abstract

The invention discloses an oscillation detection and optimization method and system for strongly connected components of a combinational logic circuit, and the method comprises the steps: building an oscillation detection module according to an external input signal in the strongly connected components and a signal value of the signal, and building an equivalent transformation module in combination with a multiplexer; and inserting the equivalent transformation module into the nested logic ring containing the negative feedback ring to share the output end of the logic gate, and outputting the transformed netlist. According to the invention, the oscillation can be successfully detected and interrupted under the condition that the circuit oscillates, the logic function of the original circuit is not influenced under the condition that the circuit does not oscillate, and the simulation efficiency and stability of the combinational circuit are improved.

Description

Technical Field

[0001] The invention relates to a digital combinational logic circuit simulation optimization technology, in particular to an oscillation detection and optimization method and system for strongly connected components of a combinational logic circuit. Background Art

[0002] In modern digital logic circuit design, with the continuous expansion of integrated circuit scale and the improvement of integration, the design complexity of digital circuits has increased significantly, and the combinational logic loop problem in combinational logic circuits has become particularly important. A combinational logic loop refers to the output signal of a combinational logic circuit being fed back to its input end through a certain path, thus forming a closed-loop structure. This structure is undesirable in digital circuit design, because the signal in the combinational logic loop will continuously circulate between the input and output, which may cause the circuit to be unable to reach a stable state, thereby causing high-frequency oscillations. This oscillation not only affects the normal operation of the circuit, but may also cause the simulator to enter a deadlock state, that is, the simulator cannot continue to simulate, the signal cannot converge to a certain state, and the simulation of the entire circuit will be invalidated.

[0003] In actual integrated circuit design, combinational logic loops may be nested to form strongly connected components (SCCs). Especially in modern large-scale circuit design, IC designers may inadvertently introduce such strongly connected components, resulting in unexpected oscillations. The traditional oscillation detection method uses a simulator to check the changes in signal states in simple logic circuits to determine whether the circuit is oscillating. However, in complex large-scale circuits, this method is extremely time-consuming and computationally expensive, and is not practical. In addition, in actual digital logic circuit simulation, the possible oscillation loop is interrupted by simply inserting a register in the logic loop of the SCC. Although this method can successfully prevent the circuit from oscillating, it may also interrupt the combinational logic loop that would not have oscillated originally, resulting in the circuit function after the transformation being not equivalent to the original one. It cannot effectively help IC designers to promptly discover potential problems that may exist in the circuit. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide an oscillation detection and optimization method and system for strongly connected components of a combinational logic circuit, so as to solve the problem in the prior art that it is difficult to accurately determine whether a circuit is oscillating while reducing computing resources and time overhead, and to interrupt the oscillation without affecting the original function of the circuit.

[0005] Technical solution: The oscillation detection and optimization method of the strongly connected components of the combinational logic circuit described in the present invention comprises the following steps: (1) Obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly connected components in the circuit to be optimized; (2) For each strongly connected component, determine the external input signal and its signal value that causes the circuit to be optimized to oscillate; (3) Building an oscillation detection module according to the external input signal and its signal value determined in step (2), so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; (4) constructing an equivalent transformation module, wherein the equivalent transformation module includes a two-to-one multiplexer, and a control input end of the two-to-one multiplexer is used to connect the output of the oscillation detection module; (5) Inserting the equivalent transformation module into the logic gate output node shared by two loops in the circuit to be optimized to obtain an equivalent transformation circuit, wherein the two loops contain at least one negative feedback logic loop; when the circuit operates normally, connecting to the first input end of the two-to-one multiplexer, and when the circuit to be optimized oscillates, selecting the second input end of the two-to-one multiplexer to interrupt the oscillation.

[0006] Furthermore, step (2) specifically includes: For each strongly connected component, the signal value of the external input signal that causes the circuit to be optimized to oscillate is determined by searching for a partial assignment induced boundary of the external input signal. The method for searching for a partial assignment induced boundary of the external input signal includes: The control value of each type of logic gate is set, the first external input signal is input from the first logic gate and transmitted backward, and the signal value is different from the control value of the second logic gate when reaching the second logic gate, and the input of the second logic gate is all internal input of the circuit, then the second logic gate is partially assigned an induced boundary for the first external input signal; wherein the signal value of the first external input signal is assigned as the control value of the first logic gate; Merge the external input signals and their signal values ​​that contain the same partial assignment induced boundaries to form a non-empty boundary set; The external input signals and their signal values ​​that do not have any partial assignment induced boundaries will constitute an empty set of boundaries.

[0007] Furthermore, step (3) specifically includes: A first oscillation detection branch is constructed according to the non-empty boundary set and the boundary empty set, so that when the external input signal and its signal value in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; A second oscillation detection branch is built according to the negative feedback logic loop in the circuit to be optimized, so that the input of the logic gate in the negative feedback logic loop meets the oscillation condition, and even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; The negative feedback logic loop is a loop containing an odd number of logic gates with negation characteristics in the strongly connected component; The outputs of the first oscillation detection branch and the second oscillation detection branch are connected by an AND gate to obtain an oscillation detection module, so that when two oscillation conditions are met at the same time, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

[0008] Furthermore, the setting of the control value of each type of logic gate includes: setting the control value of the AND gate and the NAND gate to logic 0, and setting the control value of the OR gate and the NOR gate to logic 1.

[0009] Furthermore, in step (4), a D flip-flop is inserted into the second input terminal of the two-to-one multiplexer, and a clock input terminal of the D flip-flop is grounded and maintained at a low level.

[0010] The oscillation detection and optimization system of strongly connected components of a combinational logic circuit of the present invention comprises: A strongly connected component detection unit, used to obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly connected components in the circuit to be optimized; An external input signal determination unit, used for determining, for each strongly connected component, an external input signal and its signal value that causes the circuit to be optimized to oscillate; An oscillation detection module building unit, used to build an oscillation detection module according to the external input signal and its signal value determined in the external input signal determination unit, so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; An equivalent transformation module building unit, used for building an equivalent transformation module, wherein the equivalent transformation module comprises a two-to-one multiplexer, wherein a control input end of the two-to-one multiplexer is used for connecting an output of the oscillation detection module; The circuit oscillation optimization unit is used to insert the equivalent transformation module into the logic gate output node shared by two loops in the circuit to be optimized to obtain an equivalent transformation circuit, wherein the two loops contain at least one negative feedback logic loop; when the circuit operates normally, the first input end of the two-to-one multiplexer is connected, and when the circuit to be optimized oscillates, the second input end of the two-to-one multiplexer is selected to interrupt the oscillation.

[0011] Further, the external input signal determination unit includes: For each strongly connected component, the signal value of the external input signal that causes the circuit to be optimized to oscillate is determined by searching for a partial assignment induced boundary of the external input signal; the method for searching for a partial assignment induced boundary of the external input signal includes: The control value of each type of logic gate is set, the first external input signal is input from the first logic gate and transmitted backward, and the signal value is different from the control value of the second logic gate when reaching the second logic gate, and the input of the second logic gate is all internal input of the circuit, then the second logic gate is partially assigned an induced boundary for the first external input signal; wherein the signal value of the first external input signal is assigned as the control value of the first logic gate; Merge the external input signals and their signal values ​​that contain the same partial assignment induced boundaries to form a non-empty boundary set; The external input signals and their signal values ​​that do not have any partial assignment induced boundaries will constitute an empty set of boundaries.

[0012] Furthermore, the vibration detection module building unit includes: A first oscillation detection branch is constructed according to the non-empty boundary set and the boundary empty set, so that when the external input signal and its signal value in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; A second oscillation detection branch is built according to the negative feedback logic loop in the circuit to be optimized, so that the input of the logic gate in the negative feedback logic loop meets the oscillation condition, and even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; The negative feedback logic loop is a loop containing an odd number of logic gates with negation characteristics in the strongly connected component; The outputs of the first oscillation detection branch and the second oscillation detection branch are connected by an AND gate to obtain an oscillation detection module, so that when two oscillation conditions are met at the same time, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

[0013] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the oscillation detection and optimization method of the strongly connected components of the combinational logic circuit is implemented.

[0014] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the oscillation detection and optimization method of the strongly connected components of the combinational logic circuit is implemented.

[0015] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) After performing equivalent transformation on the combinational logic circuit, the present invention can not only effectively prevent the occurrence of oscillations that affect circuit simulation, but also help IC designers discover design problems and find the locations of circuit structures that do not meet expectations, thereby improving the efficiency and reliability of circuit simulation; (2) The oscillation detection module proposed in the present invention can improve the accuracy of oscillation identification compared to the feedback loop analysis and isolation method based on graph theory, and can also provide a signal OscFlag for detecting oscillations, which is logic 1 when oscillation occurs and logic 0 when oscillation does not occur; (3) The equivalent transformation module proposed in the present invention can perform equivalent transformation on the circuit without introducing sequential logic and changing the original function of the circuit, and the transformed circuit can successfully detect and interrupt oscillations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the oscillation detection and optimization method of the present invention.

[0017] Figure 2 Schematic diagram of the circuit structure to be optimized in an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of the circuit structure of the oscillation detection module in an embodiment of the present invention.

[0019] Figure 4 Schematic diagram of the circuit structure of the equivalent transformation module in an embodiment of the present invention.

[0020] Figure 5 Schematic diagram of the circuit structure after equivalent transformation in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0022] like Figure 1 As shown, the oscillation detection and optimization method of the strongly connected components of the combinational logic circuit includes the following steps.

[0023] Step 1: Read the Verilog source code netlist information through the VPI interface.

[0024] The Verilog simulator interacts with the C language program through the VPI interface, reads the input Verilog source code file, and extracts the topology structure of the combinational logic circuit, circuit signal connection and other circuit information. The circuit information includes the type of logic gate (such as AND gate, OR gate, NOT gate, etc.), the name of the input and output port and its signal connection relationship, etc. The schematic diagram of the circuit structure to be optimized generated according to the circuit information in this embodiment is shown in FIG. Figure 2As shown, in practice, combinatorial logic rings may be nested to form strongly connected component circuits (in the mathematical theory of directed graphs, if every vertex of a graph can be reached from any other point in the graph, the graph is called strongly connected. The part that can achieve strong connectivity in any directed graph is called a strongly connected component). Simple combinatorial logic rings also meet the definition of strongly connected component circuits. The circuit to be optimized in this embodiment is a strongly connected component (SCC). In practice, the strongly connected components in the circuit can be identified by abstracting the circuit into a directed node graph and then using graph theory algorithms such as depth-first search (DFS). The strongly connected component includes AND gates: I1, I3, I4, I7, I8, I9, I10, I11, I12; NOT gates: I2, I5; NAND gates: I6, I13, I14. Including external input signals: w1, w2, w3, w4, w5, w6, w7, w8. And some internal signals marked: w5_6, w8_9, w9_12, w13_14.

[0025] Step 2: Find the external input part of the strongly connected components, assign the induced boundaries and classify and merge them.

[0026] The method for finding the partial assignment (PA) induced boundary, hereinafter referred to as the PA induced boundary, is as follows: first, assign a value to the external input signal of the SCC, and assign a value to the input according to the control value of the first logic gate corresponding to the external input signal. This forces the output of the first logic gate to be a given value and continues to transmit backward until the signal reaches a certain logic gate and is not the control value of the logic gate, and all the input signals of the logic gate are internal signals of the SCC. In this way, the boundary of the external input signal is called non-empty and the logic gate is the PA induced boundary of the input signal. In this way, the effect of partially cutting the SCC into a non-cyclic combinational circuit can be achieved.

[0027] If an external input signal of SCC does not meet the condition that the boundary is non-empty, that is, after the control value is assigned to the first logic gate input corresponding to the external input signal, when the signal is transmitted backward to a certain logic gate, the remaining input signals of the logic gate exist in the external input signal of SCC, or after the control value is assigned to the input signal, the signal is transmitted inside the SCC, resulting in the existence of the control value in the external input signal of each negative feedback loop contained in the SCC without oscillation, thereby making it impossible for the entire SCC to oscillate, then the PA induced boundary of the input signal is called empty.

[0028] The control value of the logic gate can be determined according to the actual situation. In this embodiment, the control value of the AND gate and the NAND gate is logic 0, and the NOT gate only realizes the function of single input inversion. The control value of other common logic gates such as the OR gate and the NOR gate is logic 1. Figure 2For the circuit structure shown, the results of finding the PA induced boundaries of external input signals w1-w8 are as follows: since input w1 corresponds to an AND gate I1, the w1 part is assigned the I1 control value logic 0, and when the signal is transmitted to I3, it is logic 1, which is not the control value of I3, so the PA induced boundary corresponding to w1 is I3; similarly, the induced boundaries of w2 assigned logic 0 are I6 and I14; the boundary of w3 assigned logic 0 is empty; w4 is assigned logic 0 boundary I6; w5 is assigned logic 0 corresponding to boundary I14; w6 is assigned logic 0 corresponding to boundary I3 and I9; w7 is assigned logic 0 corresponding to boundary I3 and I9; w8 is assigned logic 0 corresponding to boundary empty.

[0029] After observation, we know that the signals with empty reachable logical boundaries are w3 and w8; then we try to merge the non-empty boundary cases with the same reachable logical boundaries. The boundaries corresponding to signals w6 and w7 are consistent, so we can merge them. Finally, the inputs with empty boundaries are R1={w3=0} and R2={w8=0}; the merged non-empty boundary input is R3={w6=0,w7=0}.

[0030] Step 3: Build the vibration monitoring module.

[0031] The oscillation detection module consists of two detection branches, namely the first oscillation detection branch and the second oscillation detection branch. In order to ensure that when both oscillation detection branches are logical 1, the circuit to be optimized oscillates, that is, the OscFlag value is logical 1. The two branches are combined with logic to obtain the oscillation detection module. Figure 3 As shown, when the output signal OscFlag of the oscillation detection module is logic 1, it means that the strongly connected component oscillates, and when OscFlag is logic 0, it means that the strongly connected component does not oscillate.

[0032] The structure of the first oscillation detection branch depends on the PA-induced boundary of the external input signal of the strongly connected component. For the inputs R1={w3=0} and R2={w8=0} with empty boundaries, they must be non-controlled values ​​to achieve the oscillation condition. For the inputs {w6=0,w7=0} with non-empty boundaries after merging, any one of them can be a non-controlled value. In order to meet the condition that the circuit can only reach the oscillation condition when the inputs w3 and w8 with empty boundaries are both logical 1, two serial OR gates U4 and U5 are set. Since the control value of the OR gate is logical 1, an inverter U6 and U7 are set after the input signals w3 and w8 respectively, so that when w3 and w8 are logical 1, they cannot be used as the control values ​​of the logic gates U4 and U5 to affect the output of the first oscillation detection branch. In order to satisfy the requirement that the external inputs w6 and w7 whose boundaries are non-empty after merging can make the output of the first oscillation detection branch be logic 1 only when they are both logic 0, an AND gate U3 is set in series with the previous OR gates U4 and U5, so that the input signals w6 and w7 are used as the inputs of U3. Since the control value of the AND gate is 0, inverters U1 and U2 are set after the signals w6 and w7 respectively. According to the above conditional constraints, the first oscillation detection branch can be obtained.

[0033] There are two types of combinational logic loops in strongly connected components: positive feedback loops and negative feedback loops. A negative feedback loop refers to a combinational logic loop that contains an odd number of logic gates with negation characteristics, such as NOT gates and NAND gates. A positive feedback loop refers to a logic loop that contains an even number of or no logic gates with negation characteristics. If the negative feedback loop in the circuit is not processed during circuit simulation, oscillation may occur, causing the entire simulator to fall into a deadlock state, greatly increasing the simulation running time until it is automatically interrupted.

[0034] The structure of the second oscillation detection branch depends on the external input signal of the negative feedback loop contained in the strongly connected component. If the external input signals of the negative feedback loop are all non-control values, it is determined that the logic loop has reached the oscillation condition. Figure 2It can be known that the condition can be met as long as the out-loop signals w8, w5_6, w9_12, w6 of the negative feedback loop: {I8 - I9 - I10 - I6 - I8} are all non-controlled values, or the out-loop signals w7, w13_14, w8_9, w3 of another negative feedback loop: {I9 - I11 - I14 - I12 - I9} are all non-controlled values. In order to meet the above conditions, two branches are set in parallel and then connected to an OR gate U15. The first parallel branch is connected in series with three AND gates U9, U10 and U11, so that the signals w8, w5_6, w9_12 and w6 are used as the inputs of the AND gates. The second parallel branch is also connected in series with three AND gates U12, U13 and U14, so that the signals w7, w13_14, w8_9, w3 are used as the inputs of the AND gates. According to the above conditions, the second oscillation detection branch is obtained.

[0035] Step 4: Build the equivalent transformation module.

[0036] In order to ensure that when the strongly connected components of the combinational logic are equivalently transformed, the circuit can successfully detect the oscillation in time when it occurs, and does not affect the normal operation of the logic function of the original circuit when the circuit does not oscillate, it is necessary to design an equivalent transformation module.

[0037] Equivalent transformation module such as Figure 4 As shown, based on the oscillation detection module obtained in step S3, its output signal OscFlag is used as the input of the control terminal sel0 of the two-to-one multiplexer. The first data input terminal a of the two-to-one multiplexer is directly connected to the input terminal in without processing. When no oscillation occurs or the circuit is in the initial state, this path is selected to ensure that the circuit operates with the original logic function. A D flip-flop that does not introduce sequential logic will be inserted into the second data input terminal b of the two-to-one multiplexer. The clock input terminal of the flip-flop is grounded GND and always maintains a low level. When the circuit oscillates, this path will be selected to interrupt the oscillation through the flip-flop. Finally, an equivalent transformation module is obtained, whose input is signal in and output is signal out.

[0038] Step 5: insert the equivalent transformation module into the circuit for equivalent transformation.

[0039] The strongly connected component is composed of several nested combinational logic loops, among which the negative feedback loop may cause oscillation, because the positive feedback loop contains an even number of logic gates with negation characteristics, which does not have the conditions to make the signal infinitely flip and cause oscillation. In order to minimize the number of inserted equivalent transformation modules, the equivalent transformation module is inserted into the logic gate output node shared by the two logic loops, and the two combinational logic loops must contain at least one negative feedback loop, so as to ensure that the oscillation is completely interrupted when it occurs. Based on this idea, in Figure 2In the circuit shown in the figure, the output nodes of logic gates I9 and I6 are both inserted with equivalent transformation modules, and the circuit structure after equivalent transformation is finally completed is as follows: Figure 5 shown.

[0040] When the equivalently modified circuit receives a new set of external excitation signals, the oscillation detection module will immediately react to determine whether the strongly connected component oscillates under the output excitation signal. If oscillation occurs, the OscFlag signal is logic 1, and the multiplexer selects a path to insert the D flip-flop, immediately interrupting the combinational logic loop to prevent the oscillation from occurring. IC designers can find faults in the circuit based on the OscFlag signal. If oscillation does not occur, the OscFlag signal is logic 0, and the multiplexer selects another path that is not processed, which will not affect the logic function of the original circuit.

[0041] In order to better verify and illustrate the technical effects of the method of the present invention, this embodiment selects to test the method of the present invention by comparing the feedback loop analysis and isolation method based on graph theory, and compares the test results by means of scientific demonstration to verify the real effect of the method of the present invention. Among them, the steps of the feedback loop analysis and isolation method based on graph theory are as follows:

[0042] First, the combinational logic circuit is abstracted into a directed node graph. In this process, each logic gate in the circuit is regarded as a node in the graph, and the connection relationship between the logic gates is represented as a directed edge. Specifically, if the output of a logic gate is connected to the input of another logic gate, a directed edge is drawn between the corresponding nodes to indicate the flow direction of the signal. In this way, the entire combinational logic circuit is converted into a directed graph, which provides a basis for subsequent loop detection.

[0043] Then use graph theory algorithms such as depth-first search (DFS) to traverse the directed graph to detect all loops in it. The DFS algorithm starts from a starting node and searches deeply along the path until it can no longer go forward, then it backtracks. During the search, if a node that has been visited is encountered and the node is not the starting node of the current path, it means that a loop has been found. In this way, the entire directed graph can be systematically traversed to find all possible loops. These loops are feedback loops in combinational logic circuits and are potential causes of oscillation.

[0044] After all loops are detected, they need to be analyzed to determine which loops are the key factors causing oscillation. Generally, the length of the loop, the type of logic gates contained, and the signal propagation characteristics will affect its impact on the stability of the circuit. By analyzing the structure and characteristics of the loop, those loops that are most likely to cause oscillation can be processed first. For example, determine whether the loop is a positive feedback loop or a negative feedback loop, and insert a register or trigger in the negative feedback loop to interrupt the loop, while the positive feedback loop is not processed.

[0045] Finally, the loop is broken by inserting a register in the combinational logic loop. The insertion position of the register needs to be carefully selected to ensure that the loop can be effectively broken while minimizing the impact on the circuit function. Generally speaking, the register should be inserted on the critical path of the loop, that is, the path where the signal circulates in the loop. In this way, the register can temporarily store the signal, breaking the continuous feedback of the signal, thereby preventing the occurrence of oscillation.

[0046] Based on the digital circuit simulation platform Verisim, the circuits transformed by the above two methods were run, and three combinational logic circuits of different scales and complexities were tested: T_CCA_1, T_ACA_1 and T_ACA_2, which respectively contain strongly connected components with multiple double-ring nesting, three-ring nesting and multiple three-ring nesting structures. In order to verify whether the transformed combinational circuit is equivalent to the original circuit logic function without oscillation, all possible input vectors are applied to the input end of the transformed circuit, and the internal node signals under each input vector are monitored and compared with the internal node signals of the original circuit under the same input vector. The number of input vectors with completely consistent internal signals when not oscillating is counted. In order to verify whether the transformed circuit can successfully detect and interrupt oscillation, the number of oscillations successfully detected and interrupted by the transformed circuit is counted.

[0047] Table 1: Results of the operation of the method of the present invention

[0048]

[0049] Table 2: Results of feedback loop analysis and isolation method based on graph theory

[0050]

[0051] Referring to Table 1 and Table 2, the number of input vectors whose internal signals are completely consistent in the circuit transformed by the method of the present invention when it is not oscillating is consistent with the total number of non-oscillating input vectors, indicating that the internal node logic value is completely consistent with the internal node logic value of the original circuit in the case of non-oscillating input vectors, proving that the circuit transformed by the method of the present invention can completely match the internal node signal of the original circuit when no oscillation occurs, without affecting the function of the original circuit, and achieves the effect of equivalent transformation, while the internal node signal of the circuit after transformation based on graph theory and the original circuit only match 83% on average. Compared with the method based on graph theory, the signal matching degree is improved by an average of 16%, and the number of detections and interruptions of oscillations is improved by an average of 12%. In summary, the present invention effectively achieves equivalent transformation of the original circuit while detecting and interrupting circuit oscillations, improving the efficiency and stability of combinational circuit simulation.

[0052] The oscillation detection and optimization system of strongly connected components of a combinational logic circuit of the present invention comprises: A strongly connected component detection unit, used to obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly connected components in the circuit to be optimized; An external input signal determination unit, used for determining, for each strongly connected component, an external input signal and its signal value that causes the circuit to be optimized to oscillate; An oscillation detection module building unit, used to build an oscillation detection module according to the external input signal and its signal value determined in the external input signal determination unit, so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; An equivalent transformation module building unit, used for building an equivalent transformation module, wherein the equivalent transformation module comprises a two-to-one multiplexer, wherein a control input end of the two-to-one multiplexer is used for connecting an output of the oscillation detection module; The circuit oscillation optimization unit is used to insert the equivalent transformation module into the logic gate output node shared by two loops in the circuit to be optimized to obtain an equivalent transformation circuit, wherein the two loops contain at least one negative feedback logic loop; when the circuit operates normally, the first input end of the two-to-one multiplexer is connected, and when the circuit to be optimized oscillates, the second input end of the two-to-one multiplexer is selected to interrupt the oscillation.

[0053] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the oscillation detection and optimization method of the strongly connected components of the combinational logic circuit is implemented.

[0054] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the oscillation detection and optimization method of the strongly connected components of the combinational logic circuit is implemented.

[0055] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0056] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A method for oscillation detection and optimization of strongly connected components of a combinational logic circuit, characterized in that: The steps include: (1) Obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly connected components in the circuit to be optimized; (2) For each strongly connected component, determine the external input signal and its signal value that causes the circuit to be optimized to oscillate; (3) Building an oscillation detection module according to the external input signal and its signal value determined in step (2), so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; (4) constructing an equivalent transformation module, wherein the equivalent transformation module includes a two-to-one multiplexer, and a control input end of the two-to-one multiplexer is used to connect the output of the oscillation detection module; (5) Inserting the equivalent transformation module into the logic gate output node shared by two loops in the circuit to be optimized to obtain an equivalent transformation circuit, wherein the two loops contain at least one negative feedback logic loop; when the circuit operates normally, connecting to the first input end of the two-to-one multiplexer, and when the circuit to be optimized oscillates, selecting the second input end of the two-to-one multiplexer to interrupt the oscillation.

2. The oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to claim 1, characterized in that: Step (2) specifically includes: for each strongly connected component, determining the signal value of the external input signal that causes the circuit to be optimized to oscillate by searching for the partial assignment induced boundary of the external input signal, and the method for searching for the partial assignment induced boundary of the external input signal includes: The control value of each type of logic gate is set, the first external input signal is input from the first logic gate and transmitted backward, and the signal value is different from the control value of the second logic gate when reaching the second logic gate, and the input of the second logic gate is all internal input of the circuit, then the second logic gate is partially assigned an induced boundary for the first external input signal; wherein the signal value of the first external input signal is assigned as the control value of the first logic gate; The external input signals and their signal values ​​that contain the same partial assignment induced boundaries are merged to form a non-empty boundary set; the external input signals and their signal values ​​that do not have partial assignment induced boundaries are combined to form an empty boundary set.

3. The oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to claim 2, characterized in that: Step (3) specifically includes: A first oscillation detection branch is constructed according to the non-empty boundary set and the boundary empty set, so that when the external input signal and its signal value in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; A second oscillation detection branch is built according to the negative feedback logic loop in the circuit to be optimized, so that the input of the logic gate in the negative feedback logic loop meets the oscillation condition, and even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; The negative feedback logic loop is a loop containing an odd number of logic gates with negation characteristics in the strongly connected component; The outputs of the first oscillation detection branch and the second oscillation detection branch are connected by an AND gate to obtain an oscillation detection module, so that when two oscillation conditions are met at the same time, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

4. The oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to claim 2, characterized in that: The setting of the control value of each type of logic gate includes: setting the control value of the AND gate and the NAND gate to logic 0, and setting the control value of the OR gate and the NOR gate to logic 1.

5. The oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to claim 1, characterized in that: In step (4), the second input terminal of the two-to-one multiplexer is inserted into a D flip-flop, and the clock input terminal of the D flip-flop is grounded and maintained at a low level.

6. A system for detecting and optimizing oscillations of strongly connected components of a combinational logic circuit, characterized in that: include: A strongly connected component detection unit, used to obtain the netlist information of the circuit to be optimized and detect the circuit structure information of the strongly connected components in the circuit to be optimized; An external input signal determination unit, used for determining, for each strongly connected component, an external input signal and its signal value that causes the circuit to be optimized to oscillate; An oscillation detection module building unit, used to build an oscillation detection module according to the external input signal and its signal value determined in the external input signal determination unit, so that when the circuit to be optimized oscillates, the output value of the oscillation detection module is logic 1; An equivalent transformation module building unit, used for building an equivalent transformation module, wherein the equivalent transformation module comprises a two-to-one multiplexer, wherein a control input end of the two-to-one multiplexer is used for connecting an output of the oscillation detection module; The circuit oscillation optimization unit is used to insert the equivalent transformation module into the logic gate output node shared by two loops in the circuit to be optimized to obtain an equivalent transformation circuit, wherein the two loops contain at least one negative feedback logic loop; when the circuit operates normally, the first input end of the two-to-one multiplexer is connected, and when the circuit to be optimized oscillates, the second input end of the two-to-one multiplexer is selected to interrupt the oscillation.

7. The oscillation detection and optimization system for strongly connected components of a combinational logic circuit according to claim 6, characterized in that: The external input signal determination unit comprises: For each strongly connected component, the signal value of the external input signal that causes the circuit to be optimized to oscillate is determined by searching for a partial assignment induced boundary of the external input signal; the method for searching for a partial assignment induced boundary of the external input signal includes: The control value of each type of logic gate is set, the first external input signal is input from the first logic gate and transmitted backward, and the signal value is different from the control value of the second logic gate when reaching the second logic gate, and the input of the second logic gate is all internal input of the circuit, then the second logic gate is partially assigned an induced boundary for the first external input signal; wherein the signal value of the first external input signal is assigned as the control value of the first logic gate; Merge the external input signals and their signal values ​​that contain the same partial assignment induced boundaries to form a non-empty boundary set; The external input signals and their signal values ​​that do not have any partial assignment induced boundaries will constitute an empty set of boundaries.

8. The oscillation detection and optimization system for strongly connected components of a combinational logic circuit according to claim 7, characterized in that: The vibration detection module building unit includes: A first oscillation detection branch is constructed according to the non-empty boundary set and the boundary empty set, so that when the external input signal and its signal value in the non-empty boundary set and the boundary empty set are satisfied, even if the circuit to be optimized reaches the first oscillation condition, the output of the first oscillation detection branch is logic 1; A second oscillation detection branch is built according to the negative feedback logic loop in the circuit to be optimized, so that the input of the logic gate in the negative feedback logic loop meets the oscillation condition, and even if the circuit to be optimized reaches the second oscillation condition, the output of the second oscillation detection branch is logic 1; The negative feedback logic loop is a loop containing an odd number of logic gates with negation characteristics in the strongly connected component; The outputs of the first oscillation detection branch and the second oscillation detection branch are connected by an AND gate to obtain an oscillation detection module, so that when two oscillation conditions are met at the same time, the circuit to be optimized oscillates, and the output value of the oscillation detection module is logic 1.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the oscillation detection and optimization method of strongly connected components of a combinational logic circuit according to any one of claims 1 to 5 is implemented.

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