Method for extracting parasitic capacitance of integrated circuit interconnection line

Abstract

The invention belongs to the related technical field of integrated circuits, and particularly relates to a stray capacitance extraction method for an integrated circuit interconnection line, which comprises the following steps: constructing a conductor surface and internal sampling point set; constructing a stray capacitance matrix which is formed by capacitors connected in pairs and has all initial values of zero; generating an ideal surface potential value set corresponding to the surface sampling point of each conductor; a neural network structure composed of an input layer, a single hidden layer and an output layer is constructed, a surface sampling point is used as input, a mean square error between an ideal surface potential value corresponding to the surface sampling point and output of the neural network is used as a loss function, and a Green function of a Poisson equation is used as a hidden layer activation function. Taking all equivalent point charge positions as center coordinates of a hidden layer activation function; and training the weight coefficient of each neuron of the hidden layer, correspondingly taking the weight coefficient as the equivalent charge value of each equivalent point charge, obtaining the equivalent charge values of all equivalent point charges of each conductor, and updating the parasitic capacitance matrix. According to the invention, stray capacitance extraction can be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field related to integrated circuits, and more specifically, relates to a method for extracting parasitic capacitance of interconnection lines of integrated circuits. Background Art

[0002] With the continuous advancement of semiconductor manufacturing process technology, the size of integrated circuits has been shrinking accordingly. In this case, the integration density of chips has increased significantly, resulting in a denser arrangement of interconnects. The distance between interconnects has become smaller and smaller, and at the same time, the process changes of the interconnects themselves have become more and more obvious. Therefore, the parasitic effects between interconnects have become more serious, and the influence of parasitic parameters, especially parasitic capacitance, on circuits has become more and more significant. How to accurately extract the parameters of these parasitic effects has become one of the key issues in the field of integrated circuits. At present, the mainstream interconnect parasitic capacitance field solvers can be divided into two categories according to the solution principle. One is the traditional discrete numerical method, which is used to solve physical field equations, such as the finite difference method and the boundary element method; the other is the method of solving integrals, such as the floating random walk method, which uses floating random walks to convert the calculation of conductor charge into Monte Carlo integrals. The floating random walk method has higher computational efficiency and accuracy than several other traditional numerical methods, but the calculation results have variance, so the symmetry of the interconnect capacitance matrix is ​​poor, and it often faces challenges when dealing with non-Manhattan shaped conductors (with process variability) and complex dielectric distributions; the accuracy of traditional numerical discrete methods is lower than that of random shape methods, and the need to divide discrete grids requires a large computational cost (especially for non-Manhattan shaped conductors).

[0003] The rapidly developing neural networks are playing an increasingly important role in the field of integrated circuit electronic design automation. Great progress has been made in the research of data-driven neural network parasitic capacitance prediction methods. However, there are few related studies on methods of using neural networks to directly solve parasitic capacitance, and no machine learning method for solving parasitic capacitance fields that is equal to methods such as boundary elements has been proposed. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a method for extracting parasitic capacitance of integrated circuit interconnects, which aims to organically combine artificial neural networks with the physical problem of solving parasitic capacitance, give full play to the flexible and efficient characteristics of neural networks, and achieve high-precision parasitic capacitance extraction.

[0005] To achieve the above object, according to one aspect of the present invention, a method for extracting parasitic capacitance of an integrated circuit interconnect line is provided, comprising: S1, constructing a surface sampling point position coordinate set and an internal sampling point position coordinate set for each conductor in the integrated circuit, wherein each internal sampling point is regarded as the position of an equivalent point charge; constructing a parasitic capacitance matrix composed of all conductor interconnected capacitances with initial values ​​of zero; S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values ​​to 0; according to the ideal surface potential value of each conductor, generate a set of ideal surface potential values ​​corresponding to the surface sampling points of the conductor one by one; S3. Construct a neural network structure consisting of an input layer, a single hidden layer and an output layer, wherein the position coordinates of the surface sampling points are used as the input of the neural network, the mean square error between the ideal surface potential values ​​corresponding to the surface sampling points and the output of the neural network is used as the loss function, the number of neurons is the same as the number of all equivalent point charges corresponding to all conductors, the Green's function of the Poisson equation in three-dimensional space is used as the activation function of the single hidden layer, and the position coordinates of all equivalent point charges are used as the central coordinates of the hidden layer activation function; based on the surface sampling point position coordinate set of all conductors and the one-to-one corresponding ideal surface potential value set, the weight coefficient of each neuron in the single hidden layer of the neural network is trained, corresponding to the equivalent charge value of each equivalent point charge, and the equivalent charge value of all equivalent point charges in each conductor is obtained; S4. Calculate the charge of each conductor using the equivalent charge values ​​of all equivalent point charges in the conductor to calculate the interconnection capacitance between the two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor acts as a primary conductor.

[0006] Furthermore, the surface sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional space model of each conductor, a preset number of sampling points are sampled on the surface of the conductor by uniform random sampling or uniform grid sampling to obtain a position coordinate set of the surface sampling points.

[0007] Furthermore, the internal sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional spatial model of each conductor, all internal sampling points are set to be distributed in the original length of each conductor according to the preset sampling ratio parameter. aOn the surface of the three-dimensional closed structure obtained after proportional reduction, the interior of the conductor is sampled to obtain a set of internal sampling point position coordinates.

[0008] Furthermore, when there are conductors with irregular surfaces in the integrated circuit, each conductor with an irregular surface is treated as a conductor with a regular surface, and the training described in S1-S3 is performed; the training described in S1-S3 is performed according to the actual surface of the conductor with the irregular surface, wherein the number of surface sampling points obtained by the two samplings is the same and the number of internal sampling points is the same, and the initial value of the weight coefficient of each neuron in the neural network during the second training is the weight coefficient of each neuron in the neural network obtained after the first training; and S4 is performed using the equivalent charge value of all equivalent point charges in each conductor finally obtained.

[0009] Furthermore, in S3, the weight coefficient of each neuron in a single hidden layer of the neural network is trained by using a gradient descent method or a least square method.

[0010] Furthermore, when the least squares method is used to train the weight coefficients of each neuron in a single hidden layer of a neural network, after the least squares method training is completed, another internal sampling point position coordinate set is constructed for each conductor, and the equivalent charge values ​​of all equivalent point charges corresponding to each conductor obtained by the current training are used to calculate the electrostatic potential jointly excited by all equivalent point charges on the conductor at the position of each surface sampling point, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined. The mean square error between the difference between the one-to-one correspondence between the surface sampling points and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge values ​​of all equivalent point charges determined by the two internal sampling point position coordinate sets for each conductor.

[0011] According to another aspect of the present invention, an electronic device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0012] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the steps of the method described above.

[0013] According to another aspect of the present invention, a computer program product is provided, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the steps of the method described above are implemented.

[0014] In general, compared with the prior art, the technical solution conceived by the present invention has the following beneficial effects: 1. The present invention proposes a method for extracting parasitic capacitance of integrated circuit interconnects. The basic principle is to assume that there are a large number of equivalent point charges inside each conductor, and all the equivalent point charges work together to make the surface potential value of each conductor reach an expected value, so as to calculate the parasitic capacitance matrix. Specifically, a neural network structure is constructed consisting of an input layer, a single hidden layer and an output layer, with the Green's function of the Poisson equation in three-dimensional space as the activation function (i.e., kernel function) of the single hidden layer, and the position coordinates of all equivalent point charges as the center coordinates of the kernel function of the single hidden layer. The equivalent charge values ​​of all equivalent point charges can be calculated, thereby calculating the capacitance matrix. Therefore, as the first parasitic capacitance numerical calculation method completely driven by machine learning, this method has sufficient theoretical support, distinct physical significance and interpretability, which ensures the reliability of the solution results. Compared with traditional algorithms such as random walk and finite element, the accuracy of capacitance calculation by this method exceeds that of capacitance calculation by finite element method, and is comparable to the accuracy of the current highest accuracy random walk method. In addition, the variance of the calculation result is smaller than that of the random walk method, that is, the parasitic capacitance matrix calculated by this method has higher symmetry. In addition, due to the structural characteristics of the neural network, different training parameter methods can be selected, so it has higher calculation flexibility; the construction method and parameter training method of the neural network determine that when calculating the interconnection capacitance matrix, it will not be limited by the process deviation and random fluctuation of the interconnection conductor structure (for example, when processing an interconnection conductor structure with an irregular surface, it is first trained: the neural network model for the interconnection line conductor under an ideal state is trained, and the distribution of its equivalent point charge is geometrically similar, and then the position of the sampling point is changed to map it to the actual surface of the conductor with process changes, keep its charge constant, and continue to make the distribution of the equivalent point charge and the sampling point geometrically similar. Finally, this is used as the initial state of the neural network for training, simulating the capacitance of the interconnection line conductor with process deviation, and the high-precision solution of the parasitic capacitance matrix of the interconnection conductor with irregular surface can be quickly achieved); this method organically combines the artificial neural network with the physical problem of parasitic capacitance solution, can give full play to the flexible and efficient characteristics of the neural network, and brings new ideas for numerically solving the physical problem of parasitic capacitance.

[0015] 2. The present invention proposes a sampling method for surface sampling points, which obtains a set of position coordinates of surface sampling points by sampling the surface of the interconnected conductor structure as the input of the constructed neural network model. Compared with the traditional full-space discretization method such as the finite element method, the dimension of the problem is reduced. At the same time, there is no need to perform mesh discretization processing on the interconnected conductor structure, thereby saving the computational cost of mesh generation.

[0016] 3. In the training scheme proposed by the present invention, after the parameters are trained for the first time using the least squares method, another set of internal sampling point position coordinates is constructed for each conductor. According to the equivalent charge values ​​of all equivalent point charges corresponding to each conductor obtained by the current training, the electrostatic potential jointly excited by all equivalent point charges on the conductor at the position of each surface sampling point is calculated, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined. The mean square error between the difference corresponding to the surface sampling points and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained again to obtain the equivalent charge values ​​of all equivalent point charges determined by the two internal sampling point position coordinate sets for each conductor. This scheme reduces the error of the least squares training result through multiple trainings, and ensures the accuracy of the calculation result of the final interconnect capacitance matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of a method for extracting parasitic capacitance of an integrated circuit interconnect provided by an embodiment of the present invention.

[0018] Figure 2 A schematic diagram of the structure and training method of a physical perception extreme learning machine provided in an embodiment of the present invention.

[0019] Figure 3 An overall flow chart of parasitic capacitance extraction provided by an embodiment of the present invention.

[0020] Figure 4 A detailed flow chart of building a neural network model - a physical perception extreme learning machine and calculating the interconnected capacitance matrix of conductors provided in an embodiment of the present invention.

[0021] Figure 5 A diagram of an interconnect conductor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] Embodiment 1 A method for extracting parasitic capacitance of an integrated circuit interconnect line, such as Figure 1 As shown, including: S1, constructing a surface sampling point position coordinate set and an internal sampling point position coordinate set for each conductor in the integrated circuit, wherein each internal sampling point is regarded as the position of an equivalent point charge; constructing a parasitic capacitance matrix composed of all conductor interconnected capacitances with initial values ​​of zero; S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values ​​to 0; according to the ideal surface potential value of each conductor, generate a set of ideal surface potential values ​​corresponding to the surface sampling points of the conductor one by one; S3. Construct a neural network structure consisting of an input layer, a single hidden layer and an output layer, wherein the position coordinates of the surface sampling points are used as the input of the neural network, the mean square error between the ideal surface potential values ​​corresponding to the surface sampling points and the output of the neural network is used as the loss function, the number of neurons is the same as the number of all equivalent point charges corresponding to all conductors, the Green's function of the Poisson equation in three-dimensional space is used as the kernel function of the single hidden layer, and the position coordinates of all equivalent point charges are used as the central coordinates of the kernel function of the single hidden layer; based on the set of surface sampling point position coordinates of all conductors and the one-to-one corresponding set of ideal surface potential values, the weight coefficients of each neuron in the single hidden layer of the neural network are trained, corresponding to the equivalent charge values ​​of each equivalent point charge, and the equivalent charge values ​​of all equivalent point charges in each conductor are obtained; S4. Calculate the charge of each conductor using the equivalent charge values ​​of all equivalent point charges in the conductor to calculate the interconnection capacitance between the two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor acts as a primary conductor.

[0024] It should be noted that the interconnect capacitance is the parasitic capacitance. The above Green function is , the position coordinates of all equivalent point charges are taken as the center coordinates of the single hidden layer kernel function , represents the dielectric constant, Represents the position coordinates of the surface sampling points. The position coordinates of the surface sampling points of the conductor obtained above are used as input, the position of the equivalent point charge obtained above is used as the initial position of the neurons in the hidden layer, and the Green's function of the Poisson equation in three-dimensional space is used as As the activation function of the hidden layer, It is the Euclidean distance between each element in the input surface sampling coordinate set and all hidden layer neurons. The activation function maps the relationship between the input and output to the linear space. The mean square error between the ideal surface potential value of the conductor set above and the output of the neural network is used as the loss function. The equivalent charge value of the equivalent point charge is obtained by solving the coefficient matrix of the linear equation group of the input and output in the linear space.

[0025] In S4, when calculating and updating the parasitic capacitance matrix of the conductor structure, since the electric fields excited by different point charges at the same position in space are linearly superimposed, according to the relationship formula between surface potential and conductor charge capacitance , sum up the equivalent charge values ​​of the equivalent point charges inside each conductor, obtain the self-capacitance when the main conductor is the above-selected conductor and the mutual capacitance between the main conductor and the slave conductor, and write the results into the corresponding positions in the interconnection capacitance matrix of the conductor.

[0026] In addition, in S4, it is determined whether all conductors have been set as main conductors. If there is a conductor that has not been set as the main conductor, it is set as the new main conductor, and its ideal surface potential value is set to 1. The remaining conductors are set as slave conductors, and their ideal surface potential values ​​are set to 0. According to the ideal surface potential value of each conductor, a set of potential values ​​corresponding to its surface sampling point set is generated, and the steps of neural network construction and training are repeated. If all conductors have been set as main conductors, the interconnected capacitance matrix is ​​calculated and output. The principle of selecting another main conductor is that the conductor has not been set as the main conductor. If there are multiple conductors that have not been set as the main conductor, the selection order is not limited.

[0027] A method for extracting parasitic capacitance of integrated circuit interconnects in this embodiment is the first machine learning interconnect parasitic capacitance solution that is completely driven by physical principles rather than data. It uses a neural network to directly solve the interconnect parasitic capacitance matrix of the interconnect conductor structure, which is similar to the basic idea of ​​solving the parasitic capacitance of interconnects using the traditional boundary element method. Its solution principle has distinct physical significance and explainability. This method uses the Green's function of the Poisson's equation as the activation function of the hidden layer in the extreme learning machine, and liberates the position of the equivalent point charge (Green's function excitation source) from the surface of the conductor to the inside of the conductor, which has higher computational flexibility than traditional methods.

[0028] The method for extracting the parasitic capacitance of interconnects provided in this embodiment obtains the model input by sampling on the surface of the interconnect conductor structure, and obtains the excitation source (i.e., neuron) of the Green's function by sampling inside the conductor, so the calculation process of the method will not be limited by the process deviation and random fluctuation of the interconnect conductor structure. For example, preferably, when there is a conductor with an irregular surface in the integrated circuit, each conductor with an irregular surface is regarded as a conductor with a regular surface (the irregular surface has protrusions or depressions, and the regular surface is flat, and "as" means to first treat the conductor with an irregular surface as a conductor with a flat surface), and perform the training described in S1-S3; perform the training described in S1-S3 according to the real surface of the conductor with an irregular surface; wherein the number of surface sampling points obtained by the two samplings is the same and the number of internal sampling points is the same, and the initial value of the weight coefficient of each neuron in the neural network during the second training is the weight coefficient of each neuron in the neural network obtained after the first training. That is, when dealing with an interconnect conductor structure with an irregular surface, it is first pre-trained: the neural network model for the interconnect conductor under an ideal state is trained, and the distribution of its equivalent point charge is geometrically similar. Then, the position of the sampling point is changed to map it to the actual surface of the conductor with process changes, keeping its charge constant, and continuing to make the distribution of the equivalent point charge and the sampling point geometrically approximate. Finally, this is used as the initial state of the neural network for training to simulate the capacitance of the interconnect conductor with process deviations, so that the high-precision solution of the parasitic capacitance matrix of the interconnect conductor with irregular surfaces can be quickly achieved.

[0029] In addition, the method for extracting the parasitic capacitance of interconnect lines provided in this embodiment is a machine learning method for parasitic capacitance of interconnect conductor structures that is completely driven by the physical underlying layer. Therefore, this method has a high degree of parallelization characteristics and software and hardware affinity. With the improvement of hardware performance such as GPU and the improvement of machine learning software framework, faster computing speed and higher computing efficiency will be achieved.

[0030] As a preferred implementation, the surface sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of an integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional space model of each conductor, a preset number of sampling points are sampled on the surface of the conductor by uniform random sampling or uniform grid sampling to obtain a position coordinate set of the surface sampling points.

[0031] As a preferred implementation, the internal sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of an integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional spatial model of each conductor, all internal sampling points are set to be distributed in the original length of each conductor according to the preset sampling ratio parameter. a On the surface of the three-dimensional closed structure obtained after proportional reduction, the interior of the conductor is sampled to obtain a set of internal sampling point position coordinates.

[0032] The process layout file of the interconnect conductor includes a binary file that describes the physical layout of the integrated circuit and a file that records the information of each process layer. Among them, the binary file that describes the physical layout of the integrated circuit is a GDSII file commonly used in the integrated circuit post-simulation process; the content of the file about each process layer information, if it is a metal layer, the content includes the name, number of layers, data type, height, and thickness of the metal layer; if it is a through-hole layer, the content includes the name, number of layers, data type, and name of the metal layers connected above and below the through-hole layer.

[0033] GDSII Stream Format (GDSII) is a database file format that is used for data transfer of integrated circuit layouts and has become a de facto industry standard. GDSII is a binary file that contains the geometric shapes, text or labels, and other relevant information of the planes in the integrated circuit layout and can be composed of a hierarchical structure. GDSII data can be used to reconstruct all or part of the layout information.

[0034] According to the interconnect conductor process layout file, the coordinate sets of sampling points are obtained on the three-dimensional surface and inside the three-dimensional space of the conductor structure. As an implementation example, the tool used to read the binary file describing the physical layout of the integrated circuit is the python package "python-gdsii". Among them, "python-gdsii" is a python library that can be used to read, create, modify and save GDSII files. The package also includes methods that can be used to convert binary GDS files into other simple text formats.

[0035] When sampling inside each interconnect conductor, the sampling rules, density and distribution characteristics of the sampling points are first set. The sampling rules can be set to uniformly distributed random sampling or grid sampling. The position distribution of the sampling points is generally set to the three-dimensional closed structure surface obtained after the length of each side of the original conductor is proportionally reduced according to the sampling ratio parameter a. For example, after the length of the conductor side is reduced to a=0.8 times and a=0.9 times the original length, the three-dimensional closed structure surface is sampled according to the set sampling rules and density.

[0036] The method for extracting the parasitic capacitance of interconnect lines provided by the method of this embodiment obtains model input by sampling on the surface of the interconnected conductor structure. Compared with the traditional finite element method, the dimension of the problem is reduced. When solving the three-dimensional interconnected conductor structure, only sampling on the surface is required. When solving the two-dimensional interconnected conductor structure, only sampling on the boundary is required. At the same time, there is no need to perform mesh discretization on the interconnected conductor structure. For example, when calculating the mutual capacitance of an isolated metal sphere, the traditional boundary element algorithm requires complex mesh discretization of the sphere surface, while the equivalent point charge represented by the Green's function excitation source of the Poisson equation is placed at the center of the sphere. Only this unknown variable needs to be solved to determine the electric field distribution in the space outside the conductor under given voltage conditions. Therefore, this method has higher computational efficiency.

[0037] As a preferred implementation, in S3, the weight coefficients of each neuron in a single hidden layer of the neural network are trained using the gradient descent method or the least squares method. In this implementation, the neural network can be trained using the physical perception neural network training method, i.e., using the gradient descent method for back propagation to train the network, or using the least squares method for training. In this case, the neural network is referred to as a physical perception extreme learning machine in this embodiment. Figure 2 When using the gradient descent method, the output value of the model Compared with the ideal surface potential of the conductor mentioned above The mean square error function is used as the loss function in the back-propagation process. The optimizer used can be Adam, AdamW, LBFGS, etc., without limitation. The software framework used to build and train the neural network can be Pytorch, Tensorflow, Jax, etc., without limitation. When using the physical perception neural network training method, that is, the gradient descent method back-propagation to train the network, the position coordinate information of the neuron can be selected as a training parameter. If it is selected as a training parameter, it will take a relatively longer training time, which will make the solution more accurate. In addition, when using the gradient descent method for training, you can also use a batch training method. The specific operation is to train multiple different physical perception extreme learning machine models in sequence, where the subsequent model is used to fit the residuals of the previous model training.

[0038] The physical perception extreme learning machine, a neural network model constructed based on the position coordinate set of equivalent point charges, combines the physical perception neural network and the extreme learning machine and has only one hidden layer. The model can be optimized by two training methods, the least squares method and the gradient descent method, which correspond to the training methods of the extreme learning machine and the physical perception neural network, respectively.

[0039] If the training method of the extreme learning machine is adopted, that is, the weight coefficient is solved directly by the analytical method (i.e., the least square method), because the fitting residual of the weight coefficient obtained by the training method has a certain optimization space, the fitting residual of the training method can be reduced through further training. That is, it can be used as a preferred implementation method, when the least square method is used to train the weight coefficient of each neuron in the single hidden layer of the neural network, after the least square method training is completed, another internal sampling point position coordinate set is constructed for each conductor, and according to the equivalent charge value of all equivalent point charges corresponding to each conductor obtained by the current training, the electrostatic potential jointly excited by all equivalent point charges on the conductor at the position of each surface sampling point is calculated, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined, and the mean square error between the difference between the one-to-one corresponding surface sampling points and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge value of all equivalent point charges determined by the two internal sampling point position coordinate sets for each conductor.

[0040] If the gradient descent method is used, when the iteration reaches the termination condition, the equivalent charge values ​​of all equivalent point charges in each conductor corresponding to a set of neuron weight coefficients with the best prediction performance are determined, and the process jumps to step S4; if the least squares method is used, after S3 is completed, the equivalent charge values ​​of all equivalent point charges in each conductor are determined, and the process jumps to step S4.

[0041] The method for extracting parasitic capacitance of interconnect lines provided in this embodiment can flexibly configure the training method of the neural network according to different actual conditions. For example, no matter which training method is used, a multi-stage training strategy can be adopted, and multiple different neural networks can be trained in sequence, wherein the subsequent model is used to fit the residual of the previously trained model, and thus has high accuracy.

[0042] It should be noted that if the least squares method is used for training, it is preferred to construct two sets of internal sampling point position coordinates, perform two neural network construction and training, and improve the accuracy. The two sets of internal sampling point position coordinates can be constructed in the same way. For example, as mentioned above, according to the three-dimensional space model of each conductor, all the internal sampling points are set to be distributed in the original length of each conductor according to the preset sampling ratio parameter. a On the surface of the three-dimensional closed structure obtained after proportional reduction, the interior of the conductor is sampled to obtain a set of internal sampling point position coordinates. Sampling ratio parameter a The value of can be adjusted according to actual needs. For example, the first internal sampling point position coordinate set corresponds to , the second internal sampling point position coordinate set corresponds to , that is, appropriately increase the sampling ratio parametera , obtaining internal points closer to the surface can speed up the reduction of loss function and residual in the subsequent training and fitting process, and has practical application value. The position of the equivalent point charge sampled for the second time does not coincide with the position in the position coordinate set of the equivalent point charge sampled for the first time.

[0043] An alternative implementation. See Figure 3 , which is a framework process for the whole, please refer to Figure 4 , which is an overall workflow, through the above steps can achieve accurate calculation of the interconnection parasitic capacitance parameter matrix of the interconnection conductor structure.

[0044] like Figure 5 An interconnect conductor structure is shown, and the corresponding interconnect capacitance matrix is ​​obtained by using this method to solve the structure, as follows: The unit of each value is From the matrix, we can see that the symmetry of the matrix is ​​very high, which means that the variance of this algorithm is small.

[0045] The method obtained in this embodiment Figure 5 Calculation results of the self-capacitance of each conductor of the example conductor structure ( ) is compared with the calculation results of other methods. The results are shown in Table 1. It can be seen that the results of this method are comparable to those of the most accurate random walk method ( ) are extremely close, with an average relative error of less than one percent, and the accuracy is higher than the calculation results of Comsol software using the finite element method ( ).

[0046] In general, the method of this embodiment eliminates the computational cost caused by discrete grid division, ensures that the calculation results can achieve high accuracy while having low variance, and is easily applicable to interconnected conductor structures with non-Manhattan conductors. At the same time, it organically combines artificial neural networks with the physical problem of solving parasitic capacitance, which can give full play to the flexible and efficient characteristics of neural networks and bring new ideas to the numerical solution of the physical problem of parasitic capacitance.

[0047] Embodiment 2 The present application also relates to an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0048] The electronic device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The memory may be used to store computer programs and / or modules, and the processor may perform various functions of the electronic device by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory.

[0049] The relevant technical solutions are the same as above and will not be described again here.

[0050] Embodiment 3 The present application also relates to a computer-readable storage medium having a computer program stored thereon, and the steps of the above method are implemented when the computer program is executed by a processor.

[0051] Specifically, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0052] The relevant technical solutions are the same as above and will not be described again here.

[0053] Embodiment 4 The embodiment of the present application provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of the method of the above embodiment of the present application.

[0054] The relevant technical solutions are the same as above and will not be described again here.

[0055] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for extracting parasitic capacitance of an integrated circuit interconnect, characterized in that: include: S1, constructing a surface sampling point position coordinate set and an internal sampling point position coordinate set for each conductor in the integrated circuit, wherein each internal sampling point is regarded as the position of an equivalent point charge; constructing a parasitic capacitance matrix composed of all conductor interconnected capacitances with initial values ​​of zero; S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values ​​to 0; according to the ideal surface potential value of each conductor, generate a set of ideal surface potential values ​​corresponding to the surface sampling points of the conductor one by one; S3. Construct a neural network structure consisting of an input layer, a single hidden layer and an output layer, wherein the position coordinates of the surface sampling points are used as the input of the neural network, the mean square error between the ideal surface potential values ​​corresponding to the surface sampling points and the output of the neural network is used as the loss function, the number of neurons is the same as the number of all equivalent point charges corresponding to all conductors, the Green's function of the Poisson equation in three-dimensional space is used as the activation function of the single hidden layer, and the position coordinates of all equivalent point charges are used as the central coordinates of the hidden layer activation function; based on the surface sampling point position coordinate set of all conductors and the one-to-one corresponding ideal surface potential value set, the weight coefficient of each neuron in the single hidden layer of the neural network is trained, corresponding to the equivalent charge value of each equivalent point charge, and the equivalent charge value of all equivalent point charges in each conductor is obtained; S4. Calculate the charge of each conductor using the equivalent charge values ​​of all equivalent point charges in the conductor to calculate the interconnection capacitance between the two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor acts as a primary conductor.

2. The extraction method according to claim 1, characterized in that The surface sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional space model of each conductor, a preset number of sampling points are sampled on the surface of the conductor by uniform random sampling or uniform grid sampling to obtain a position coordinate set of the surface sampling points.

3. The extraction method according to claim 1, characterized in that The internal sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional spatial model of each conductor, all internal sampling points are set to be distributed in the original length of each conductor according to the preset sampling ratio parameter. a On the surface of the three-dimensional closed structure obtained after proportional reduction, the interior of the conductor is sampled to obtain a set of internal sampling point position coordinates.

4. The extraction method according to claim 1, characterized in that When there are conductors with irregular surfaces in the integrated circuit, each conductor with an irregular surface is treated as a conductor with a regular surface, and the training described in S1-S3 is performed; the training described in S1-S3 is performed according to the actual surface of the conductor with an irregular surface, wherein the number of surface sampling points and the number of internal sampling points obtained by executing S1 twice are the same, and the initial value of the weight coefficient of each neuron in the neural network during the second training is the weight coefficient of each neuron in the neural network obtained after the first training; and S4 is performed using the equivalent charge value of all equivalent point charges in each conductor finally obtained.

5. The extraction method according to any one of claims 1 to 4, characterized in that In S3, the gradient descent method or the least square method is used to train the weight coefficients of each neuron in a single hidden layer of the neural network.

6. The extraction method according to claim 5, characterized in that When the least square method is used to train the weight coefficients of each neuron in a single hidden layer of a neural network, after the least square method training is completed, another internal sampling point position coordinate set is constructed for each conductor, and the equivalent charge values ​​of all equivalent point charges corresponding to each conductor obtained by the current training are used to calculate the electrostatic potential jointly excited by all equivalent point charges on the conductor at the position of each surface sampling point, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined. The mean square error between the difference corresponding to the surface sampling points one by one and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge values ​​of all equivalent point charges determined by the two internal sampling point position coordinate sets for each conductor.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the steps of the method according to any one of claims 1 to 6.

9. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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