An equivalent model circuit of a memristor

Abstract

The present invention discloses a memristor equivalent model circuit, belonging to the technical field of circuit design. This equivalent model circuit is composed of V i variable sub-circuits, φ variable sub-circuits, - ρ variable sub-circuits, V o which are cascaded by variable sub-circuits; the V i variable sub-circuits are connected to the V o variable sub-circuits through ports; the V o variable sub-circuits are connected to the φ variable sub-circuits through ports V i and V i variable sub-circuits; the - ρ variable sub-circuits are connected to the φ variable sub-circuits through ports φ and V o variable sub-circuits are connected to the V i variable sub-circuits through ports V i and are connected to the φ variable sub-circuits through ports φ and are connected to the - ρ variable sub-circuits through ports - ρ The circuit model of the present invention has a clear and simple structure, is easy to implement, and has great significance for the design and research of memristor equivalent model circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and relates to an equivalent circuit structure of a memory element model, and particularly to the design and implementation of a physically realizable equivalent model of a meminductor with hysteresis curve characteristics. Background Art

[0002] In 1971, Professor Chua predicted and first proposed, based on the completeness of circuits, a fourth basic circuit element - memristor, which is juxtaposed with resistors, capacitors, and inductors. This innovative discovery has opened up a new direction for constructing systems based on traditional circuits, making the construction of system circuits no longer limited to traditional elements such as resistors, inductors, and capacitors. In December 2008, at the "Symposium on Memristors and Memristive Systems" held at the University of California, Berkeley, Professor Leon Chua pointed out again that memory elements should not be limited to memristors, but should also be extended to memcapacitors and meminductors. At the same time, it was pointed out that although meminductors and memcapacitors are also memory devices, they are different from memristors, that is, they are energy storage elements. In 2009, through two new variables σ and ρ , the memory elements were extended from memristors to memristive systems, so that the memory elements, like traditional circuit elements, form a complete system.

[0003] In the existing memory element system, some memory elements are made by chemical preparation methods, and the other part uses equivalent substitution circuits to implement memory elements. Among them, the equivalent model construction of memristors has been relatively perfect. However, due to the particularity of the intrinsic variables of meminductors and memcapacitors, there are still certain deficiencies in the current equivalent circuit construction. Therefore, it is of great significance to design a meminductor model and build a corresponding equivalent circuit. Summary of the Invention

[0004] In view of the deficiencies of the prior art, the present invention proposes an equivalent circuit of a meminductor model.

[0005] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0006] The devices adopted by the present invention include a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , an eleventh resistor R 11, the twelfth resistor R 12 , the thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 , the sixteenth resistor R 16 , the seventeenth resistor R 17 , the eighteenth resistor R 18 , the nineteenth resistor R 19 , the first capacitor C 1 , the second capacitor C 2 , the first diode D 1 , the second diode D 2 , the first operational amplifier U 1 , the second operational amplifier U 2 , the third operational amplifier U 3 , the fourth operational amplifier U 4 , the fifth operational amplifier U 5 , the sixth operational amplifier U 6 , the seventh operational amplifier U 7 , the eighth operational amplifier U 8 , the first signal source V 1 , the second signal source V 2 . The memristor model is composed of V i variable quantum circuits, φ variable quantum circuits, - ρ variable quantum circuits, V o variable quantum circuits cascaded.

[0007] The V i variable quantum circuit is connected to the V o through the port V o variable quantum circuit; the non-inverting input terminal of the first operational amplifier U 1 is used as the signal input port A, and the inverting input terminal is connected to its output terminal as the port V i ; one end of the first resistor R 1 is connected to the input port V o , and the other end is connected to the non-inverting input terminal of the first operational amplifier U 1 .

[0008] The φ variable quantum circuit is connected to the V i through the port V i variable quantum circuit; the non-inverting input terminal of the second operational amplifier U 2The inverting input terminal is grounded, and the non-inverting input terminal is connected to one end of the second resistor R 2 The other end of the second resistor R 2 is connected to the input port V i ; One end of the third resistor R 3 is connected to the inverting input terminal of the second operational amplifier U 2 , and the other end is connected to the output of the second operational amplifier U 2 to serve as port - φ ; The first capacitor C 1 is connected in parallel with the third resistor R 3 ; One end of the fourth resistor R 4 is connected to the output terminal of the second operational amplifier U 2 , and the other end is connected to the inverting input terminal of the third operational amplifier U 3 ; One end of the fifth resistor R 5 is connected to the inverting input terminal of the third operational amplifier U 3 , and the other end is connected to the output terminal of the third operational amplifier U 3 and serves as the output port φ ; The non-inverting input terminal of the third operational amplifier U 3 is grounded.

[0009] The - ρ variable quantum circuit is connected to the φ variable quantum circuit through the port φ ; One end of the sixth resistor R 6 is connected to the input port φ , and the other end is connected to the inverting input terminal of the fourth operational amplifier U 4 ; One end of the seventh resistor R 7 is connected to the non-inverting input terminal of the fourth operational amplifier U 4 and the inverting input terminal of the fifth operational amplifier U 5 , and the other end is connected to the input port φ ; One end of the eighth resistor R 8 is connected to the non-inverting input terminal of the fifth operational amplifier U 5 , and the other end is connected to the ground; One end of the ninth resistor R 9 is connected to the inverting input terminal of the fourth operational amplifier U 4 , and the other end is connected to the negative terminal of the second diode D 2 ; The negative terminal of the first diode D 1 is connected to the non-inverting input terminal of the fourth operational amplifier U 4 , and the positive terminal is connected to the output terminal of the fifth operational amplifier U 5 ; The positive terminal of the second diode D 2 is connected to the output terminal of the fourth operational amplifier U 4 , and the negative terminal is connected to the ninth resistor R9 is connected; the tenth resistor R 10 has one end connected to the negative terminal of the second diode D 2 as a port| φ |, and the other end is connected to the inverting input terminal of the sixth operational amplifier; the eleventh resistor R 11 has one end connected to the inverting input terminal of the sixth operational amplifier U 6 , and the other end is connected to the positive terminal of the DC current source V 1 ; the twelfth resistor R 12 has one end connected to the inverting input terminal of the sixth operational amplifier U 6 , and the other end is connected to the output terminal of the sixth operational amplifier U 6 as the output port - ρ ; the second capacitor C 2 is in parallel with the twelfth resistor R 12 , and the non-inverting input terminal of the sixth operational amplifier U 6 is grounded.

[0010] The V o variable quantum circuit is connected to the V i variable quantum circuit through the port V i , and is connected to the φ variable quantum circuit through the port φ , and is connected to the - ρ variable quantum circuit through the port - ρ ; the thirteenth resistor R 13 has one end connected to the inverting input terminal of the seventh operational amplifier U 7 , and the other end is connected to the input port V i ; the fourteenth resistor R 14 has one end connected to the output terminal of the seventh operational amplifier U 7 , and the other end is connected to the inverting input terminal of the seventh operational amplifier U 7 ; the non-inverting input terminal of the seventh operational amplifier U 7 is grounded; the fifteenth resistor R 15 has one end connected to the output terminal of the seventh operational amplifier U 7 , and the other end is connected to the inverting input terminal of the eighth operational amplifier U 8 ; the sixteenth resistor R 16 has one end connected to the input port φ , and the other end is connected to the inverting input terminal of the eighth operational amplifier U 8 ; the seventeenth resistor R 17 has one end connected to the input port - ρ , and the other end is connected to the inverting input terminal of the eighth operational amplifier U 8The inverting input terminal is connected; the eighteenth resistor R 18 One end is connected to the inverting input terminal of the eighth operational amplifier U 8 The other end is connected to the positive terminal of the DC voltage source V 2 The nineteenth resistor R 19 One end is connected to the inverting input terminal of the operational amplifier U 8 The other end is connected to the output terminal of the eighth operational amplifier U 8 as the output port V o ; The non-inverting input terminal of the eighth operational amplifier U 8 is grounded.

[0011] The present invention has the following characteristics and beneficial effects:

[0012] Adopting the above technical solution, the structure is simple, the types of devices used are few, and it does not involve various integrated modules and complex operation modules, greatly reducing the complexity and cost of the circuit. The circuit model structure is clear and simple, easy to implement, and has very important significance for the design and research of the equivalent model circuit of the memristor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of the structure of the present invention;

[0014] Figure 2 is the circuit block diagram of the variable in the equivalent model of the memristor of the present invention V i ;

[0015] Figure 3 is the circuit block diagram of the variable in the equivalent model of the memristor of the present invention φ ;

[0016] Figure 4 is the circuit block diagram of the variable in the equivalent model of the memristor of the present invention - ρ ;

[0017] Figure 5 is the circuit block diagram of the variable in the equivalent model of the memristor of the present invention V o ;

[0018] Figure 6 is the φ ( t ) and i ( t ) timing diagram of the equivalent model of the memristor of the present invention;

[0019] Figure 7 is the φ - i variable phase diagram of the equivalent model of the memristor of the present invention;

[0020] Figure 8 is the φ ( t ) and i ( t ) timing diagram of the equivalent hardware circuit of the memristor of the present invention;

[0021] Figure 9 is the φ - i variable phase diagram of the equivalent hardware circuit of the memristor of the present invention. Detailed implementation manners

[0022] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] The mathematical expression on which the equivalent model circuit of the memristor designed by the present invention is based is shown in Equation (1)

[0024] (1)

[0025] where φ , i respectively represent the magnetic flux and current of the memristor, which are the constitutive variables of the memristor and represent the input and output of the system. r is obtained by φ integration. In addition, in the above expression, the parameters are set as a =-1 / 10, b =5 / 3, c =0.5 and d =2.57. The magnetic flux φ can be obtained by integrating the input voltage.

[0026] The equivalent model circuit of the memristor designed by the present invention is composed of four cascaded sub-circuits, as Figure 1 shown, where A the port is the signal input port of the equivalent model of the memristor. At A the end, the input voltage V in , and the feedback output voltage V o pass through the adder voltage follower circuit composed of the operational amplifier U 1 to obtain the variable V i . In the next stage, the second resistor R 2 , the third resistor R 3 , the first capacitor C 1 and the second operational amplifier U 2The composed reverse integration circuit has an input of V i , and after the integration operation of the second operational amplifier U 2 , a negative magnetic flux (- φ ) is obtained at the output. The third operational amplifier U 3 , the fourth resistor R 4 and the fifth resistor R 5 form a reverse proportional operation circuit, which operates on the input - φ to obtain φ . In order to perform an absolute value operation on the magnetic flux signal, in the next stage, it consists of the fourth operational amplifier U 4 , the fifth operational amplifier U 5 and the sixth operational amplifier U 6 , the first diode D 1 and the second diode D 2 , the sixth resistor R 6 , the seventh resistor R 7 , the eighth resistor R 8 and the ninth resistor R 9 form an absolute value operation circuit. When the input is φ , the output is . Similarly, the reverse addition integration circuit composed of the sixth operational amplifier U 6 , the tenth resistor R 10 , the eleventh resistor R 11 and the twelfth resistor R 12 , the second capacitor C 2 , the first signal source V 1 can perform an operation to obtain the variable - ρ . Next, - ρ , V i , φ and the second signal source V 2 pass through the seventh operational amplifier U 7 and the eighth operational amplifier U 8 , the thirteenth resistor R13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 , the sixteenth resistor R 16 , the seventeenth resistor R 17 , the eighteenth resistor R 18 and the nineteenth resistor R 19 are added by the inverting adder circuit composed of them to obtain the output voltage of the memristor V o , finally, the output voltage V o passes through the first resistor R 1 to convert the voltage into current, that is, the current flowing through the memristor can be obtained i .

[0027] As Figure 2 shown, in the V i variable quantum circuit, the non-inverting input terminal of the first operational amplifier U 1 is used as the signal input port A , and the inverting input terminal is connected to its output terminal as the port V i ; one end of the first resistor R 1 is connected to the input port V o , and the other end is connected to the non-inverting input terminal of the first operational amplifier U 1 .

[0028] As Figure 3 shown, in the φ variable quantum circuit, the non-inverting input terminal of the second operational amplifier U 2 is grounded, the inverting input terminal is connected to one end of the second resistor R 2 , the other end of the second resistor R 2 is connected to the input port V i ; one end of the third resistor R 3 is connected to the inverting input terminal of the second operational amplifier U 2 , and the other end is connected to the output of the second operational amplifier U 2 as the port - φ ; the first capacitor C 1 is connected in parallel with the third resistor R 3 ; one end of the fourth resistor R 4 is connected to the output terminal of the second operational amplifier U 2 , and the other end is connected to the inverting input terminal of the third operational amplifier U 3 ; one end of the fifth resistor R 5 is connected to the inverting input terminal of the third operational amplifier U 3 , and the other end is connected to the third operational amplifier U3 are connected to the output end and serve as the output port φ ; the third operational amplifier U 3 The non-inverting input terminal is grounded.

[0029] Such as Figure 4 shown, in the said - ρ variable sub-circuit, the sixth resistor R 6 One end is connected to the input port φ and the other end is connected to the inverting input terminal of the fourth operational amplifier U 4 ; the seventh resistor R 7 One end is connected to the non-inverting input terminal of the fourth operational amplifier U 4 and the inverting input terminal of the fifth operational amplifier U 5 and the other end is connected to the input port φ ; the eighth resistor R 8 One end is connected to the non-inverting input terminal of the fifth operational amplifier U 5 and the other end is connected to the ground; the ninth resistor R 9 One end is connected to the inverting input terminal of the fourth operational amplifier U 4 and the other end is connected to the negative terminal of the second diode D 2 ; the negative terminal of the first diode D 1 is connected to the non-inverting input terminal of the fourth operational amplifier U 4 and the positive terminal is connected to the output end of the fifth operational amplifier U 5 ; the positive terminal of the second diode D 2 is connected to the output end of the fourth operational amplifier U 4 and the negative terminal is connected to the ninth resistor R 9 ; the tenth resistor R 10 One end is connected to the negative terminal of the second diode D 2 and serves as the port | φ |, and the other end is connected to the inverting input terminal of the sixth operational amplifier; the eleventh resistor R 11 One end is connected to the inverting input terminal of the sixth operational amplifier U 6 and the other end is connected to the positive terminal of the DC current source V 1 ; the twelfth resistor R 12 One end is connected to the inverting input terminal of the sixth operational amplifier U 6 and the other end is connected to the output end of the sixth operational amplifier U 6 and serves as the output port - ρ ; the second capacitor C 2 is in parallel with the twelfth resistor R 12 ; the non-inverting input terminal of the sixth operational amplifier U 6 is grounded.

[0030] Such as Figure 5 shown, the said V oIn the variable sub-circuit, the thirteenth resistor R 13 has one end connected to the inverting input terminal of the seventh operational amplifier U 7 and the other end connected to the input port V i ; the fourteenth resistor R 14 has one end connected to the output terminal of the seventh operational amplifier U 7 and the other end connected to the inverting input terminal of the seventh operational amplifier U 7 ; the non-inverting input terminal of the seventh operational amplifier U 7 is grounded; the fifteenth resistor R 15 has one end connected to the output terminal of the seventh operational amplifier U 7 and the other end connected to the inverting input terminal of the eighth operational amplifier U 8 ; the sixteenth resistor R 16 has one end connected to the input port φ and the other end connected to the inverting input terminal of the eighth operational amplifier U 8 ; the seventeenth resistor R 17 has one end connected to the input port - ρ and the other end connected to the inverting input terminal of the eighth operational amplifier U 8 ; the eighteenth resistor R 18 has one end connected to the inverting input terminal of the eighth operational amplifier U 8 and the other end connected to the positive pole of the DC voltage source V 2 ; the nineteenth resistor R 19 has one end connected to the inverting input terminal of the operational amplifier U 8 and the other end connected to the output terminal of the eighth operational amplifier U 8 as the output port V o ; the non-inverting input terminal of the eighth operational amplifier U 8 is grounded.

[0031] To verify the effectiveness of the memristor circuit model, a circuit was built in the Multisim simulation software, and a magnetic flux excitation φ ( t ) = φ 0 cos(2π ft ) ( φ 0 = 4V, f = 100Hz) was applied to the circuit model. Figure 6 shows the timing relationship between φ ( t ) and i ( t ), Figure 7 and shows φ - iThe phase relationship between variables shows a hysteresis curve waveform between the constitutive variables unique to the memristor circuit, indicating that it conforms to the definition of the memristor equivalent model. Further, based on the memristor equivalent sub-circuit structure and component parameters, a hardware circuit was built to further prove its feasibility and effectiveness. In the hardware circuit, the operational amplifier uses OP07C (U 1 to U 8 ) and its operating voltage is set to ±15V. The diode uses 1N4007 (D 1 and D 2 ). The parameters of the remaining circuit components and the DC voltage sources (V 1 and V 2 ) are the same as the values set in the sub-circuit diagram. Figure 8 shows φ ( t ) and i ( t )'s timing relationship. Figure 9 shows φ - i the phase relationship between variables. The test results of the hardware circuit, the simulation circuit results, and the theoretical analysis results are all consistent, fully verifying the realizability and effectiveness of the memristor model circuit of the present invention.

[0032] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions, and variations to these embodiments including components still fall within the protection scope of the present invention.

Claims

1. A memristor equivalent model circuit, characterized in that: By V i Variable subcircuit, Variable subcircuit, -ρ variable subcircuit, V o It is composed of variable subcircuits cascaded; The V i The variable subcircuit passes through port V o With V o The variable subcircuits are connected; The variable subcircuit passes through port V i With V i The variable subcircuit is connected; the -ρ variable subcircuit is connected through the port and The variable sub-circuit is connected; the V o The variable subcircuit passes through port V i With V i The variable subcircuits are connected through ports and The variable subcircuits are connected, and connected to the -ρ variable subcircuits through ports -ρ; The V i In the variable subcircuit, the first operational amplifier U1 has a non-inverting input terminal as a signal input port A, and a reverse input terminal connected to its output terminal as a port V i ; One end of the first resistor R1 is connected to the input port V o The other end is connected to the same-direction input terminal of the first operational amplifier U1; Said In the variable subcircuit, the same-direction input terminal of the second operational amplifier U2 is grounded, the reverse input terminal is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the input port V i One end of the third resistor R3 is connected to the reverse input terminal of the second operational amplifier U2, and the other end is connected to the output of the second operational amplifier U2 as a port - The first capacitor C1 is connected in parallel with the third resistor R3; one end of the fourth resistor R4 is connected to the output end of the second operational amplifier U2, and the other end is connected to the reverse input end of the third operational amplifier U3; one end of the fifth resistor R5 is connected to the reverse input end of the third operational amplifier U3, and the other end is connected to the output end of the third operational amplifier U3 and serves as an output port The non-inverting input terminal of the third operational amplifier U3 is grounded; In the -ρ variable subcircuit, one end of the sixth resistor R6 is connected to the input port One end of the seventh resistor R7 is connected to the same-direction input terminal of the fourth operational amplifier U4 and the reverse input terminal of the fifth operational amplifier U5, and the other end is connected to the input port One end of the eighth resistor R8 is connected to the same-direction input terminal of the fifth operational amplifier U5, and the other end is connected to the ground; one end of the ninth resistor R9 is connected to the reverse input terminal of the fourth operational amplifier U4, and the other end is connected to the negative end of the second diode D2; the negative end of the first diode D1 is connected to the same-direction input terminal of the fourth operational amplifier U4, and the positive end is connected to the output terminal of the fifth operational amplifier U5; the positive end of the second diode D2 is connected to the output terminal of the fourth operational amplifier U4, and the negative end is connected to the ninth resistor R9; the tenth resistor R 10 One end is connected to the negative end of the second diode D2 as a port The other end is connected to the inverting input end of the sixth operational amplifier; the eleventh resistor R 11 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the positive end of the DC current source V1; the twelfth resistor R 12 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the output end of the sixth operational amplifier U6 as the output port -ρ; the second capacitor C2 is connected to the twelfth resistor R 12 In parallel; the same-direction input terminal of the sixth operational amplifier U6 is grounded; The V o In the variable subcircuit, the thirteenth resistor R 13 One end is connected to the inverting input terminal of the seventh operational amplifier U7, and the other end is connected to the input port V i Connected; fourteenth resistor R 14 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the seventh operational amplifier U7; the same-inverting input end of the seventh operational amplifier U7 is grounded; the fifteenth resistor R 15 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the eighth operational amplifier U8; a sixteenth resistor R 16 One end and input port The other end is connected to the inverting input terminal of the eighth operational amplifier U8; the seventeenth resistor R 17 One end is connected to the input port -ρ, and the other end is connected to the inverting input terminal of the eighth operational amplifier U8; the eighteenth resistor R 18 One end is connected to the inverting input terminal of the eighth operational amplifier U8, and the other end is connected to the positive electrode of the DC voltage source V2; the nineteenth resistor R 19 One end is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the eighth operational amplifier U8 as the output port V o ; The same-direction input terminal of the eighth operational amplifier U8 is grounded.

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