Graphics processing system, graphics processor, and computing device

Abstract

The present disclosure relates to a graphics processing system, comprising at least two graphics processing pipelines and a pipeline control module. Each graphics processing pipeline comprises: a geometry processing pipeline configured to receive graphics input data assigned to the corresponding graphics processing pipeline, generate and output stream output data corresponding to the received graphics input data; a stream output module configured to receive the stream output data from the corresponding geometry processing pipeline, output a size of the received stream output data to the pipeline control module, receive a stream output address from the pipeline control module, and write the received stream output data to a target memory based on the received stream output address. The pipeline control module is configured to determine the corresponding stream output address based on the size of each stream output data, and feed back the determined stream output address to the corresponding stream output module, each stream output address being determined such that each stream output data is stored in a preset order of each graphics input data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computer technology, and in particular, to a graphics processing system, a graphics processing unit and a computing device. BACKGROUND

[0002] In the field of computer technology, various graphics data can be processed by a graphics processing unit (GPU). In the graphics processing unit, there is a graphics processing pipeline. The graphics processing pipeline mainly includes a geometry processing pipeline and a fragment processing pipeline. The geometry processing pipeline is mainly responsible for vertex processing, primitive assembly, tessellation and geometry shading processing, etc., and the fragment processing pipeline is mainly responsible for rasterization and calculation of the color of each pixel. The input data of the fragment processing pipeline can be the output data of the geometry processing pipeline. In some cases, there can be a need to read the output data of the geometry processing pipeline, for example, for secondary processing of the data or for other purposes, and therefore, how to efficiently and reliably store the output data of the geometry processing pipeline to a designated memory (such as a memory) is a problem that is concerned in the field. SUMMARY

[0003] In view of the above, the present disclosure provides a graphics processing system, a graphics processing unit and a computing device, which help to solve or at least alleviate the above problems.

[0004] According to an aspect of the present disclosure, a graphics processing system is provided, which is characterized in that the graphics processing system comprises at least two graphics processing pipelines and a pipeline control module, wherein each graphics processing pipeline of the at least two graphics processing pipelines comprises: a geometry processing pipeline configured to receive graphics input data assigned to the corresponding graphics processing pipeline, and to generate and output stream output data corresponding to the received graphics input data; a stream output module configured to receive the stream output data from the corresponding geometry processing pipeline, to output the size of the received stream output data to the pipeline control module, and to receive a stream output address from the pipeline control module and write the received stream output data to a target memory based on the received stream output address, wherein the pipeline control module is configured to determine the stream output address corresponding to each stream output data based on the size of each received stream output data, and to feed back the determined stream output address to the corresponding stream output module, wherein each stream output address is determined such that each stream output data is stored in the target memory in a preset order of each graphics input data corresponding thereto.

[0005] In some embodiments, the pipeline control module is further configured to: sequentially receive sizes of the stream output data from the stream output modules according to the preset order of the graphics input data corresponding to the stream output data; and for each received size of the stream output data, update the current stream output address based on a sum of an address increment corresponding to the size of the stream output data and the current stream output address, and feed back the updated current stream output address to the corresponding stream output module.

[0006] In some embodiments, the at least two graphics processing pipelines have an index order, the multiple portions of the graphics input data having the preset order are sequentially assigned to the corresponding graphics processing pipelines based on the index order, and wherein the pipeline control module is further configured to: sequentially receive sizes of the stream output data from the stream output modules of each of the at least two graphics processing pipelines based on the index order.

[0007] In some embodiments, the stream output module is further configured to: in response to receiving a complete portion of the stream output data from the corresponding geometry processing pipeline, determine and output a size of the complete portion of the stream output data to the pipeline control module.

[0008] In some embodiments, the graphics input data assigned to the corresponding graphics processing pipeline includes a tail string at an end of the data, and the stream output module is further configured to: in response to detecting the tail string upon receiving each portion of the stream output data, determine and output a size of the portion of the stream output data based on the stream output data received before the tail string.

[0009] In some embodiments, the stream output module of each graphics processing pipeline includes a buffer for storing the stream output data from the corresponding geometry processing pipeline, and the stream output module is further configured to: write the received stream output data to the buffer based on a position indicated by a first pointer, and update the first pointer based on a size of the written data; read the stored stream output data from the buffer based on a position indicated by a second pointer, write the read stream output data to a target memory based on the received stream output address, and update the second pointer based on a size of the read data, wherein the first pointer and the second pointer are initialized to indicate the same position in the buffer when the graphics processing system is initialized.

[0010] In some embodiments, the at least two graphics processing pipelines are configured to process the graphics input data assigned to each graphics processing pipeline in parallel.

[0011] In some embodiments, the graphics input data assigned to each graphics processing pipeline is obtained by dividing to-be-processed graphics data, and the preset order of the graphics input data is an order in which the graphics input data appears in the to-be-processed graphics data.

[0012] According to another aspect of the present disclosure, a graphics processing system is provided, which comprises a graphics processing pipeline according to various embodiments of the preceding aspects.

[0013] According to yet another aspect of the present disclosure, a computing device is provided, which comprises a graphics processing pipeline according to the preceding aspects.

[0014] In the graphics processing system provided by the present disclosure, by means of the pipeline control module and the stream output module arranged in each graphics processing pipeline, the stream output function can be implemented in the case of enabling multiple graphics processing pipelines, and it is ensured that the stream output data can be stored in the target memory in the expected preset order. Thus, it is helpful to improve the stream output capability of the graphics processing system, reduce the waste of hardware resources, and improve the overall processing efficiency of the graphics processing system.

[0015] These and other aspects of the present disclosure will become apparent from the embodiments described below, and will be clarified by reference to the embodiments described below. BRIEF DESCRIPTION OF DRAWINGS

[0016] In the following description of the exemplary embodiments in conjunction with the accompanying drawings, more details, features and advantages of the present disclosure are disclosed, in which:

[0017] Figure 1 An example architecture diagram of a graphics processing system in the related art is schematically shown;

[0018] Figure 2 An example architecture diagram of a graphics processing system according to some embodiments of the present disclosure is schematically shown;

[0019] Figure 3 Another example architecture diagram of a graphics processing system according to some embodiments of the present disclosure is schematically shown;

[0020] Figure 4 An example flowchart of a graphics processing process according to some embodiments of the present disclosure is schematically shown;

[0021] Figure 5 An example block diagram of a graphics processing pipeline according to some embodiments of the present disclosure is schematically shown;

[0022] Figure 6 An example block diagram of a computing device according to some embodiments of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0023] In the present disclosure, a graphics processing pipeline can be understood as a collection of functional modules that perform multiple graphics processing operations in a graphics processing system, wherein each functional module can be implemented in hardware, software, or a combination of hardware and software. The graphics processing pipeline can receive graphics data and, based on the graphics data, perform a series of processing to ultimately render a corresponding image. For example, the graphics data may include vertex data, texture data, etc. for rendering the corresponding image. As previously mentioned, the graphics processing pipeline can include a geometry processing pipeline and a fragment processing pipeline. The geometry processing pipeline focuses on the processing and operation of geometric data, and is mainly responsible for vertex processing, primitive assembly, surface tessellation, and geometry shading processing, etc. The fragment processing pipeline focuses on pixel-level data processing, and is mainly responsible for rasterization and calculating the color of each pixel, such as determining the color and attributes of each pixel by performing pixel-level lighting calculations, texture sampling, depth testing, and other operations. The input data of the fragment processing pipeline can be the output data of the geometry processing pipeline.

[0024] Figure 1 Schematically shows an example architecture diagram of a graphics processing system 100 in the related art. Figure 1 As shown, the graphics processing system 100 may include at least one graphics processing pipeline 110-1 to 110-N, where N is an integer greater than or equal to 1. Each graphics processing pipeline may include a geometry processing pipeline and a fragment processing pipeline, such as Figure 1 The geometry processing pipelines 111-1 to 111-N and the fragment processing pipelines 112-1 to 112-N are shown, wherein the geometry processing pipeline in each graphics processing pipeline is coupled to the fragment processing pipeline, and the input data of the fragment processing pipeline can be the output data of the geometry processing pipeline. In some embodiments, there can also be a stream output module after the geometry processing pipeline, which can output the processing results of the geometry processing pipeline to a target storage, such as a memory, so that the stored data can be input into the geometry processing pipeline again for repeated processing to achieve the desired processing effect, or the stored data can also be read by various programmable shaders or central processing units (CPUs) to perform other desired processing. Subsequent processing of the stored data can be performed according to the user's expectations and will not be described in detail here. In the present disclosure, the processing results of the geometry processing pipeline can also be referred to as stream output data.

[0025] However, due to the existence of stages such as surface subdivision and geometry shading in the geometry processing pipeline, for different graphics input data provided to the geometry processing pipeline, even if the provided graphics input data has the same data amount, the data amount of the stream output data corresponding to each graphics input data is often different, and the data amount of the stream output data corresponding to each graphics input data cannot be determined until the geometry processing pipeline finishes processing the graphics input data. In addition, in order to facilitate data reading, it is generally required that the stream output data be continuous when stored. Therefore, in the architecture shown in Figure 1 If two or more geometry processing pipelines are enabled at the same time and two or more stream output modules are correspondingly enabled, it will be difficult to guarantee the continuity of the storage of the stream output data. Therefore, in the related art, when the stream output function is used, only one geometry processing pipeline and one corresponding stream output module are enabled. This not only wastes hardware resources, but also when the geometry processing task is heavy, the geometry processing pipeline becomes the bottleneck of the entire graphics processing system.

[0026] To solve the above problems, the present disclosure provides a graphics processing system which can continuously output the stream output data of multiple geometry processing pipelines to a target memory, thereby allowing the stream output function to be enabled while multiple geometry processing pipelines are enabled, greatly improving the stream output capability of the graphics processing system, avoiding the waste of hardware resources, and further improving the overall processing efficiency of the graphics processing system.

[0027] Figure 2 An example architecture diagram of a graphics processing system 200 according to some embodiments of the present disclosure is schematically shown. As shown in Figure 2 The graphics processing system 200 can include at least two graphics processing pipelines 210-1 to 210-N and one pipeline control module 220, where N is an integer greater than or equal to 2. Each of the at least two graphics processing pipelines 210-1 to 210-N includes a geometry processing pipeline and a stream output module, for example, as shown in Figure 2 The graphics processing pipeline 210-1 includes a geometry processing pipeline 211-1 and a stream output module 212-1, and the graphics processing pipeline 210-N includes a geometry processing pipeline 211-N and a stream output module 212-N. In addition, optionally, similar Figure 1 In the architecture shown, each of the graphics processing pipelines 210-1 to 210-N can also include a fragment processing pipeline, and within each graphics processing pipeline, the fragment processing pipeline can be coupled to the geometry processing pipeline and obtain the processing result of the geometry processing pipeline.

[0028] Each of the geometry processing pipelines 211-1 to 211-N can be configured to receive graphics input data assigned to a corresponding graphics processing pipeline, and to generate and output stream output data corresponding to the received graphics input data. Here, the corresponding graphics processing pipeline should be understood as the graphics processing pipeline to which the geometry processing pipeline belongs, and different graphics processing pipelines can be assigned different graphics input data. Optionally, the geometry processing pipeline can perform one or more of vertex processing, primitive assembly, tessellation, geometry shading, etc. on the received graphics input data, and output stream output data corresponding to the received graphics input data based on the processed data. Optionally, after processing of one piece of graphics input data is completed, i.e., after the corresponding stream output data is output, the geometry processing pipeline can continue to receive and process the next piece of graphics input data assigned to the graphics processing pipeline, if any.

[0029] Exemplarily, the graphics input data assigned to each graphics processing pipeline can be obtained by dividing a piece of to-be-processed graphics data. The to-be-processed graphics data can be graphics data obtained from an upper application program, from a central processing unit, read from an internal or external storage device, received from other devices, or obtained in other manners, or data obtained by preprocessing such graphics data. A piece of to-be-processed graphics data can correspond to a frame of image, for example, or can be defined in other manners according to different application scenarios. Exemplarily, a piece of to-be-processed graphics data can be divided by the graphics processing system 200 or other systems or devices to obtain two or more pieces of graphics input data, which can be assigned to each of the graphics processing pipelines 210-1 to 210-N according to a preset rule. Optionally, the two or more pieces of graphics input data can have a fixed size, which can be pre-specified, or adaptively determined according to one or more of the state of the graphics processing system and the size of the to-be-processed graphics data, etc. Optionally, when processing a piece of to-be-processed graphics data, a graphics processing pipeline can be assigned one or more pieces of graphics input data, and can process the assigned graphics input data in sequence. In the present disclosure, the graphics input data assigned to each graphics processing pipeline can also be referred to as inter-core interleaved data.

[0030] The two or more pieces of graphic input data can not have dependency relationship with each other, and thus can have good parallelism. Thus, in some embodiments, the at least two graphic processing pipelines 210-1 to 210-N can be configured to process the graphic input data assigned to each graphic processing pipeline in parallel. More specifically, each geometry processing pipeline 211-1 to 211-N can be configured to process the graphic input data assigned to the corresponding graphic processing pipeline in parallel and generate corresponding stream output data, and the processing procedure of each geometry processing pipeline can be completely independent of each other. Such parallel processing helps to maximize the utilization of hardware resources in the graphic processing system and improve the graphic processing efficiency.

[0031] Each of the stream output modules 212-1 to 212-N can be configured to receive the stream output data from the corresponding geometry processing pipeline, output the size of the received stream output data to the pipeline control module 220, and receive the stream output address from the pipeline control module 220 and write the received stream output data to the target memory based on the received stream output address. In various embodiments of the present disclosure, the stream output modules and the geometry processing pipelines can be one-to-one corresponding, and a set of corresponding stream output modules and geometry processing pipelines should be understood as the stream output modules and the geometry processing pipelines included in the same graphic processing pipeline, such as, Figure 2 The corresponding geometry processing pipeline of the stream output module 212-1 shown is the geometry processing pipeline 211-1. The stream output module can be coupled with the corresponding geometry processing pipeline and receive the stream output data from the corresponding geometry processing pipeline through a port. In the present disclosure, the size of the stream output data can be understood as the data amount of the stream output data, which can be determined in any known manner in the art, and the present disclosure does not make specific limitation on the determination manner of the size of the stream output data. Optionally, the stream output address can be a memory address for the target memory, such as the number of a storage unit in the target memory, or can also be other forms of address data corresponding to such memory address. Optionally, the target memory can be the memory of a computing device such as a computer, and after obtaining the stream output address, the stream output module can output the stream output data to the corresponding position in the memory through a bus.

[0032] In some embodiments, the timing at which each of the stream output modules 212-1 to 212-N sends the size of the stream output data to the pipeline control module 220 can be when a complete piece of stream output data, i.e., a complete piece of processing result of the graphics input data (or inter-core interleaved data) processed by the corresponding geometry processing pipeline, is received. In other words, each of the stream output modules 212-1 to 212-N can be configured to determine and output the size of a complete piece of stream output data to the pipeline control module 220 in response to receiving the complete piece of stream output data from the corresponding geometry processing pipeline.

[0033] Exemplarily, the start and / or end of a complete piece of stream output data can be indicated by a specified string or a string generated according to a specified rule, so that the stream output module can conveniently determine and identify the start and end of a piece of stream output data by detecting such a string, and thus can determine whether a complete piece of stream output data has been received and further determine the size of the complete piece of stream output data. Alternatively, such a string can be added at at least one of the start and end of each piece of graphics input data when the graphics data to be processed is divided into multiple pieces of graphics input data, whereby the geometry processing pipeline and the stream output module can both determine the start and / or end of the corresponding data by detecting such an added string, or the geometry processing pipeline can add or update such a string at at least one of the start and end of each piece of stream output data, whereby the stream output module can determine the start and / or end of the stream output data by detecting such an added or updated string. Further exemplarily, in some embodiments, the graphics input data assigned to the corresponding graphics processing pipeline can include a tail string at the end of the data, and at this time, each of the stream output modules 212-1 to 212-N can determine and output the size of each piece of stream output data based on the stream output data received before the tail string in response to detecting the tail string when receiving each piece of stream output data. Here, detecting the tail string can refer to detecting a string consistent with a pre-specified tail string, or can also refer to detecting a string consistent with a specified rule for the tail string, etc. In addition, as mentioned above, in addition to the tail string, the graphics input data assigned to the corresponding graphics processing pipeline can also include a head string at the start of the data. The data between the head string and the tail string can be regarded as a complete piece of graphics input data, and accordingly, in the stream output data, the data between such a head string and a tail string (or an updated or adjusted string corresponding thereto) can be regarded as a complete piece of stream output data.

[0034] In some embodiments, the stream output module of each graphics processing pipeline can include a buffer in which stream output data from the corresponding geometry processing pipeline can be stored. The size of the buffer can be designed according to experience and application scenario requirements, higher than the possible size of the stream output data, or, when dividing the graphics input data, the size of the graphics input data can be controlled to be lower than the size of the storage space of the buffer after processing by the geometry processing pipeline. The stream output module can manage the data writing and reading of the buffer through two pointers. Specifically, each stream output module can maintain a first pointer and a second pointer, where the first pointer can be a write pointer indicating the position of the writable data in the buffer, and the second pointer can be a read pointer indicating the position of the readable data in the buffer. Further exemplarily, when the graphics processing system is initialized, the first pointer and the second pointer can be initialized to point to the same position in the buffer, such as a specified starting position or a random starting position. When receiving stream output data from the corresponding geometry processing pipeline, the stream output module can write the received stream output data to the buffer based on the position indicated by the first pointer, and update the first pointer based on the size of the written data, i.e. write the received stream output data to the position indicated by the first pointer in the buffer, and update the position indicated by the first pointer so that the updated first pointer indicates the next storage position after the storage area for storing stream output data in the buffer. For example, if the first pointer indicates position 0001 and the size of the received and stored stream output data is 50, the updated first pointer can indicate position 0051. When reading out and writing the stored stream output data to the target memory, the stream output module can read out the stored stream output data from the buffer based on the position indicated by the second pointer, write the read out stream output data to the target memory based on the received stream output address, and update the second pointer based on the size of the read out data, i.e. read out the stream output data from the buffer starting from the position indicated by the second pointer, write the read out stream output data to the target memory, and update the position indicated by the second pointer so that the updated second pointer indicates the next storage position after the area for storing the read out stream output data in the buffer. For example, if the second pointer indicates position 0001 and the size of the read out stream output data is 50, the updated second pointer can indicate position 0051. Optionally, the above first pointer or second pointer can be updated step by step as the stream output data is written or read step by step. During the process of reading out the stream output data, when the second pointer points to the same position as the first pointer, it can be considered that the stored stream output data has been completely read out, at which time the data reading operation can be stopped and the next stream output data can be received. Further exemplarily, when the first pointer or the second pointer reaches the tail position of the buffer, it can be returned to the head position of the buffer, thereby a circular buffer can be realized, and multiple stream output data can be flexibly continuously written and read.

[0035] The pipeline control module 220 can be configured to determine a stream output address corresponding to each stream output data based on the size of the received stream output data, and feed back the determined stream output address to the corresponding stream output module, wherein each stream output address can be determined such that each stream output data is stored in the target memory in a preset order of the corresponding graphic input data. Through the interaction between the pipeline control module and each stream output module, the stream output addresses of each stream output module can be uniformly managed, so as to ensure that each stream output data can be continuously stored in the target memory according to the preset order, thereby allowing the use of stream output function in the case of enabling multiple graphic processing pipelines, avoiding the waste of hardware resources, improving the stream output capability of the graphic processing system, and further helping to improve the overall graphic processing efficiency.

[0036] Exemplarily, the preset order of each graphic input data can be the order of each graphic input data appearing in the to-be-processed graphic data, wherein each graphic input data is obtained by dividing the to-be-processed graphic data. Thus, the preset order can reflect the order of each graphic input data, so that the stream output data can be continuously stored in the target memory according to the appearance order of the corresponding graphic input data in the to-be-processed graphic data, thereby better ensuring the continuity of the content of the stream output data. In addition, optionally, according to the requirements of specific application scenarios, the preset order can also be other types of specified order. Exemplarily, the above-mentioned preset order can be identified by a preset order identifier. For example, when dividing the graphic input data, an identifier indicating the preset order of each graphic input data can be added to each graphic input data, so that the pipeline control module 220 can determine the receiving or processing order of the data indicating the size of each stream output data through such identifier or other data corresponding to such identifier. Alternatively, the above-mentioned preset order can also be identified by a specific allocation rule of each graphic input data. For example, each portion of graphic input data can be allocated to each graphic processing pipeline in the preset order, and the order of each graphic processing pipeline allocated to the graphic input data can be specified in advance or determined according to a specified rule, so that the pipeline control module 220 can determine the receiving or processing order of the size of each stream output data based on such allocation rule, in combination with the identifier of different graphic processing pipelines, geometry processing pipelines or stream output modules.

[0037] In some embodiments, the pipeline control module 220 can determine the stream output addresses corresponding to the stream output data according to the preset order of the graphics input data corresponding to the stream output data, and feed back the determined stream output addresses to the corresponding stream output modules in sequence based on the sizes of the received stream output data. For example, the pipeline control module 220 can receive the sizes of the stream output data from the stream output modules in sequence according to the preset order of the graphics input data corresponding to the stream output data, and determine the corresponding stream output addresses based on the received sizes of the stream output data in sequence; or the pipeline control module 220 can receive the sizes of the stream output data according to the order in which the stream output modules send the sizes of the stream output data, cache the received sizes of the stream output data, and determine the corresponding stream output addresses based on the cached sizes of the stream output data based on the preset order. In the latter case, storage space is occupied in the pipeline control module 220 to store the received sizes of the stream output data, and the sizes of the stream output data should also have an identifier for determining the preset order, such as an identifier indicating the order of the corresponding graphics input data in the graphics data to be processed, or an identifier indicating the order of the corresponding graphics processing pipeline, geometry processing pipeline or stream output module, etc. In contrast, the former can avoid storage occupation in the pipeline control module 220 while ensuring that the stream output addresses are determined in order. For example, the pipeline control module 220 can maintain a current stream output address. When the graphics processing system is initialized, the current stream output address can be initialized to the starting address of the region in the target memory for writing the stream output data, or can be initialized to the starting address of the currently free region or other specified address in the target memory. According to the preset order of the graphics input data corresponding to the stream output data, for each received size of the stream output data, the pipeline control module 220 can update the current stream output address based on the sum of the address increment corresponding to the size of the stream output data and the current stream output address, and feed back the updated current stream output address to the corresponding stream output module. For further example, if the current stream output address is 0010, according to the preset order, the address increment corresponding to the size of the first stream output data is 10, and the address increment corresponding to the size of the second stream output data is 20, then the pipeline control module 220 can first add 10 to the current stream output address, update the current stream output address to 0020, and feed back the current stream output address 0020 to the stream output module providing the size of the first stream output data, then add 20 to the current stream output address, update the current stream output address to 0040, and feed back the current stream output address 0040 to the stream output module providing the size of the second stream output data. In this way, the corresponding stream output addresses can be fed back to the stream output modules providing the sizes of the stream output data.Thus, the uniform management of the stream output addresses can be conveniently realized, and the stream output data can be continuously stored in the target memory according to the expected preset order.

[0038] In some embodiments, in order to more conveniently determine the receiving or processing order of the sizes of the stream output data, and ensure that the stream output addresses can be determined according to the preset order, the graphic input data can be allocated based on the index order of the graphic processing pipelines, and the sizes of the stream output data can be received or processed based on the index order of the graphic processing pipelines. More specifically, the at least two graphic processing pipelines can have an index order, such as Figure 2 The N graphic processing pipelines shown can have an index order from 1 to N. The multiple graphic input data with the preset order can be allocated to the corresponding graphic processing pipelines in turn based on the index order. For example, the multiple graphic input data can be allocated one by one in the preset order, and the N graphic processing pipelines can receive the allocated graphic input data in turn according to the index order from 1 to N, and when the allocation is to the last graphic processing pipeline, it can return to the first graphic processing pipeline to continue the allocation. Alternatively, this allocation process can be realized by pre-computation, or it can also be realized in real time during the data transmission. In this case, when receiving the sizes of the stream output data output by the stream output modules, the pipeline control module 220 can receive the sizes of the stream output data from the stream output modules of the graphic processing pipelines in the at least two graphic processing pipelines in turn based on the index order. For example, the pipeline control module 220 can receive data from different stream output modules in the stream output modules 212-1 to 212-N through different ports. When the complete stream output data is received, each stream output module can send the size of the stream output data through the corresponding port, and the pipeline control module 220 can receive the data of each port in turn based on the above index order. When it is the turn of a certain port, but the corresponding stream output module has not sent data, the pipeline control module 220 can wait for the data of the port until the corresponding data is received, and then receive the data of the next port. When it is the turn of the last port, it can return to the first port to continue receiving data. Thus, it can be ensured by hardware that the stream output data can be written to the target memory according to the preset order.

[0039] For example, assume that the graphics processing system has two graphics processing pipelines, denoted as graphics processing pipeline 1 and graphics processing pipeline 2, where each graphics processing pipeline includes a geometry processing pipeline and a corresponding stream output module, denoted as geometry processing pipeline 1 and stream output module 1, and geometry processing pipeline 2 and stream output module 2, respectively, and that the complete graphics data to be processed is split into four graphics input data, denoted as graphics input data 1, graphics input data 2, graphics input data 3 and graphics input data 4, according to a predetermined order (order of appearance in the graphics data to be processed). If each graphics input data is assigned to a corresponding graphics processing pipeline according to the predetermined order and an index order from 1 to 2, then graphics processing pipeline 1 will be assigned to graphics input data 1 and graphics input data 3, and graphics processing pipeline 2 will be assigned to graphics input data 2 and graphics input data 4. Geometry processing pipeline 1 and geometry processing pipeline 2 can receive the graphics input data assigned to the corresponding graphics processing pipeline, respectively, where the order of receiving the graphics input data assigned to each geometry processing pipeline can be based on the predetermined order of the graphics input data. As described in the previous embodiments, stream output module 1 will receive the stream output data outputted by geometry processing pipeline 1, and stream output module 2 will receive the stream output data outputted by geometry processing pipeline 2. The received stream output data can be temporarily stored in the buffer of the stream output module, which can be implemented based on the first pointer mentioned in the previous embodiments. When a complete stream output data is received by a stream output module, it can send the size of the stream output data to the pipeline control module. The pipeline control module can receive the size of the stream output data from the two stream output modules in turn based on the index order. That is, the data can be received in the following order: data of stream output module 1, data of stream output module 2, data of stream output module 1, data of stream output module 2. After receiving each data, the pipeline control module can add the address increment data corresponding to the size of the received stream output data to the current stream output address based on the current stream output address maintained internally, update the current stream output address, and feed back the updated address data to the corresponding stream output module. After receiving the stream output address fed back by the pipeline control module, the stream output module can write the buffered stream output data to the target memory based on the address, which can be implemented based on the second pointer mentioned in the previous embodiments. After the writing is completed, the stream output module can continue to receive the stream output data from the corresponding geometry processing pipeline, and end the processing procedure if there is no subsequent data.

[0040] For example, Figure 3 An architectural diagram of a graphics processing system 300 according to some embodiments of the present disclosure is shown schematically. Similar to Figure 2 The architecture shown, in Figure 3In the illustrated architecture, there are graphics processing pipelines 310-1 to 310-N and a pipeline control module 320, where N is an integer greater than or equal to 2. Each graphics processing pipeline includes a corresponding geometry processing pipeline and a stream output module, such as geometry processing pipelines 311-1 to 311-N and stream output modules 312-1 to 312-N shown in the figure. In addition, each graphics processing pipeline can also include a corresponding fragment processing pipeline, such as fragment processing pipelines 313-1 to 313-N, each of which can take output data from the corresponding geometry processing pipeline and perform further processing, such as rasterization and other pixel-level data processing. In addition, the system 300 can also include buses 330 and 340, through which each geometry processing pipeline can receive graphics input data from, for example, an application program, and through which each stream output module can write stream output data to a target memory, such as a memory.

[0041] To further facilitate understanding, Figure 4 An example flowchart of a graphics processing process according to some embodiments of the present disclosure is schematically shown. Specifically, Figure 4 A geometry processing pipeline 410 and a stream output module 420 within a graphics processing pipeline, as well as a pipeline control module 430, are shown. It should be understood that there can be more graphics processing pipelines in practice, and the processing steps of each graphics processing pipeline can be the same or similar to those shown. As Figure 4 illustrated, the geometry processing pipeline 410 can receive graphics input data from an application program, and perform geometry processing on the graphics input data, such as vertex processing, primitive assembly, and other geometry processing. The geometry processing pipeline 410 can then output geometry processing results to the stream output module 420, which can perform stream output processing on the geometry processing results, such as tessellation, rasterization, and other stream output processing. The stream output module 420 can then output stream output data to a target memory, such as a memory. Figure 4As shown, at step S1, the geometry processing pipeline 410 can acquire graphics input data assigned to the corresponding graphics processing pipeline, at step S2, the geometry processing pipeline 410 can perform various processing operations on the acquired graphics input data, which can include one or more of vertex processing, primitive assembly, tessellation, and geometry shading processing, etc., and other optional operations, after the processing is completed, at step S3, the processed stream output result can be output to the corresponding stream output module 420. At step S4, the stream output module 420 can receive and buffer the stream output data, in response to receiving a complete stream output data, at step S5, the stream output module 420 can send the size of the received stream output data to the pipeline control module 430. At step S6, the pipeline control module 430 can sequentially receive the output from each stream output module according to, for example, the index order of the graphics processing pipeline, at step S7, the pipeline control module 430 can update the current stream output address maintained internally step by step based on the size of the received stream output data, and feed back the current stream output address after each update to the corresponding stream output module. At step S8, after receiving the stream output address from the pipeline control module 430, at step S9, the stream output module 420 can write the buffered stream output data to the target memory according to the received address, such as writing to the memory via the bus. Subsequently, the stream output module 420 can continue to receive the output data of the geometry processing pipeline 410, and if not, the current processing flow can be ended.

[0042] The present disclosure also proposes a graphics processor, illustratively, Figure 5 An example block diagram of a graphics processor 500 according to some embodiments of the present disclosure is shown. As Figure 5 shown, the graphics processor 500 can include a graphics processing system 510. The graphics processing system 510 is the same as or similar to Figure 2 or Figure 3 the graphics processing system 200 or 300 described above and has reference to Figure 2 or Figure 3 various embodiments described above. Illustratively, the graphics processor 500 can be implemented as a chip or other form of device.

[0043] The present disclosure also proposes a computing device, illustratively, Figure 6 An example block diagram of a computing device 600 according to some embodiments of the present disclosure is shown. As Figure 6 shown, the computing device 600 can include Figure 5The illustrated graphics processor 500. Illustratively, the computing device referred to in the present disclosure can refer to a desktop computer, a notebook computer, a tablet computer, a smartphone, a workstation, a game console, or other types of computing devices. The graphics processor described above can perform various operations related to images and graphics and the like in such computing devices.

[0044] It should be understood that the embodiments of the present disclosure have been described with reference to different functional units. The functions of each functional unit can be implemented in a single unit, in multiple units, or as part of other functional units without deviating from the present disclosure. For example, functions described as being performed by a single unit can be performed by multiple different units. Therefore, the specific functional units referred to in the present disclosure should only be regarded as a reference to an appropriate unit for providing the described functions, rather than indicating a strict logical or physical structure or organization.

[0045] It should also be understood that, although various devices, elements, components or parts are described in the present disclosure by first, second, third, etc. terms, these devices, elements, components or parts should not be limited by these terms. These terms are only used to distinguish one device, element, component or part from another device, element, component or part. In addition, in the present disclosure, the term "and / or" and similar terms include all combinations of any one, multiple and all of the associated listed items.

[0046] Variations to the disclosed embodiments can become apparent to those of ordinary skill in the art from the foregoing description and accompanying claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The mere fact that measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A graphics processing system, characterized in that: The graphics processing system includes at least two graphics processing pipelines and a pipeline control module. Each of the at least two graphics processing pipelines includes: The geometry processing pipeline is configured to: receive graphics input data assigned to the corresponding graphics processing pipeline, and generate and output stream output data corresponding to the received graphics input data; a stream output module configured to: receive stream output data from the corresponding geometry processing pipeline, output the size of the received stream output data to the pipeline control module, and receive a stream output address from the pipeline control module and write the received stream output data to a target memory based on the received stream output address; The pipeline control module is configured to determine a stream output address corresponding to each stream output data based on the size of each received stream output data, and feed the determined stream output address back to the corresponding stream output module, wherein each stream output address is determined so that each stream output data is stored in the target memory in a preset order of the corresponding graphics input data. The stream output module of each graphics processing pipeline includes a cache for storing stream output data from the corresponding geometry processing pipeline. Wherein, the stream output module is further configured to: Writing the received stream output data into the cache based on the position indicated by the first pointer, and updating the first pointer based on the size of the written data; Based on the position indicated by the second pointer, the stored stream output data is read from the cache, the read stream output data is written to the target memory based on the received stream output address, and the second pointer is updated based on the size of the read data. The first pointer and the second pointer are initialized to point to the same position in the cache when the graphics processing system is initialized.

2. The graphics processing system according to claim 1, wherein: The pipeline control module is further configured to: receiving the size of the stream output data from each stream output module in sequence according to the preset order of the graphic input data corresponding to each stream output data; For each size of received stream output data, the current stream output address is updated based on the sum of the address increment corresponding to the size of the stream output data and the current stream output address, and the updated current stream output address is fed back to the corresponding stream output module.

3. The graphics processing system according to claim 2, wherein: The at least two graphics processing pipelines have an index sequence, and the plurality of graphics input data having the preset order are sequentially allocated to the corresponding graphics processing pipelines based on the index sequence, and, The pipeline control module is further configured to: sequentially receive the size of the stream output data from the stream output module of each of the at least two graphics processing pipelines based on the index sequence.

4. The graphics processing system according to claim 1, wherein: The stream output module is further configured to: In response to receiving a complete portion of stream output data from a corresponding geometry processing pipeline, a size of the complete portion of stream output data is determined and output to the pipeline control module.

5. The graphics processing system according to claim 4, wherein: The graphics input data distributed to the corresponding graphics processing pipeline includes a tail string at the end of the data. The stream output module is further configured to: when receiving each portion of stream output data, in response to detecting the tail string, determine and output the size of the portion of stream output data based on the stream output data received before the tail string.

6. The graphics processing system according to any one of claims 1 to 5, wherein: The at least two graphics processing pipelines are configured to process graphics input data distributed to the respective graphics processing pipelines in parallel.

7. The graphics processing system according to any one of claims 1 to 5, wherein: The graphics input data distributed to each graphics processing pipeline is obtained by dividing the graphics data to be processed, and the preset order of the graphics input data is the order in which the graphics input data appear in the graphics data to be processed.

8. A graphics processor, characterized in that: The graphics processor comprises a graphics processing system according to any one of claims 1-7.

9. A computing device, characterized in that The computing device includes the graphics processor of claim 8.

Images