Digital circuit experiment system and method, computer equipment and storage medium

Abstract

The invention provides a digital circuit experiment system and method, which replace and cover a basic design experiment link and a verification experiment link of a traditional digital circuit experiment, can avoid a debugging link, strengthen an experiment gravity center, improve experiment teaching efficiency and reduce invalid consumption of experiment time resources. The interference of verification circuit debugging on experiment performance evaluation is reduced, the fairness and objectivity of experiment ability evaluation of an experimenter in experiment teaching are enhanced, the experimenter can be prevented from calculating experiment results through theoretical knowledge to submit the experiment results, the experimenter can be prevented from submitting the experiment results by copying the experiment results of other people, experiment cheating behaviors are effectively prevented, and the experiment efficiency is improved. The design emphasis in the basic design experiment is improved from multiple angles, the FPGA design environment is transparent in the digital circuit experiment process, the acceptance efficiency of the experiment result of an experiment teacher can be improved, acceptance resource extrusion under the high student-teacher ratio is avoided, and the teaching burden of the experiment teacher is relieved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuit experiments, and in particular to a digital circuit experiment system and method, computer equipment, and storage medium. Background Art

[0002] At present, the conventional teaching mode of digital circuit experiment includes three steps, namely verification experiment, basic design experiment and comprehensive design experiment. Figure 1 shown.

[0003] Verification experiment is the most basic step in experimental teaching that takes the target chip or a basic functional circuit as the research object. The conventional practice is that the teacher designs the circuit schematic, test requirements, test methods and other experimental related content in advance, and publishes them to the experimenters through textbooks, PPT and other text materials. The experimenters connect the circuits according to the schematics, and record the experimental process data and experimental result data such as waveforms and test parameters after the circuit functions normally, and then analyze them and verify them with the theoretical knowledge.

[0004] The basic design experiment is an enhanced experimental teaching step that takes the target chip or a basic functional circuit as the research object. The general practice is that the teacher creates an experimental task for the research object: requiring the experimenter to design a simple circuit with a specified function, such as using logic gates to design a three-person voting circuit, monostable to achieve signal delay, etc., which is often highly correlated with the verification experimental circuit to ensure that newcomers have a step-by-step process; experimental tasks and specific design indicators are also released through textbooks, PPT, etc. In terms of the specific experimental process, the basic design experiment has a high degree of similarity with the verification experiment, except that the experimenter needs to design and draw the schematic diagram. The goal of the basic design experiment is for the experimenter to make the research object move through independent design and prepare for the comprehensive design experiment.

[0005] The experimental focus of the basic design experiment is on the design, application and realization of the target chip or a basic functional circuit. The goal of the design task is generally limited to the target chip and a small number of connections, and often does not include components such as buttons and LED displays to increase the success rate of circuit building. The third step of experimental teaching is to set up some comprehensive design experimental tasks that are valuable, large-scale, interesting, demonstrative, technically continuous, and fulfilling, based on multiple basic design experimental objects, buttons, LEDs and other components. The goal of the comprehensive design experiment is to promote the experimenter to master the design ideas of the system circuit and improve the comprehensive debugging ability of the circuit.

[0006] The circuit debugging of the verification experiment and the circuit debugging of the basic design experiment are repetitive settings during the experiment, which causes a waste of resources in the experimental course with tight class hours. However, in the traditional experimental mode, the debugging of the verification circuit cannot be avoided, and the debugging process during the circuit test is very random, which is very unfriendly to the experimenter. Some experimenters can work normally after connecting to the line, and some experimenters have not solved the problem after debugging for a whole class, thus delaying the experimenter's learning of subsequent experimental test technology and verification of the logical function of the experimental device. Moreover, the debugging time has nothing to do with the experimenter's learning seriousness, which interferes with the evaluation of the experimenter's experimental performance to a certain extent. In addition, since the verification experiment tasks are uniformly released through textbooks or PPTs, some experimenters will analyze the experimental results through theoretical knowledge and submit the theoretical analysis results as experimental test results. Some experimenters will also copy the experimental results from other experimenters and submit them as their own experimental results.

[0007] The acceptance of experimental results after the experiment is completed is not only the acceptance of data on paper, but also includes the acceptance of standardized measurement operations of equipment such as multimeters and oscilloscopes. The acceptance process is time-consuming and labor-intensive, and because the experimenters' completion time is close, it will cause a squeeze on teachers' acceptance resources and affect the objective evaluation of experimental results.

[0008] Therefore, it is necessary to provide a new method to solve the above technical problems. Summary of the invention

[0009] In order to achieve the above-mentioned purpose and other advantages of the present invention, the first purpose of the present invention is to provide a digital circuit experiment system, including a server, a local information processing device, an all-in-one data module, an interface module, and an acceptance automation module; wherein,

[0010] The server is used to store black box circuit files and their test case files, experimenter information, generate and store associations between the experimenter and the black box circuit files and the test case files, receive logic function analysis results uploaded by the experimenter and determine the correctness, receive information uploaded by the acceptance automation module, and export experiment information related to the experimenter in response to a teacher's request;

[0011] The local information processing device is used to implement the black box circuit file extracted by the experimenter on the experimental board, determine the timing of the experimenter drawing the design schematic diagram in the standardized template file according to the judgment result of the server and generate the VHDL code of the drawn schematic diagram, call the generation automation program to compile the comprehensive embodiment to generate the code stream file and configure the experimental board;

[0012] The interface module is used to connect the all-in-one data module and the experimental board to form a test closed loop;

[0013] The acceptance automation module is used to download the corresponding test case file according to the experimenter information, send the input signal to the experimental board through the interface module through the signal source part of the all-in-one data module, and collect the output signal of the experimental board through the signal acquisition part of the all-in-one data module, compare the collected output signal with the output signal in the test case file for consistency, and upload corresponding information to the server according to the comparison result.

[0014] Furthermore, the server database also stores circuit file information, including file name and related attributes. The file name points to the black box circuit file and the test case file. The server database also stores exercises and answers corresponding to each file and the ownership relationship of the files.

[0015] Furthermore, the ownership relationship of the file includes the experimental project to which the file belongs, and the experimental course to which the experimental project belongs.

[0016] Furthermore, the black box circuit file and the test case file are configured to be generated in batches through an FPGA environment and a script.

[0017] Furthermore, the black box circuit file is stored in the server in the form of a code stream file, and the test case file is stored in the server in the form of a text file.

[0018] Furthermore, the test cases include 0, 1, and half-width commas. The number of characters in each line is the same and they are separated by commas. The data before the comma is defined as the input signal and the data after the comma is defined as the output signal. Each line of data is a time slice sampling data.

[0019] Furthermore, the interface module is configured as a planned interface strip, and the pin sequence of the interface strip is predefined.

[0020] Furthermore, the acceptance automation module uses a window-shifting verification method to compare the collected experimental result data sequence with the test case for consistency, and the length of the experimental result data sequence is a multiple of the length of the test case; if the acceptance passes, the pass information is uploaded to the server, if the acceptance fails, the collected experimental result data sequence is uploaded to the server.

[0021] A second object of the present invention is to provide a digital circuit experiment method, which is applied to the above-mentioned server and comprises the following steps:

[0022] Receive black box circuit files, test case files and file information edited by teachers;

[0023] In response to a teacher's request to create an experimental project or an experimental course, an experimental project or an experimental course is created, and an attribution relationship between the black box circuit file, the test case file, the experimental project, and the experimental course is established;

[0024] importing the experimenter information in response to a request to import the experimenter information;

[0025] After the course is arranged, an association relationship is established between the experimenter information and the black box circuit file and the test case file;

[0026] Receive the logic function analysis results uploaded by the experimenter and determine the correctness of the logic function analysis results;

[0027] Receive information uploaded by the acceptance automation module;

[0028] In response to a teacher's request to export the experimental information, the experimental information related to the experimenter is exported.

[0029] Furthermore, the method further comprises the steps of:

[0030] In response to the experimenter's request to extract the black box circuit file, the black box circuit file is extracted in a random manner and transmitted to a local information processing device used by the experimenter.

[0031] Furthermore, the step of determining the correctness of the logic function analysis result includes:

[0032] If the verification is determined to be successful, a control signal is sent to enable the local information processing device to allow the experimenter to draw a design schematic diagram in a standardized template file.

[0033] A third object of the present invention is to provide a digital circuit experiment method, which is applied to the above-mentioned local information processing device and comprises the following steps:

[0034] Download the black box circuit file corresponding to the experimenter;

[0035] Implement the black box circuit file on a test board;

[0036] Upload the logic function analysis results to the server;

[0037] Determine the timing for the experimenter to draw the design schematic diagram in the standardized template file according to the judgment result of the server and generate the VHDL code of the drawn schematic diagram;

[0038] Call the generation automation program to compile and synthesize the generated code stream file and configure the experimental board.

[0039] Furthermore, the step of determining the timing for the experimenter to draw the design schematic diagram in the standardized template file according to the judgment result of the server includes:

[0040] If the server determines that the verification is successful, it allows the experimenter to draw a design schematic diagram in the standardized template file.

[0041] A fourth object of the present invention is to provide a digital circuit experiment method, which is applied to the above-mentioned acceptance automation module and comprises the following steps:

[0042] Download the corresponding test case file according to the experimenter information;

[0043] The input signal is sent to the experiment board through the interface module via the signal source part of the all-in-one data module;

[0044] Collecting the output signal of the experimental board through the signal acquisition part of the all-in-one data module;

[0045] Compare the collected output signal with the output signal in the test case file for consistency;

[0046] Upload the corresponding information to the server based on the comparison results.

[0047] Furthermore, the step of comparing the collected output signal with the output signal in the test case file for consistency includes:

[0048] The collected experimental result data sequence is compared with the test case for consistency using the window-shifting verification method.

[0049] Furthermore, the step of uploading corresponding information to the server according to the comparison result includes:

[0050] If the acceptance is passed, the passing information is uploaded to the server;

[0051] If the acceptance fails, the collected experimental result data sequence is uploaded to the server.

[0052] A fifth object of the present invention is to provide a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0053] A sixth object of the present invention is to provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0054] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0055] The present invention provides a digital circuit experiment system and method, which replaces and covers the basic design experiment link and verification experiment link of the traditional digital circuit experiment, can avoid the debugging link, strengthen the experiment focus, improve the experimental teaching efficiency, reduce the ineffective consumption of experimental time resources, reduce the interference of verification circuit debugging on the experimental performance evaluation, enhance the fairness and objectivity of the experimental ability evaluation of the experimenter in the experimental teaching, can avoid the experimenter submitting the experimental result by calculating the experimental result through theoretical knowledge, can avoid the experimenter submitting the experimental result by copying other people's experimental results, effectively prevent the experimental cheating behavior, realize the improvement of the design emphasis in the basic design experiment from multiple angles, make the FPGA design environment transparent in the digital circuit experiment process, can improve the experimental result acceptance efficiency of the experimental teacher, avoid the acceptance resource squeeze under the high "student-teacher ratio", and reduce the teaching burden of the experimental teacher.

[0056] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. The specific implementation of the present invention is given in detail by the following embodiments and their accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0058] Figure 1 This is a schematic diagram of the conventional mode of digital circuit experimental teaching;

[0059] Figure 2 This is the schematic diagram of the digital circuit experimental system;

[0060] Figure 3 Schematic diagram of a comprehensive programmable experimental board based on FPGA Figure 1 ;

[0061] Figure 4 Schematic diagram of a comprehensive programmable experimental board based on FPGA Figure 2 ;

[0062] Figure 5 Server management flow chart from the teacher's perspective;

[0063] Figure 6 To accept the automation module system block diagram;

[0064] Figure 7 It is a schematic diagram of the interface of the standardized template file of the combinational logic;

[0065] Figure 8 This is a schematic diagram of sequential logic window shifting verification;

[0066] Fig. 9 This is the black box experiment platform operation flow chart from the experimenter's perspective;

[0067] Fig.10 Experimental method flow for digital circuits Figure 1 ;

[0068] Fig.11 Experimental method flow for digital circuits Figure 2 ;

[0069] Fig.12 Experimental method flow for digital circuits Figure 3 ;

[0070] Fig.13 It is a schematic diagram of computer equipment;

[0071] Fig.14 A schematic diagram of a computer-readable storage medium. DETAILED DESCRIPTION

[0072] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0073] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work shall fall within the scope of protection of the present invention.

[0074] The figure numbers in this application are only used to distinguish the various steps in the scheme, and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0076] Example 1

[0077] A digital circuit experiment system replaces the verification experiment link and basic design experiment link of the traditional digital circuit experiment, and can complete the basic design acceptance of all digital logic classes, such as Figure 2 As shown, the system includes a server 1, a local information processing device 2, an all-in-one data module 3, an interface module 4, and an acceptance automation module 5; wherein,

[0078] The server is used to store black box circuit files and their test case files, experimenter information, generate and store the association relationship between the experimenter and the black box circuit files and the test case files, that is, there is an allocation relationship between the student and the circuit, receive the logic function analysis results uploaded by the experimenter and judge the correctness, receive the information uploaded by the acceptance automation module, and export the experiment information related to the experimenter in response to the teacher's request;

[0079] The local information processing device is used to implement the black box circuit file extracted by the experimenter on the experimental board, determine the timing for the experimenter to draw the design schematic in the standardized template file according to the judgment result of the server and generate the VHDL code of the drawn schematic, call the generation automation program to compile the comprehensive embodiment to generate the code stream file and configure the experimental board; optionally, the local information processing device is configured as a local computer.

[0080] The interface module is used to connect the all-in-one data module and the experimental board to form a test closed loop;

[0081] The acceptance automation module is used to download the corresponding test case file according to the experimenter information, send the input signal to the experimental board through the interface module through the signal source part of the all-in-one data module, and collect the output signal of the experimental board through the signal acquisition part of the all-in-one data module, compare the collected output signal with the output signal in the test case file for consistency, and upload corresponding information to the server according to the comparison result.

[0082] In some embodiments, the server database also stores circuit file information, including circuit test guidance information such as file name, related attributes, and port definition. The file name points to the black box circuit file and the test case file. The server database also stores the exercises and answers corresponding to each file, and the file ownership relationship.

[0083] Set up a number of exercises for each file to automatically determine whether the experimenter's test results are correct or not.

[0084] Optionally, the relevant attributes include difficulty level, label and other attributes.

[0085] Furthermore, the ownership relationship of the file includes the experimental project to which the file belongs, and the experimental course to which the experimental project belongs.

[0086] Specifically, all circuit files of the same experimental project belong to the experimental project, and a series of experimental projects that complete a course belong to the course.

[0087] In some embodiments, the black box circuit file and the test case file are configured to be generated in batches through an FPGA environment and a script.

[0088] FPGA stands for Field Programmable Gate Array, which is a programmable digital circuit device. It can be reconfigured to obtain different circuit functions by configuring different code stream files through download line programming. The circuit units and wiring are all inside the FPGA device, and the specific circuit structure cannot be known through external observation. Therefore, without providing a schematic diagram or HDL code, the FPGA circuit can be regarded as a black box circuit.

[0089] In experimental teaching, a comprehensive programmable experimental board based on FPGA is used as the hardware platform. The programmable experimental board is usually equipped with a certain number of switches, LEDs, and external resources such as power strips that can be used for expansion, which are connected to the IO ports specified by the FPGA chip. For a certain experimental project, the black box circuit adopts a unified input and output terminal setting, which is announced through PPT, black box file descriptions on the platform website, etc. The set input and output terminals can be selected according to the experimental teaching plan, such as switches, LEDs, and power strips. Figure 3 , Figure 4 shown.

[0090] Furthermore, the black box circuit file is stored in the server in the form of a code stream file; in this embodiment, the test sample is stored in the server in the form of a file, and the file structure can be set very simply. Preferably, the test case file is stored in the server in the form of a text file.

[0091] Taking combinatorial logic analysis as an example, the batch generation process of black box circuit files is as follows: Since the truth table of a 3-input logic function has 8 rows, there are 256 3-input logic function expressions. Delete a few logic expressions such as all 1s and all 0s in the truth table, and assign the remaining logic expressions in groups of 3 to form 84 3-input 3-output logic expression groups listed in HDL. Each group has a group number, and the case generation block is used to determine which group of logic expressions is synthesized by the group number.

[0092] The Python script loops from 1 to 84, uses the replacement statement to change the case group number in the HDL code file, calls the TCL statement, and batch generates 84 3-input 3-output combinational logic circuits. Each circuit file is set with a file number, which is displayed on the digital tube when the black box file configures the FPGA, providing teachers with certain prediction information about the black box circuit function.

[0093] Furthermore, the test cases only include three characters: "0", "1", and half-width commas. The number of characters in each line is the same, separated by a comma. The data before the comma is defined as the input signal, and the data after the comma is defined as the output signal. Each line of data is a time slice sampling data. If the sample data is matrix transposed, it can be regarded as a set of input and output waveforms. Due to the needs of the black box experimental platform, there are a large number of test samples of different black box circuits. Batch test samples are obtained by calling the FPGA software design environment TCL script through Python script to run the simulation code.

[0094] Taking the combinational logic circuit as an example, the batch generation process of the test case file is as follows: create simulation HDL code, which mainly includes the combinational logic circuit instantiation code, simulation timing description, and input and output logic file saving statements. The content of the test case file after the simulation is as follows, with the input signal before the comma and the output signal after the comma, and the signal name is fixed.

[0095] 000,111

[0096] 001,000

[0097] 010,001

[0098] 011,111

[0099] 100,010

[0100] 101,111

[0101] 110,111

[0102] 111,100

[0103] Test case file series are also generated in batches via Python.

[0104] The server management process from the teacher's perspective is as follows Figure 5As shown in the figure, the teacher generates black-box circuit files (code stream files) and test case files in batches through the FPGA environment and scripts, uploads them to the server (can be uploaded in batches), and edits the circuit file information and the exercises exclusive to each circuit file. The editing of circuit file information and exercises can be done in batches by importing excel files. After the file information is edited, an experimental project is created for each experimental project unit, and the relevant black-box circuits are summarized in the experimental project. Since several experimental projects belong to one experimental course, it is also necessary to establish an experimental course. The relationship between experimental courses and experimental projects is 1:n, and the relationship between experimental projects and black-box circuits is also 1:n. The experimental courses, experimental projects, and black-box circuits are hierarchically constructed into a 1:n tree network structure. Before arranging courses, it is necessary to ensure that the information of all experimenters has been imported, including student numbers, names, and classes. After the course is arranged, the experimenters indirectly establish a relationship with the black-box circuits through experimental courses and experimental projects. When the experimenters complete the experiment and upload the experimental data, the teacher can export the experimental data for scoring and assessment.

[0105] In order to solve the problem of acceptance resource squeeze under the 1:30 teacher-student ratio and further improve acceptance efficiency, a laboratory is equipped with 3-4 sets of acceptance automation equipment at the same time, and the experimenters can complete the acceptance operations by themselves without the intervention of teachers.

[0106] like Figure 6 As shown in the figure, during the acceptance process, the experimenter only needs to do three things: connect the all-in-one data module box and the FPGA experiment board through two sets of interface strips to form a test closed loop; log in your student number on the acceptance automation software on the local computer; click acceptance and observe the acceptance feedback information. An experimenter can complete the acceptance in no more than 1 minute.

[0107] Due to the need for automated acceptance, the connection between the all-in-one data module and the experimental circuit must be in a specified format and strictly implemented, otherwise the automated acceptance will fail. Ensuring the correct connection requires the collaboration of both software and hardware. The hardware needs to define the order of the socket pins, which cannot be wrong. Furthermore, the interface module is configured as a planned interface socket, and the pin order of the interface socket is predefined; the software needs to design the circuit as a standardized input and output port, so it is necessary to pre-compile a standardized template file for the interface of the circuit to be tested.

[0108] The interface of the standardized template file for combinational logic is as follows Figure 7As shown. In order to ensure that the experimenter can easily verify the circuit implementation by himself during the design process and can quickly perform automated acceptance, JA0~JA2 in the figure are input socket interface terminals, JB0~JB2 are output socket interface terminals, which are used during automated acceptance, SW0~SW2 are dip switches, and LED0~LED2 are light-emitting diodes, which are used when the experimenter designs and debugs. The switch between acceptance and debugging is controlled by the dip switch SW15 controlling three two-to-one data selectors. The experimenter only needs to draw a valid schematic in the design area, and after the background FPGA process operation, it can be manually verified on the experimental board, or quickly verified on the automated acceptance equipment.

[0109] Although some of the existing basic design experiment tasks are based on the FPGA platform and use FPGA for digital circuit experimental design learning, no matter the editing code type or the schematic diagram type design, the software environment provided by the FPGA manufacturer is usually used to complete the generation process from source code to code stream file, as well as the configuration of FPGA hardware operations. Therefore, the experimenter needs to master a series of complex usage processes of the manufacturer's software including configuration pins. This process will bias the experimenter's attention to the use of the software environment within the limited experimental class time, affecting the achievement of experimental teaching objectives. The present invention improves the design emphasis in the basic design experiment from multiple angles, makes the FPGA design environment transparent in the digital circuit experiment process, strengthens the experimental focus, and improves the efficiency of experimental teaching.

[0110] After the experimenter logs in with his / her student ID, the acceptance automation program will log in to the server and download the corresponding test case file for the experimenter according to his / her student ID. The signal source part of the all-in-one module sends the input signal to the FPGA experiment board through the interface strip at a certain frequency, and simultaneously receives the output signal of the FPGA experiment board through the signal acquisition part of the all-in-one module, and compares the consistency with the output signal in the test sample. If the comparison is successful, the "pass" information is uploaded to the server. If the comparison is unsuccessful, the collected experimental result data sequence is uploaded. Based on compatibility considerations, the data sequence length of the collected experimental circuit is 1.5 to 2 times the test case length, and the window shifting verification method is adopted.

[0111] Furthermore, the acceptance automation module uses a window shifting verification method to compare the collected experimental result data sequence with the test case for consistency; the length of the experimental result data sequence is a multiple of the test case length, for example, the length of the data sequence of the collected experimental circuit is 1.5 to 2 times the test case length; if the acceptance passes, the pass information is uploaded to the server, if the acceptance fails, the collected experimental result data sequence is uploaded to the server.

[0112] When testing sequential logic circuits, such as counters, there may be a "pre-start state", so the sequential logic verification process needs to adopt a "moving window verification method", such as Figure 8 As shown: together with the input and output, collect data of 1.5 to 2 times the length of the test case, take the data fragments with the same length as the test case signal sequence in the collected signal of the tested circuit and compare them one by one. If the comparison fails ( Figure 8 The window moves backward until the comparison is successful ( Figure 8 The thick dashed line frame in the upper middle part and the lower dashed line frame), or until all the acquisition signal sequences of the circuit under test are compared.

[0113] The operation process of the black box experiment platform from the experimenter's perspective is as follows Fig. 9 As shown in the figure, the experimenter logs in to the server, randomly extracts a black box circuit file and downloads it to the local computer; the black box circuit is implemented on the FPGA experimental board through the FPGA configuration software installed on the local computer; the experimenter uses experimental equipment including multimeters and oscilloscopes to test according to standardized experimental operation techniques, and records experimental data and analyzes logical functions; the analyzed logical functions are uploaded to the server, and the server automatically determines whether the analysis results are correct or not.

[0114] After the experimenter uploads the conclusion and passes it, he / she starts to draw the design schematic in the Multisim standardized template file released by the teacher; after the schematic is drawn, VHDL code is generated through the export function of Multisim; the generation automation program specially compiled for the black box experiment system is called to implement the entire process of compiling and synthesizing the generated code stream file and configuring the FPGA experiment board. The pin definition is pre-configured and no operation is required by the experimenter. The FPGA software environment is transparent during the experiment; the experimenter uses multimeters, oscilloscopes and other equipment to conduct independent inspections of the designed circuit. After confirming that the design is correct, he / she goes to the acceptance automation equipment for independent acceptance. If the acceptance is passed, the passed information is uploaded. If the upload fails, the corresponding failure record is registered.

[0115] The present invention provides a digital circuit experiment system, which replaces and covers the basic design experiment link and the verification experiment link of the traditional digital circuit experiment, can avoid the debugging link, strengthen the experiment focus, improve the experimental teaching efficiency, reduce the ineffective consumption of experimental time resources, reduce the interference of the verification circuit debugging on the experimental performance evaluation, enhance the fairness and objectivity of the experimental ability evaluation of the experimenter in the experimental teaching, can avoid the experimenter submitting the experimental result by calculating the experimental result through theoretical knowledge, can avoid the experimenter submitting the experimental result by copying other people's experimental results, effectively prevent the experimental cheating behavior, realize the improvement of the design emphasis in the basic design experiment from multiple angles, make the FPGA design environment transparent in the digital circuit experiment process, can improve the experimental result acceptance efficiency of the experimental teacher, avoid the acceptance resource squeeze under the high "student-teacher ratio", and reduce the teaching burden of the experimental teacher.

[0116] Example 2

[0117] A digital circuit experiment method is applied to the above-mentioned server. For a detailed description of the server, reference can be made to the corresponding description in the above-mentioned digital circuit experiment system embodiment, which will not be repeated here.

[0118] like Fig.10 As shown, the method comprises the following steps:

[0119] S100, receiving the black box circuit file uploaded by the teacher, the test case file and the file information edited by the teacher, and the exercises and answers corresponding to each file;

[0120] The server management process from the teacher's perspective is as follows Figure 5 As shown in the figure, the teacher generates black box circuit files (code stream files) and test case files in batches through the FPGA environment and scripts, uploads them to the server (can be uploaded in batches), and edits the circuit file information and the exercises exclusive to each circuit file. The editing of circuit file information and exercises can be done in batches by importing Excel files. The server receives the black box circuit files, test case files uploaded by the teacher, and the file information edited by the teacher.

[0121] Optionally, the circuit file information includes circuit test guidance information such as a file name, related attributes, and port definitions, and the file name points to the black box circuit file and the test case file.

[0122] Set up a number of exercises for each file to automatically determine whether the experimenter's test results are correct or not.

[0123] Optionally, the relevant attributes include difficulty level, label and other attributes.

[0124] In some embodiments, the black box circuit file and the test case file are configured to be generated in batches through an FPGA environment and a script.

[0125] FPGA stands for Field Programmable Gate Array, which is a programmable digital circuit device. It can be reconfigured to obtain different circuit functions by configuring different code stream files through download line programming. The circuit units and wiring are all inside the FPGA device, and the specific circuit structure cannot be known through external observation. Therefore, without providing a schematic diagram or HDL code, the FPGA circuit can be regarded as a black box circuit.

[0126] In experimental teaching, a comprehensive programmable experimental board based on FPGA is used as the hardware platform. The programmable experimental board is usually equipped with a certain number of switches, LEDs, and external resources such as power strips that can be used for expansion, which are connected to the IO ports specified by the FPGA chip. For a certain experimental project, the black box circuit adopts a unified input and output terminal setting, which is announced through PPT, black box file descriptions on the platform website, etc. The set input and output terminals can be selected according to the experimental teaching plan, such as switches, LEDs, and power strips. Figure 3 , Figure 4 shown.

[0127] Furthermore, the black box circuit file is stored in the server in the form of a code stream file; in this embodiment, the test sample is stored in the server in the form of a file, and the file structure can be set very simply. Preferably, the test case file is stored in the server in the form of a text file.

[0128] Taking combinatorial logic analysis as an example, the batch generation process of black box circuit files is as follows: Since the truth table of a 3-input logic function has 8 rows, there are 256 3-input logic function expressions. Delete a few logic expressions such as all 1s and all 0s in the truth table, and assign the remaining logic expressions in groups of 3 to form 84 3-input 3-output logic expression groups listed in HDL. Each group has a group number, and the case generation block is used to determine which group of logic expressions is synthesized by the group number.

[0129] The Python script loops from 1 to 84, uses the replacement statement to change the case group number in the HDL code file, calls the TCL statement, and batch generates 84 3-input 3-output combinational logic circuits. Each circuit file is set with a file number, which is displayed on the digital tube when the black box file configures the FPGA, providing teachers with certain prediction information about the black box circuit function.

[0130] Furthermore, the test cases only include three characters: "0", "1", and half-width commas. The number of characters in each line is the same, separated by a comma. The data before the comma is defined as the input signal, and the data after the comma is defined as the output signal. Each line of data is a time slice sampling data. If the sample data is matrix transposed, it can be regarded as a set of input and output waveforms. Due to the needs of the black box experimental platform, there are a large number of test samples of different black box circuits. Batch test samples are obtained by calling the FPGA software design environment TCL script through Python script to run the simulation code.

[0131] Taking the combinational logic circuit as an example, the batch generation process of the test case file is as follows: create simulation HDL code, which mainly includes the combinational logic circuit instantiation code, simulation timing description, and input and output logic file saving statements. The content of the test case file after the simulation is as follows, with the input signal before the comma and the output signal after the comma, and the signal name is fixed.

[0132] 000,111

[0133] 001,000

[0134] 010,001

[0135] 011,111

[0136] 100,010

[0137] 101,111

[0138] 110,111

[0139] 111,100

[0140] Test case file series are also generated in batches via Python.

[0141] S101, creating an experimental project and an experimental course in response to a teacher's request to create an experimental project and an experimental course, and establishing an attribution relationship between the black box circuit file, the test case file, and the experimental project and the experimental course;

[0142] Furthermore, the attribution relationship includes the experimental project to which the file belongs, and the experimental course to which the experimental project belongs.

[0143] Specifically, all circuit files of the same experimental project belong to the experimental project, and a series of experimental projects that complete a course belong to the course.

[0144] like Figure 5 As shown in the figure, after the file information is edited, the teacher creates an experimental project for each experimental project unit and classifies the relevant black box circuits into the experimental project; since several experimental projects belong to one experimental course, an experimental course needs to be established; the relationship between the experimental course and the experimental project is 1:n, and the relationship between the experimental project and the black box circuit is also 1:n. The experimental courses, experimental projects, and black box circuits are hierarchically constructed into a 1:n tree network structure.

[0145] S102, importing the experimenter information in response to a request for importing the experimenter information;

[0146] like Figure 5 As shown, before arranging the courses, it is necessary to ensure that the information of all experimenters has been imported, including student number, name and class; after the courses are arranged, the experimenters indirectly establish a relationship with the black box circuit through experimental courses and experimental projects.

[0147] S103, after the course is arranged, establishing an association relationship between the experimenter information and the black box circuit file and the test case file;

[0148] In some embodiments, the steps include:

[0149] In response to the experimenter's request to extract the black box circuit file, the black box circuit file is extracted in a random manner and transmitted to a local information processing device used by the experimenter.

[0150] After the black box circuit file extracted by the experimenter is determined, an association relationship between the experimenter information and the black box circuit file and the test case file can be established.

[0151] S104, receiving the logic function analysis result uploaded by the experimenter and judging the correctness of the logic function analysis result;

[0152] The operation process of the black box experiment platform from the experimenter's perspective is as follows Fig. 9 As shown in the figure, the experimenter logs in to the server, randomly extracts a black box circuit file and downloads it to the local computer; the black box circuit is implemented on the FPGA experimental board through the FPGA configuration software installed on the local computer; the experimenter uses experimental equipment including multimeters and oscilloscopes to test according to standardized experimental operation techniques, and records experimental data and analyzes logical functions; the analyzed logical functions are uploaded to the server, and the server automatically determines whether the analysis results are correct or not.

[0153] Furthermore, the step of determining the correctness of the logic function analysis result includes:

[0154] If the verification is determined to be successful, a control signal is sent to enable the local information processing device to allow the experimenter to draw a design schematic diagram in a standardized template file.

[0155] like Fig. 9 As shown in the figure, when the experimenter uploads the conclusion and passes it, he starts to draw the design schematic in the Multisim standardized template file released by the teacher; after the schematic is drawn, VHDL code is generated through the export function of Multisim; the generation automation program specially compiled for the black box experiment system is called to implement the entire process of compiling and synthesizing the generated code stream file and configuring the FPGA experiment board. The pin definition is pre-configured and no operation is required by the experimenter. The FPGA software environment is transparent during the experiment; the experimenter uses multimeters, oscilloscopes and other equipment to conduct independent inspections of the designed circuit. After confirming that the design is correct, he goes to the acceptance automation equipment for independent acceptance. If the acceptance is passed, the passed information is uploaded. If the upload fails, the corresponding failure record is registered.

[0156] S105, receiving information uploaded by the acceptance automation module;

[0157] Specifically, if the comparison is successful, the acceptance automation device uploads a "pass" message to the server; if the comparison is unsuccessful, the acceptance automation device uploads the collected experimental result data sequence.

[0158] S106. In response to the teacher's request to export the experimental information, the experimental information related to the experimenter is exported.

[0159] like Figure 5 As shown in the figure, after the experimenter completes the experiment and uploads the experimental data, the teacher can export the experimental data for scoring and assessment.

[0160] The present invention provides a digital circuit experiment method, which replaces and covers the basic design experiment link and the verification experiment link of the traditional digital circuit experiment, can avoid the debugging link, strengthen the experiment focus, improve the experimental teaching efficiency, reduce the ineffective consumption of experimental time resources, reduce the interference of the verification circuit debugging on the experimental performance evaluation, enhance the fairness and objectivity of the experimental ability evaluation of the experimenter in the experimental teaching, can avoid the experimenter submitting the experimental result by calculating the experimental result through theoretical knowledge, can avoid the experimenter submitting the experimental result by copying the experimental result of others, effectively prevents the experimental cheating behavior, realizes the improvement of the design emphasis in the basic design experiment from multiple angles, makes the FPGA design environment transparent in the digital circuit experiment process, can improve the experimental result acceptance efficiency of the experimental teacher, avoids the acceptance resource squeeze under the high "student-teacher ratio", and reduces the teaching burden of the experimental teacher.

[0161] Example 3

[0162] A digital circuit experiment method is applied to the above-mentioned local information processing device. For a detailed description of the local information processing device, reference can be made to the corresponding description in the above-mentioned digital circuit experiment system embodiment, which will not be repeated here. Fig.11 As shown, the following steps are included:

[0163] S200, download the black box circuit file corresponding to the experimenter;

[0164] The operation process of the black box experiment platform from the experimenter's perspective is as follows Fig. 9 As shown in Figure 2, the experimenter logs into the server, randomly extracts a black box circuit file and downloads it to the local computer.

[0165] S201, implementing the black box circuit file on a test board;

[0166] Specifically, the black box circuit is implemented on the FPGA experiment board through the FPGA configuration software installed on the local computer.

[0167] S202, uploading the logic function analysis result to the server;

[0168] like Fig. 9 As shown, the experimenter uses experimental equipment including a multimeter and an oscilloscope to perform tests according to standardized experimental operation techniques, record experimental data, and analyze logical functions; the analyzed logical functions are uploaded to the server, and the server automatically determines whether the analysis results are correct or not.

[0169] S203, determining the timing for the experimenter to draw the design schematic diagram in the standardized template file according to the judgment result of the server and generating VHDL code of the drawn schematic diagram;

[0170] In some embodiments, the step of determining the timing for the experimenter to draw the design schematic diagram in the normalized template file according to the judgment result of the server includes:

[0171] If the server determines that the verification is successful, it will allow the experimenter to draw a design schematic in the standardized template file. Fig. 9 As shown in the figure, after the experimenter uploads the conclusion and passes it, he starts to draw the design schematic in the Multisim standardized template file released by the teacher; after the schematic is drawn, the VHDL code is generated through the export function of Multisim.

[0172] S204, calling the automatic generation program to compile and synthesize the generated code stream file and configure the experimental board.

[0173] In this embodiment, a generation automation program specially compiled for the black box experiment system is called to implement the entire process of compiling and synthesizing the generated code stream file and configuring the FPGA experiment board. The pin definition is pre-configured and no operation is required by the experimenter. The FPGA software environment is transparent during the experiment.

[0174] The present invention provides a digital circuit experiment method, which replaces and covers the basic design experiment link and the verification experiment link of the traditional digital circuit experiment, can avoid the debugging link, strengthen the experiment focus, improve the experimental teaching efficiency, reduce the ineffective consumption of experimental time resources, reduce the interference of the verification circuit debugging on the experimental performance evaluation, enhance the fairness and objectivity of the experimental ability evaluation of the experimenter in the experimental teaching, can avoid the experimenter submitting the experimental result by calculating the experimental result through theoretical knowledge, can avoid the experimenter submitting the experimental result by copying the experimental result of others, effectively prevents the experimental cheating behavior, realizes the improvement of the design emphasis in the basic design experiment from multiple angles, makes the FPGA design environment transparent in the digital circuit experiment process, can improve the experimental result acceptance efficiency of the experimental teacher, avoids the acceptance resource squeeze under the high "student-teacher ratio", and reduces the teaching burden of the experimental teacher.

[0175] Example 4

[0176] A digital circuit experiment method is applied to the above-mentioned acceptance automation module. For a detailed description of the acceptance automation module, reference can be made to the corresponding description in the above-mentioned digital circuit experiment system embodiment, which will not be repeated here. Fig.12 As shown, the following steps are included:

[0177] S300, downloading the corresponding test case file according to the experimenter information;

[0178] In order to solve the problem of acceptance resource squeeze under the 1:30 teacher-student ratio and further improve acceptance efficiency, a laboratory is equipped with 3-4 sets of acceptance automation equipment at the same time, and the experimenters can complete the acceptance operations by themselves without the intervention of teachers.

[0179] like Fig. 9 As shown, the experimenter uses a multimeter, oscilloscope and other equipment to conduct independent inspection of the designed circuit. After confirming that the design is correct, he goes to the acceptance automation equipment for independent acceptance.

[0180] like Figure 6 As shown in the figure, during the acceptance process, the experimenter only needs to do three things: connect the all-in-one data module box and the FPGA experiment board through two sets of interface strips to form a test closed loop; log in your student number on the acceptance automation software on the local computer; click acceptance and observe the acceptance feedback information. An experimenter can complete the acceptance in no more than 1 minute.

[0181] Due to the need for automated acceptance, the connection between the all-in-one data module and the experimental circuit must be in a specified format and strictly implemented, otherwise the automated acceptance will fail. Ensuring the correct connection requires the collaboration of both software and hardware. The hardware needs to define the order of the socket pins, which cannot be wrong. Furthermore, the interface module is configured as a planned interface socket, and the pin order of the interface socket is predefined; the software needs to design the circuit as a standardized input and output port, so it is necessary to pre-compile a standardized template file for the interface of the circuit to be tested.

[0182] The interface of the standardized template file for combinational logic is as follows Figure 7 As shown. In order to ensure that the experimenter can easily verify the circuit implementation by himself during the design process and can quickly perform automated acceptance, JA0~JA2 in the figure are input socket interface terminals, JB0~JB2 are output socket interface terminals, which are used during automated acceptance, SW0~SW2 are dip switches, and LED0~LED2 are light-emitting diodes, which are used when the experimenter designs and debugs. The switch between acceptance and debugging is controlled by the dip switch SW15 controlling three two-to-one data selectors. The experimenter only needs to draw a valid schematic in the design area, and after the background FPGA process operation, it can be manually verified on the experimental board, or quickly verified on the automated acceptance equipment.

[0183] Although some of the existing basic design experiment tasks are based on the FPGA platform and use FPGA for digital circuit experimental design learning, no matter the editing code type or the schematic diagram type design, the software environment provided by the FPGA manufacturer is usually used to complete the generation process from source code to code stream file, as well as the configuration of FPGA hardware operations. Therefore, the experimenter needs to master a series of complex usage processes of the manufacturer's software including configuration pins. This process will bias the experimenter's attention to the use of the software environment within the limited experimental class time, affecting the achievement of experimental teaching objectives. The present invention improves the design emphasis in the basic design experiment from multiple angles, makes the FPGA design environment transparent in the digital circuit experiment process, strengthens the experimental focus, and improves the efficiency of experimental teaching.

[0184] After the experimenter logs in with his / her student ID, the acceptance automation program logs in to the server and downloads the corresponding test case files for the experimenter according to his / her student ID.

[0185] S301, sending the input signal to the experiment board through the interface module via the signal source part of the all-in-one data module; specifically, sending the input signal to the FPGA experiment board through the interface strip at a certain frequency via the signal source part of the all-in-one module.

[0186] S302, collecting the output signal of the experimental board through the signal collection part of the all-in-one data module; specifically, synchronously receiving the output signal of the FPGA experimental board through the signal collection part of the all-in-one module.

[0187] S303, performing consistency comparison between the collected output signal and the output signal in the test case file;

[0188] In some embodiments, the step of comparing the collected output signal with the output signal in the test case file for consistency includes:

[0189] The collected experimental result data sequence is compared with the test case for consistency by using a window shifting check method, wherein the length of the experimental result data sequence is multiple times the length of the test case, for example, the length of the data sequence of the collected experimental circuit is 1.5 to 2 times the length of the test case.

[0190] When testing sequential logic circuits, such as counters, there may be a "pre-start state", so the sequential logic verification process needs to adopt a "moving window verification method", such as Figure 8 As shown: together with the input and output, collect data of 1.5 to 2 times the length of the test case, take the data fragments with the same length as the test case signal sequence in the collected signal of the tested circuit and compare them one by one. If the comparison fails ( Figure 8 The window moves backward until the comparison is successful ( Figure 8The thick dashed line frame in the upper middle part and the lower dashed line frame), or until all the acquisition signal sequences of the circuit under test are compared.

[0191] S304: Upload corresponding information to the server according to the comparison result.

[0192] In some embodiments, the step of uploading corresponding information to the server according to the comparison result includes:

[0193] If the acceptance is passed, the passing information is uploaded to the server;

[0194] If the acceptance fails, the collected experimental result data sequence is uploaded to the server. Based on compatibility considerations, the length of the data sequence collected from the experimental circuit in this embodiment is 1.5 to 2 times the length of the test case, and a window shifting verification method is adopted.

[0195] The present invention provides a digital circuit experiment method, which replaces and covers the basic design experiment link and the verification experiment link of the traditional digital circuit experiment, can avoid the debugging link, strengthen the experiment focus, improve the experimental teaching efficiency, reduce the ineffective consumption of experimental time resources, reduce the interference of the verification circuit debugging on the experimental performance evaluation, enhance the fairness and objectivity of the experimental ability evaluation of the experimenter in the experimental teaching, can avoid the experimenter submitting the experimental result by calculating the experimental result through theoretical knowledge, can avoid the experimenter submitting the experimental result by copying the experimental result of others, effectively prevents the experimental cheating behavior, realizes the improvement of the design emphasis in the basic design experiment from multiple angles, makes the FPGA design environment transparent in the digital circuit experiment process, can improve the experimental result acceptance efficiency of the experimental teacher, avoids the acceptance resource squeeze under the high "student-teacher ratio", and reduces the teaching burden of the experimental teacher.

[0196] Example 5

[0197] A computer device 400, such as Fig.13 As shown, it includes a memory 410, a processor 420, and a computer program 430 stored in the memory and executable on the processor. When the processor executes the computer program, the steps of a digital circuit experiment method are implemented. For a detailed description of the method, reference can be made to the corresponding description in the above method embodiment, which will not be repeated here.

[0198] Example 6

[0199] A computer readable storage medium such as Fig.14 As shown, a computer program is stored thereon, and when the computer program is executed by the processor, the steps of a digital circuit experiment method are implemented. For a detailed description of the method, reference may be made to the corresponding description in the above method embodiment, and no further description is given here.

[0200] The number of devices and processing scales described here are used to simplify the description of the present invention. Applications, modifications and variations of the present invention will be obvious to those skilled in the art.

[0201] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and implementation modes. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

[0202] The apparatus, computer device, non-volatile computer storage medium and method provided in the embodiments of this specification correspond to each other, and therefore, the apparatus, computer device and non-volatile computer storage medium also have similar beneficial technical effects as the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the corresponding apparatus, computer device and non-volatile computer storage medium will not be repeated here.

[0203] Those skilled in the art also know that, in addition to implementing the controller in a purely computer-readable program code, the controller can be made to implement the same function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, such a controller can be considered as a hardware component, and the devices for implementing various functions included therein can also be considered as structures within the hardware component. Or even, the devices for implementing various functions can be considered as both software units for implementing the method and structures within the hardware component.

[0204] The systems, devices or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above devices are described separately by functions in various units. Of course, when implementing one or more embodiments of this specification, the functions of each unit can be implemented in the same or more software and / or hardware.

[0205] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may be in the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0206] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0207] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0208] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0209] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0210] The specification may be described in the general context of computer-executable instructions executed by a computer, such as program units. Generally, program units include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In a distributed computing environment, program units may be located in local and remote computer storage media, including storage devices.

[0211] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0212] The above description is only an embodiment of this specification and is not intended to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the scope of the claims of one or more embodiments of this specification.

Claims

1. A digital circuit experiment system, characterized in that: It includes a server, a local information processing device, an all-in-one data module, an interface module, and an acceptance automation module; among which, The server is used to store black box circuit files and their test case files, experimenter information, generate and store associations between the experimenter and the black box circuit files and the test case files, receive logic function analysis results uploaded by the experimenter and determine the correctness, receive information uploaded by the acceptance automation module, and export experiment information related to the experimenter in response to a teacher's request; The local information processing device is used to implement the black box circuit file extracted by the experimenter on the experimental board, determine the timing of the experimenter drawing the design schematic diagram in the standardized template file according to the judgment result of the server and generate the VHDL code of the drawn schematic diagram, call the generation automation program to compile the comprehensive embodiment to generate the code stream file and configure the experimental board; The interface module is used to connect the all-in-one data module and the experimental board to form a test closed loop; The acceptance automation module is used to download the corresponding test case file according to the experimenter information, send the input signal to the experimental board through the interface module through the signal source part of the all-in-one data module, and collect the output signal of the experimental board through the signal acquisition part of the all-in-one data module, compare the collected output signal with the output signal in the test case file for consistency, and upload corresponding information to the server according to the comparison result.

2. A digital circuit experiment system as claimed in claim 1, characterized in that: The server database also stores circuit file information, including file name and related attributes. The file name points to the black box circuit file and the test case file. The server database also stores exercises and answers corresponding to each file and the ownership relationship of the files.

3. A digital circuit experiment system as claimed in claim 2, characterized in that: The ownership relationship of the file includes the experimental project to which the file belongs, and the experimental course to which the experimental project belongs.

4. A digital circuit experiment system as claimed in claim 2, characterized in that: The black box circuit file and the test case file are configured to be generated in batches through an FPGA environment and a script.

5. A digital circuit experiment system as claimed in claim 2, characterized in that: The black box circuit file is stored in the server in the form of a code stream file, and the test case file is stored in the server in the form of a text file.

6. A digital circuit experiment system as claimed in claim 5, characterized in that: The test cases include 0, 1, and half-width commas. The number of characters in each line is the same and they are separated by commas. The data before the comma is defined as the input signal and the data after the comma is defined as the output signal. Each line of data is a time slice sampling data.

7. A digital circuit experiment system as claimed in claim 1, characterized in that: The interface module is configured as a planned interface strip, and the pin sequence of the interface strip is predefined.

8. A digital circuit experiment system as claimed in claim 6, characterized in that: The acceptance automation module uses a window-shifting verification method to compare the collected experimental result data sequence with the test case for consistency, and the length of the experimental result data sequence is a multiple of the length of the test case; if the acceptance passes, the passing information is uploaded to the server; if the acceptance fails, the collected experimental result data sequence is uploaded to the server.

9. A digital circuit experiment method, applied to the server as claimed in claim 1, characterized in that: The following steps are involved: Receive black box circuit files, test case files and file information edited by teachers; In response to a teacher's request to create an experimental project or an experimental course, an experimental project or an experimental course is created, and an attribution relationship between the black box circuit file, the test case file, the experimental project, and the experimental course is established; importing the experimenter information in response to a request to import the experimenter information; After the course is arranged, an association relationship is established between the experimenter information and the black box circuit file and the test case file; Receive the logic function analysis results uploaded by the experimenter and determine the correctness of the logic function analysis results; Receive information uploaded by the acceptance automation module; In response to a teacher's request to export the experimental information, the experimental information related to the experimenter is exported.

10. A digital circuit experiment method as claimed in claim 9, characterized in that: Also includes the steps: In response to the experimenter's request to extract the black box circuit file, the black box circuit file is extracted in a random manner and transmitted to a local information processing device used by the experimenter.

11. A digital circuit experiment method as claimed in claim 9, characterized in that: The step of judging the correctness of the logic function analysis result comprises: If the verification is determined to be successful, a control signal is sent to enable the local information processing device to allow the experimenter to draw a design schematic diagram in a standardized template file.

12. A digital circuit experiment method, applied to the local information processing device as claimed in claim 1, characterized in that: The following steps are involved: Download the black box circuit file corresponding to the experimenter; Implement the black box circuit file on a test board; Upload the logic function analysis results to the server; Determine the timing for the experimenter to draw the design schematic diagram in the standardized template file according to the judgment result of the server and generate the VHDL code of the drawn schematic diagram; Call the generation automation program to compile and synthesize the generated code stream file and configure the experimental board.

13. A digital circuit experiment method as claimed in claim 12, characterized in that: The step of determining the timing for the experimenter to draw the design schematic diagram in the standardized template file according to the judgment result of the server includes: If the server determines that the verification is successful, it allows the experimenter to draw a design schematic diagram in the standardized template file.

14. A digital circuit experiment method, applied to the acceptance automation module as claimed in claim 1, characterized in that: The following steps are involved: Download the corresponding test case file according to the experimenter information; The input signal is sent to the experiment board through the interface module via the signal source part of the all-in-one data module; Collecting the output signal of the experimental board through the signal acquisition part of the all-in-one data module; Compare the collected output signal with the output signal in the test case file for consistency; Upload the corresponding information to the server based on the comparison results.

15. A digital circuit experiment method as claimed in claim 14, characterized in that: The step of comparing the collected output signal with the output signal in the test case file for consistency includes: The collected experimental result data sequence is compared with the test case for consistency using the window-shifting verification method.

16. A digital circuit experiment method as claimed in claim 14, characterized in that: The step of uploading corresponding information to the server according to the comparison result includes: If the acceptance is passed, the passing information is uploaded to the server; If the acceptance fails, the collected experimental result data sequence is uploaded to the server.

17. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 9 to 16 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 9 to 16 are implemented.

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