Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate, a plurality of pixel units and a plurality of data lines which are located in a display area, and a plurality of data outgoing lines and a plurality of first-class test circuit groups which are located in a first frame area. The plurality of first type test circuit groups are electrically connected with the plurality of data outgoing lines. The at least one first-class test circuit group comprises at least one first-class test circuit arranged along a first direction; the first type of test circuit comprises a plurality of transistors arranged along a first direction, the first type of test circuit is configured to provide a first type of test data signal for a column of pixel units, and the column of pixel units comprises a plurality of pixel units arranged along the first direction.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] This embodiment provides a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a plurality of pixel units, a plurality of data lines, a plurality of data lead lines, and a plurality of first-class test circuit groups. The substrate comprises: a display area and a first frame area located on one side of the display area along a first direction. A plurality of pixel units and a plurality of data lines are arranged on the substrate and located in the display area, the plurality of pixel units are electrically connected to the plurality of data lines, and the pixel units include a plurality of sub-pixels. A plurality of data lead lines are located in the first frame area, the plurality of data lead lines are electrically connected to the plurality of data lines. A plurality of first-class test circuit groups are located in the first frame area and connected to the plurality of data lead lines. At least one of the plurality of first-class test circuit groups comprises at least one first-class test circuit arranged along the first direction; the first-class test circuit comprises a plurality of transistors arranged along the first direction, and the first-class test circuit is configured to provide a first-class test data signal to a column of pixel units, the column of pixel units comprising a plurality of pixel units arranged along the first direction.

[0006] In some exemplary embodiments, the plurality of sub-pixels of the pixel unit include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The first type of test circuit includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit; the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit each include at least one transistor. The first test circuit is configured to provide a first type of test data signal to the first sub-pixel of the e-th row of pixel units in the column of pixel units in a first time period, and to provide a first type of test data signal to the second sub-pixel of the e+1-th row of pixel units in the column of pixel units in a second time period; the second test circuit is configured to provide a first type of test data signal to a column of third sub-pixels in the column of pixel units; the third test circuit is configured to provide a first type of test data signal to the first sub-pixel of the e+1-th row of pixel units in the column of pixel units in the first time period, and to provide a first type of test data signal to the second sub-pixel of the e-th row of pixel units in the column of pixel units in the second time period; wherein e is a positive integer; the fourth test circuit is configured to provide a first type of test data signal to another column of third sub-pixels in the column of pixel units.

[0007] In some exemplary embodiments, the first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the at least one first-type test circuit group are arranged sequentially along the first direction.

[0008] In some exemplary embodiments, the display substrate further comprises: a plurality of first test control lines, a plurality of second test control lines, a plurality of third test control lines, a plurality of first test data lines, a plurality of second test data lines and at least one third test data line located in the first frame region. The first test circuit comprises: at least one first test transistor and at least one second test transistor, the gate of the at least one first test transistor being connected to a first test control line among the plurality of first test control lines, the first electrode of the at least one first test transistor being connected to a first test data line among the plurality of first test data lines, the gate of the at least one second test transistor being connected to a second test control line among the plurality of second test control lines, the first electrode of the at least one second test transistor being connected to a second test data line among the plurality of second test data lines, and the second electrode of the at least one first test transistor and the second electrode of the at least one second test transistor being connected to the same data lead-out line among the plurality of data lead-out lines. The second test circuit includes: at least one third test transistor, a gate of the at least one third test transistor is connected to a third test control line among the plurality of third test control lines, a first electrode of the at least one third test transistor is connected to the at least one third test data line, and a second electrode of the at least one third test transistor is connected to a data lead-out line among the plurality of data lead-out lines. The third test circuit includes: at least one fourth test transistor and at least one fifth test transistor, wherein the gate of the at least one fourth test transistor is connected to another second test control line among the plurality of second test control lines, the first electrode of the at least one fourth test transistor is connected to another first test data line among the plurality of first test data lines, the gate of the at least one fifth test transistor is connected to another first test control line among the plurality of first test control lines, the first electrode of the at least one fifth test transistor is connected to another second test data line among the plurality of second test data lines, and the second electrode of the at least one fourth test transistor and the second electrode of the at least one fifth test transistor are connected to the same data lead line among the plurality of data lead lines; the fourth test circuit includes: at least one sixth test transistor, wherein the gate of the at least one sixth test transistor is connected to another third test control line among the plurality of third test control lines, the first electrode of the at least one sixth test transistor is connected to the at least one third test data line, and the second electrode of the sixth test transistor is connected to one data lead line among the plurality of data lead lines; the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit are connected to different data lead lines.

[0009] In some exemplary embodiments, the display substrate includes: four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines and one third test data line; the first second test control line, the first first test control line, the first first test data line, the first second test data line, the second second test control line, the second first test control line, the first third test control line, the third test data line, the second third test control line, the second first test data line, the third first test control line, the third second test control line, the fourth first test control line and the second second test data line are sequentially arranged along the first direction; the first type of test circuit of the at least one first type test circuit group includes: a first test transistor, a second test transistor, a third test transistor, a fourth test transistor, a fifth test transistor and a sixth test transistor; the first test transistor is connected to the first first test control line and the The first test transistor is connected to the first first test data line and is located between the first first test control line and the first first test data line in the first direction; the second test transistor is connected to the first second test data line and the second second test control line and is located between the first second test data line and the second second test control line in the first direction; the third test transistor is connected to the first third test control line and the third test data line and is located between the first third test control line and the third test data line in the first direction; the fourth test transistor is connected to the second first test data line and the third second test control line and is located between the second first test data line and the third first test control line in the first direction; the fifth test transistor is connected to the fourth first test control line and the second second test data line and is located between the fourth first test control line and the second second test data line in the first direction.

[0010] In some exemplary embodiments, the display substrate includes: two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines, and three third test data lines; the first second test control line, the first first test data line, the second first test data line, the first first test control line, the second second test control line, the first second test data line, the second second test data line, the first third test control line, the first third test data line, the second third test data line, the third third test data line, the second third test control line, the third second test control line, the third first test data line, the fourth first test control line, the fourth second test control line, the third second test data line, and the fourth second test data line are sequentially arranged along the first direction; the first type of test circuit of the at least one first type test circuit group includes: two first test transistors, two second test transistor, two third test transistors, two fourth test transistors, two fifth test transistors and two sixth test transistors; the two first test transistors are located between the first first test data line and the second first test data line in the first direction; the two second test transistors are located between the first second test data line and the second second test data line in the first direction; the two third test transistors are located between the first third test data line and the second third test data line in the first direction; the two sixth test transistors are located between the second third test data line and the third third test data line in the first direction; the two fourth test transistors are located between the third first test data line and the fourth first test data line in the first direction; the two fifth test transistors are located between the third second test data line and the fourth second test data line in the first direction.

[0011] In some exemplary embodiments, a first first test transistor of the first type of test circuit is connected to the first first test data line and the first first test control line, a second first test transistor is connected to the second first test data line and the first first test control line; a first second test transistor is connected to the first second test data line and the second second test control line, a second second test transistor is connected to the second second test data line and the second second test control line; a first third test transistor is connected to the first third test data line and the first third test control line, a second third test transistor is connected to the second third test data line and the first third test control line. a third test control line; a first sixth test transistor is connected to the second third test data line and the second third test control line, and a second sixth test transistor is connected to the third third test data line and the second third test control line; a first fourth test transistor is connected to the third first test data line and the third second test control line, and a second fourth test transistor is connected to the fourth first test data line and the third second test control line; a first fifth test transistor is connected to the third second test data line and the second first test control line, and a second fifth test transistor is connected to the fourth second test data line and the second first test control line.

[0012] In some exemplary embodiments, the at least one first-category test circuit group includes two first-category test circuits arranged along the first direction, and the first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the first first-category test circuit are arranged sequentially along the first direction, and the second test circuit, the fourth test circuit, the first test circuit, and the third test circuit of the second first-category test circuit are arranged sequentially along the first direction.

[0013] In some exemplary embodiments, the display substrate includes: four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines, and two third test data lines. The first first test control line, the first first test data line, the first second test data line, the first second test control line, the first third test control line, the first third test data line, the second third test control line, the second second test control line, the second first test data line, the second second test data line, the second first test control line, the third third test control line, the second third test data line, the fourth third test control line, the third first test control line, the third first test data line, the third second test data line, the third second test control line, the fourth second test control line, the fourth first test data line, the fourth second test data line, and the fourth first test control line are sequentially arranged along the first direction.

[0014] In some exemplary embodiments, the display substrate further includes: a plurality of second-type test circuit groups, at least one of the plurality of second-type test circuit groups including: at least one second-type test circuit arranged along the first direction, the second-type test circuit including a plurality of transistors arranged along the first direction, the second-type test circuit configured to provide a second-type test data signal to the column of pixel units.

[0015] In some exemplary embodiments, the second type of test circuit includes: a fifth test circuit, a sixth test circuit, a seventh test circuit, and an eighth test circuit. The one column of pixel units includes four columns of sub-pixels; the fifth test circuit, the sixth test circuit, the seventh test circuit, and the eighth test circuit of the second type of test circuit are configured to provide the second type of test data signals to the four columns of sub-pixels; the eighth test circuit, the seventh test circuit, the sixth test circuit, and the fifth test circuit of the second type of test circuit are arranged in sequence along the first direction.

[0016] In some exemplary embodiments, the fifth test circuit includes: at least one seventh test transistor, the sixth test circuit includes: at least one eighth test transistor, the seventh test circuit includes: at least one ninth test transistor, and the eighth test circuit includes: at least one tenth test transistor. The display substrate also includes: a plurality of fourth test control lines, a plurality of fourth test data lines, and a plurality of fifth test data lines located in the first frame area. The gate of the seventh test transistor and the gate of the eighth test transistor are connected to the same fourth test control line among the plurality of fourth test control lines, the first electrode of the seventh test transistor and the first electrode of the eighth test transistor are connected to the same fourth test data line among the plurality of fourth test data lines, the second electrode of the seventh test transistor is connected to one of the plurality of data lead lines, and the second electrode of the eighth test transistor is connected to another of the plurality of data lead lines. The gate of the ninth test transistor and the gate of the tenth test transistor are connected to the same fourth test control line among the multiple fourth test control lines, the first electrode of the ninth test transistor and the first electrode of the tenth test transistor are connected to the same fifth test data line among the multiple fifth test data lines, the second electrode of the ninth test transistor is connected to another data lead-out line among the multiple data lead-out lines, and the second electrode of the tenth test transistor is connected to another data lead-out line among the multiple data lead-out lines.

[0017] In some exemplary embodiments, the display substrate further includes: two first frame power lines and three second frame power lines located in the first frame area, the first second frame power line and the second second frame power line are located on both sides of the two first frame power lines and the third second frame power line, and the two first frame power lines are located on both sides of the third second frame power line.

[0018] In some exemplary embodiments, the display substrate further includes: four groups of initial signal lines located in the first border area, the first group of initial signal lines located on a side of the first second border power line away from the third second border power line, the second group of initial signal lines located on a side of the first second border power line close to the third second border power line, the third group of initial signal lines located on a side of the second second border power line close to the third second border power line, and the fourth group of initial signal lines located on a side of the second second border power line away from the third second border power line.

[0019] On the other hand, this embodiment provides a display device, including the display substrate as mentioned above.

[0020] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0022] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0023] Figure 2A is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure;

[0024] Figure 2B is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of an arrangement of sub-pixels in a display area of ​​at least one embodiment of the present disclosure;

[0026] Figure 4 A circuit schematic diagram of a first type of test circuit of at least one embodiment of the present disclosure;

[0027] Figure 5 An equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0028] Figure 6 A schematic plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0029] Fig. 7A for Figure 6 A schematic diagram of a first semiconductor layer in FIG.

[0030] Figure 7B for Figure 6 A schematic diagram of a first semiconductor layer and a first gate metal layer in FIG.

[0031] Figure 7C for Figure 6 A schematic diagram of a first semiconductor layer, a first gate metal layer and a second gate metal layer in FIG.

[0032] Figure 8 Another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0033] Fig. 9A schematic plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0034] Fig. 10A for Fig. 9 A schematic diagram of a first semiconductor layer and a first gate metal layer in FIG.

[0035] Fig. 10B for Fig. 9 A schematic diagram of a first semiconductor layer, a first gate metal layer and a second gate metal layer in FIG.

[0036] Fig.11 Another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0037] Fig.12 A schematic plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0038] Fig.13 for Fig.12 A schematic diagram of a first semiconductor layer, a first gate metal layer and a second gate metal layer in FIG.

[0039] Fig.14 Another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0040] Fig.15 An equivalent circuit diagram of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure;

[0041] Fig.16 A schematic plan view of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure;

[0042] Fig.17 for Fig.16 A schematic diagram of a first semiconductor layer, a first gate metal layer and a second gate metal layer in FIG.

[0043] Fig.18 A schematic diagram of local wiring in a first border area of ​​at least one embodiment of the present disclosure;

[0044] Fig.19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0046] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0047] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0048] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0049] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" may include "electrical connection", and "electrical connection" may include the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0050] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0051] In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In addition, the gate electrode may also be referred to as a control electrode. In the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0052] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0053] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0054] In this specification, "about" and "substantially" mean that the limits are not strictly defined and the process and measurement errors are allowed. In this disclosure, "same" includes the case where the numerical value differs within 10%, such as the case where the numerical value differs within 5%.

[0055] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B".

[0056] In this specification, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0057] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may be a closed polygon including linear edges. The display substrate may include: a display area AA and a frame area BB located around the display area AA. The frame area BB may include: a first frame area B1 and a fourth frame area B4 located on both sides of the display area AA along the first direction D1, and a second frame area B2 and a third frame area B3 located on both sides of the display area AA along the second direction D2. The first frame area B1 may be connected to the second frame area B2 and the third frame area B3, and the fourth frame area B4 may be connected to the second frame area B2 and the third frame area B3. The first frame area B1, the second frame area B2, the third frame area B3 and the fourth frame area B4 may be connected to surround the display area AA. For example, the first frame area B1 may also be referred to as the lower frame area of ​​the display substrate, the second frame area B2 may also be referred to as the left frame area of ​​the display substrate, the third frame area B3 may also be referred to as the right frame area of ​​the display substrate, and the fourth frame area B4 may also be referred to as the upper frame area of ​​the display substrate. However, this embodiment is not limited to this.

[0058] In some examples, such as Figure 1As shown, the first frame area B1 may include: a first sub-area B11, a bending area B12, and a second sub-area B13 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B11 may be connected to the second frame area B2, the third frame area B3, and the display area AA. The bending area B12 may be connected between the first sub-area B11 and the second sub-area B13. The bending area B12 may be configured to bend the second sub-area B13 to the back of the display area AA.

[0059] In some examples, such as Figure 1 As shown, the second sub-area B13 may include: a circuit setting area B133, a first signal access area B131, and a second signal access area B132 arranged in sequence in the first direction D1 along a direction away from the bending area B12. The circuit setting area B133 may be provided with a plurality of electrostatic discharge circuits and a plurality of test circuits, and the plurality of test circuits may be configured to provide test data signals to a plurality of data lines DL of the display area AA. The plurality of electrostatic discharge circuits may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. For example, the plurality of electrostatic discharge circuits may be located on one side of the plurality of test circuits close to the bending area B12.

[0060] In some examples, the first signal access area B131 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect an integrated circuit (IC). Some of the plurality of first contact pads may be configured to provide data signals to a plurality of data lines. The second signal access area B132 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC). At least one first contact pad in the first signal access area B131 and at least one second contact pad in the second signal access area B132 may be connected via an internal bonding wire (ILB, InnerLead bonding).

[0061] In some examples, the display area AA may include: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals or test data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signal may include a scan signal, or may include a scan signal and a light emitting control signal, or may include a scan signal, a reset control signal, and a light emitting control signal.

[0062] In some examples, the second direction D2 may be an extension direction (e.g., a row direction) of the gate lines GL in the display area AA; the first direction D1 may be an extension direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.

[0063] In some examples, a pixel unit of display area AA may include multiple sub-pixels. For example, a pixel unit may include four sub-pixels, and the four sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and two third sub-pixels emitting a third color light (e.g., green light). In other examples, a pixel unit may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.

[0064] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0065] In some examples, the shape of the light-emitting element of the sub-pixel can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally in parallel, vertically in parallel, or in a square. However, this embodiment is not limited to this. In other examples, when a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner.

[0066] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0067] Figure 2A It is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure. Figure 2A In the example, the structure of a sub-pixel in the display area AA is taken as an example for illustration. In this example, the pixel circuit includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor as an example for illustration.

[0068] In some examples, such as Figure 2A As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, and a packaging structure layer 14 sequentially arranged on the substrate 10. The circuit structure layer 12 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may include at least: a light emitting element of a plurality of sub-pixels. In other examples, the display substrate may further include a touch structure layer located on the side of the packaging structure layer 14 away from the substrate 10.

[0069] In some examples, Figure 2A In the figure, each sub-pixel includes a first type transistor 21, a second type transistor 22 and a capacitor 23. The first type transistor 21 may be a low temperature polysilicon thin film transistor, and the second type transistor 22 may be an oxide thin film transistor.

[0070] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are arranged on the substrate 10. A first insulating layer 101 may be arranged between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be arranged between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be arranged between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be arranged between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planar layer) may be arranged between the first source-drain metal layer and the second source-drain metal layer, and the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planar layer) may be arranged on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate, and can also increase the adhesion of the film layer in the display substrate on the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can also be provided on the side of the buffer layer close to the substrate, and the bottom shading metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid external light from affecting the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0071] In some examples, such as Figure 2AAs shown, the first semiconductor layer in the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least: a second plate 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, the two may overlap. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0072] In some examples, such as Figure 2AAs shown, the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first type transistor 21, and a second source 221 and a second drain 222 of the second type transistor 22. The fifth insulating layer 105 may be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104 and the third insulating layer 103 in the third pixel via hole and the fourth pixel via hole can be removed to expose at least part of the surface of the two ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first area 2101 of the first active layer 210 through the first pixel via hole, and the first drain 212 can be electrically connected to the second area 2102 of the first active layer 210 through the second pixel via hole. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via hole, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via hole. The second source-drain metal layer can include at least: a first switching electrode 241. The first switching electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 of the pixel circuit through the fifth pixel via hole opened in the sixth insulating layer 106 and the seventh insulating layer 107. In this example, the electrical connection between the pixel circuit and the light emitting element can be achieved through the first switching electrode 241 .

[0073] In some examples, the gate line of the display area may be located at the first gate metal layer and the third gate metal layer, the data line of the display area may be located at the second source-drain metal layer, the first power line of the display area may be located at the second source-drain metal layer, the first data connection segment of the data connection line of the display area may be located at the first source-drain metal layer, and the second data connection segment may be located at the second source-drain metal layer. This embodiment is not limited to this. In other examples, the circuit structure layer of the display area may also include: a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate, and the data connection line may be located at the third source-drain metal layer.

[0074] In some examples, such as Figure 2AAs shown, the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the eighth insulating layer 108, and electrically connected to the first transfer electrode 241 through the sixth pixel via hole provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the organic light emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0075] In some examples, the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and at least one of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0076] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0077] In some examples, such as Figure 2A As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display substrate, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0078] Figure 2B Another partial cross-sectional schematic diagram of a display region of at least one embodiment of the present disclosure. In some examples, the transistor types of multiple pixel transistors in the pixel circuit may be the same, for example, they may all be low-temperature polysilicon thin-film transistors. Figure 2B In the figure, a first type transistor 21 and a capacitor 23 included in each sub-pixel are taken as an example for illustration.

[0079] In some examples, such as Figure 2BAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate 10. A first insulating layer 101 may be arranged between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer, a third insulating layer 103 may be arranged between the second gate metal layer and the first source-drain metal layer, a sixth insulating layer 106 and a seventh insulating layer 107 may be arranged between the first source-drain metal layer and the second source-drain metal layer, and an eighth insulating layer 108 may be arranged on the side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 may be inorganic insulating layers. The remaining structures of the display area of ​​the display substrate of this example may be referred to. Figure 2A The description of the embodiment shown is therefore not repeated here.

[0080] In some implementations, the test circuit located in the first frame area requires a large wiring space, which limits the arrangement space of the remaining wiring in the first frame area. The space of some wirings in the first frame area (such as wirings for transmitting power signals, control signals, etc.) is limited, which is easy to affect the display effect of the display substrate.

[0081] The present embodiment provides a display substrate, comprising: a substrate, a plurality of pixel units, a plurality of data lines, a plurality of data lead lines, and a plurality of first-class test circuit groups. The substrate comprises a display area and a first frame area located on one side of the display area along a first direction. A plurality of pixel units and a plurality of data lines are arranged on the substrate and located in the display area, a plurality of pixel units are electrically connected to a plurality of data lines, and a single pixel unit comprises a plurality of sub-pixels. A plurality of data lead lines are located in the first frame area and are electrically connected to a plurality of data lines. A plurality of first-class test circuit groups are located in the first frame area and are connected to a plurality of data lead lines. Each first-class test circuit group comprises at least one first-class test circuit arranged along a first direction, and the first-class test circuit comprises a plurality of transistors arranged along a first direction. The first-class test circuit is configured to provide a first-class test data signal to a column of pixel units. A column of pixel units comprises a plurality of pixel units arranged along a first direction.

[0082] In some examples, the plurality of first-type test circuit groups may be arranged along a second direction that intersects the first direction, for example, a plane where the second direction and the first direction are located is parallel to a plane where the substrate is located, and the second direction may be perpendicular to the first direction.

[0083] The display substrate provided in this embodiment arranges at least one first-type test circuit along the first direction, and arranges multiple transistors of the first-type test circuit along the first direction, which is beneficial to compressing the arrangement space of the test circuit in the first frame area along the second direction, thereby facilitating optimizing the arrangement space of the remaining wirings in the first frame area and ensuring the wiring width of the remaining wirings.

[0084] The solution of this embodiment is described below by means of some examples.

[0085] Figure 3 Schematic diagram of an arrangement of sub-pixels in a display area of ​​at least one embodiment of the present disclosure. Figure 3 As shown, a pixel unit of the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light. Multiple pixel units may be arranged in an array within the display area AA. The pixel circuits of multiple sub-pixels may be arranged in an array along the first direction D1 and the second direction D2. In a single pixel unit, the light-emitting elements of the four sub-pixels may be arranged in different columns along the second direction D2, the light-emitting elements of the first sub-pixel 15 and the second sub-pixel 16 may be arranged in the same row, and the light-emitting elements of the two third sub-pixels 17a and 17b may be arranged in the same row. The rows where the light-emitting elements of the first sub-pixel 15 and the light-emitting elements of the third sub-pixel 17a are located may be arranged at intervals along the first direction D1. In this example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixels 17a and 17b can be green sub-pixels (G). For example, the third sub-pixel 17a can be the first green sub-pixel (G1), and the third sub-pixel 17b can be the second green sub-pixel (G2).

[0086] In some examples, such as Figure 3As shown, the plurality of pixel units arranged along the second direction D2 may be a row of pixel units, and the plurality of pixel units arranged along the first direction D1 may be a column of pixel units. The plurality of pixel units may include a plurality of first pixel units and a plurality of second pixel units, and the arrangement order of the four sub-pixels in the first pixel units and the second pixel units may be different. For example, the e-th row of pixel units may include: a plurality of first pixel units arranged in sequence along the second direction D2; the first sub-pixel 15, the third sub-pixel 17a, the second sub-pixel 16 and the third sub-pixel 17b of the first pixel unit are arranged in sequence along the second direction D2. The e+1-th row of pixel units may include: a plurality of second pixel units arranged in sequence along the second direction D2, and the second sub-pixel 16, the third sub-pixel 17b, the first sub-pixel 15 and the third sub-pixel 17a of the second pixel unit may be arranged in sequence along the second direction D2. A column of pixel units may include: first pixel units and second pixel units alternately arranged along the first direction D1. Wherein, e may be an integer greater than 0. For example, the sub-pixels of odd-numbered pixel rows in the display area may be arranged in RG1BG2, and the sub-pixels of even-numbered pixel rows may be arranged in BG2RG1; or, the sub-pixels of odd-numbered pixel rows in the display area may be arranged in BG2RG1, and the sub-pixels of even-numbered pixel rows may be arranged in RG1BG2.

[0087] In some examples, a plurality of sub-pixels arranged along the first direction D1 may be a column of sub-pixels. A column of pixel units may include four columns of sub-pixels, such as the jth column to the j+3th column of sub-pixels. The jth column of sub-pixels and the j+2th column of sub-pixels may include: first sub-pixels 15 and second sub-pixels 16 alternately arranged along the first direction D1; the j+1th column of sub-pixels and the j+3th column of sub-pixels may include: third sub-pixels 17a and 17b alternately arranged along the first direction D1. j may be an integer greater than 1. The pixel circuit of each column of sub-pixels may be connected to the same data line. For example, the jth column of sub-pixels may be connected to the data line DLj, the j+1th column of sub-pixels may be connected to the data line DLj+1, the j+2th column of sub-pixels may be connected to the data line DLj+2, and the j+3th column of sub-pixels may be connected to the data line DLj+3.

[0088] Figure 4 is a circuit schematic diagram of a first type of test circuit of at least one embodiment of the present disclosure. In some examples, such as Figure 4 As shown, the first type of test circuit may include: a first test circuit 401 , a second test circuit 402 , a third test circuit 403 and a fourth test circuit 404 .

[0089] In some examples, the first test circuit 401 may include: a first test transistor T1 and a second test transistor T2. The gate of the first test transistor T1 is connected to the first test control line SWR, and the first electrode of the first test transistor T1 may be connected to the first test data line DR; the gate of the second test transistor T2 may be connected to the second test control line SWB, and the first electrode of the second test transistor T2 may be connected to the second test data line DB; the second electrode of the first test transistor T1 and the second electrode of the second test transistor T2 may be connected to the same data lead line (e.g., data lead line DA(n)). Where n is a positive integer.

[0090] In some examples, the second test circuit 402 may include: a third test transistor T3. A gate of the third test transistor T3 may be connected to a third test control line SWG, a first electrode of the third test transistor T3 may be connected to a third test data line DG, and a second electrode of the third test transistor T3 may be connected to a data lead line (e.g., a data lead line DA(n+1)).

[0091] In some examples, the third test circuit 403 may include: a fourth test transistor T4 and a fifth test transistor T5. The gate of the fourth test transistor T4 may be connected to the second test control line SWB, and the first electrode of the fourth test transistor T4 may be connected to the first test data line DR. The gate of the fifth test transistor T5 may be connected to the first test control line SWR, and the first electrode of the fifth test transistor T5 may be connected to the second test data line DB. The second electrode of the fourth test transistor T4 and the second electrode of the fifth test transistor T5 may be connected to the same data lead line (e.g., data lead line DA(n+2)).

[0092] In some examples, the fourth test circuit 404 may include: a sixth test transistor T6. A gate of the sixth test transistor T6 may be connected to the third test control line SWG, a first electrode of the sixth test transistor T6 may be connected to the third test data line DG, and a second electrode of the sixth test transistor T6 may be connected to a data lead line (e.g., data lead line DA(n+3)).

[0093] In some examples, the data lead line DA(n) can be connected to the data line DLj, and the column of sub-pixels connected thereto may include a first sub-pixel (R) and a second sub-pixel (B), and the data lead line DA(n+2) can be connected to the data line DLj+2, and the column of sub-pixels connected thereto may include a first sub-pixel (R) and a second sub-pixel (B). For a row of pixel units in the display area, the sub-pixel connected to the data lead line DA(n) and the sub-pixel connected to the data lead line DA(n+2) emit light of different colors. For example, for the e-th row of pixel units, the data lead line DA(n) can be connected to the first sub-pixel through the data line DLj, and the data lead line DA(n+2) can be connected to the second sub-pixel through the data line DLj+2; for the e+1-th row of pixel units, the data lead line DA(n) can be connected to the second sub-pixel through the data line DLj, and the data lead line DA(n+2) can be connected to the first sub-pixel through the data line DLj+2.

[0094] In some examples, the data lead line DA(n+1) can be connected to the data line DLj+1, and the connected column of sub-pixels includes the third sub-pixel (for example, including the first green sub-pixel G1 and the second green sub-pixel G2 arranged at intervals); the data lead line DA(n+3) can be connected through the data line DLj+3, and the connected column of sub-pixels includes the third sub-pixel (for example, including the first green sub-pixel G1 and the second green sub-pixel G2 arranged at intervals).

[0095] In some examples, the first test control line SWR can be configured to control the first test transistor T1 in the first test circuit 401 and the fifth test transistor T5 in the third test circuit 403 to be turned on, and the second test control line SWB can be configured to control the second test transistor T2 in the first test circuit 401 and the fourth test transistor T4 in the third test circuit 403 to be turned on, so that the first type of test data signals transmitted by the first test data line DR and the second test data line DB can be written to different data lines through the data lead-out lines.

[0096] In some examples, the first type of test data signal may include: a first test data signal provided by a first test data line, a second test data signal provided by a second test data line, and a third test data signal provided by a third test data line. The first test circuit 401 can be configured to provide a first type of test data signal (such as a first test data signal) to a first sub-pixel of an e-th row of pixel units in a column of pixel units in a first time period, and to provide a first type of test data signal (such as a second test data signal) to a second sub-pixel of an e+1-th row of pixel units in the column of pixel units in a second time period; the third test circuit 403 can be configured to provide a first type of test data signal (such as a first test data signal) to a first sub-pixel of an e+1-th row of pixel units in the column of pixel units in a first time period, and to provide a first type of test data signal (such as a second test data signal) to a second sub-pixel of an e-th row of pixel units in the column of pixel units in a second time period; the second test circuit 402 is configured to provide a first type of test data signal (such as a third test data signal) to a third sub-pixel in a column of pixel units in the column; and the fourth test circuit 404 is configured to provide a first type of test data signal (such as a third test data signal) to a third sub-pixel in another column of pixel units in the column.

[0097] In some examples, when performing a display test (e.g., a color display test), a control device can provide a turn-on signal to the first test control line SWR (or the second test control line SWB) and the third test control line SWG, and provide the required first-type test data signals to multiple test data lines (e.g., including the first test data line DR, the second test data line DB, and the third test data line DG), so that multiple data lines in the display area obtain the first-type test data signals, and determine whether there are defective sub-pixels and locate the defective sub-pixels through the color of the display screen.

[0098] In some examples, in order to achieve a narrow frame design, the data lines in the display area are divided into two categories. The first type of data lines can be directly connected to the data lead-out lines in the first frame area, and the second type of data lines can be connected to the data lead-out lines in the first frame area through the data connection lines set in the display area, thereby effectively reducing the length of the first sub-area along the first direction, thereby greatly reducing the size of the lower frame of the display substrate. In the process of switching the second type of data lines through the data connection lines, the order of the data lead-out lines in the first frame area will be disrupted, so that the order of the data lead-out lines in the first frame area is different from the order of the data lines in the display area. In order to be compatible with the integrated circuit, the order of the data signals provided by the multiple first contact pads in the first signal access area can adapt to the arrangement order of the data signals in the display area after being switched by the data connection lines, that is, the data signals provided by the multiple first contact pads can have a first order, and a data switching is performed once in the second sub-area, so that the order of the data signals changes, such as having a second order, and a data switching is performed again in the first sub-area, so that the order of the data signals changes back to the first order, so that the data lines in the display area can receive the required data signals. Based on this, the order of the first type of test data signals provided by the test circuit arranged in the second sub-area is the aforementioned second order, and is provided to the data lines of the display area after being changed back to the first order through signal switching in the first sub-area.

[0099] Figure 5 An equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 6 It is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Fig. 7A for Figure 6 A schematic diagram of a first semiconductor layer in FIG.

[0100] Figure 7B for Figure 6 A schematic diagram of a first semiconductor layer and a first gate metal layer in FIG. Figure 7C for Figure 6 Schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in FIG. This example shows the film layer structure of the substrate as shown in FIG. Figure 2B The order of the first-type test signals provided by the plurality of first-type test circuit groups in this example may be the aforementioned second order.

[0101] In some examples, such as Figure 5 and Figure 6 As shown, the display substrate may include: a plurality of first type test circuit groups located in a circuit setting area of ​​the first frame region and arranged along the second direction D2. Figure 5 and Figure 6Six first-category test circuit groups are used as an example for illustration. Each first-category test circuit group may include a first-category test circuit. The first-category test circuit may include: a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404. The first test circuit 401, the second test circuit 402, the fourth test circuit 404, and the third test circuit 403 in at least one first-category test circuit may be arranged in sequence along the first direction D1 in a direction away from the display area; the third test circuit 403, the second test circuit 402, the fourth test circuit 404, and the first test circuit 401 in at least one first-category test circuit may be arranged in sequence along the first direction D1 in a direction away from the display area.

[0102] Below Figure 5 and Figure 6 The first first-type test circuit group shown in FIG. 1 is used as an example for explanation. The first test transistor T1 and the second test transistor T2 of the first test circuit 401 of the first-type test circuit of the first-type test circuit group, the third test transistor T3 of the second test circuit 402, the sixth test transistor T6 of the fourth test circuit 404, the fourth test transistor T4 and the fifth test transistor T5 of the third test circuit 403 can be arranged in sequence in the first direction D1, for example, arranged in sequence along the direction away from the display area AA.

[0103] In some examples, the plurality of data lead lines may be divided into a plurality of groups of data lead lines, each group of data lead lines may include the following four: a first data lead line 51, a second data lead line 52, a third data lead line 53, and a fourth data lead line 54. For example, a group of data lead lines may be configured to provide a data signal or a test data signal to a column of pixel units.

[0104] In some examples, the first border area may also be provided with a plurality of first test control lines (e.g., four first test control lines SWR1, SWR2, SWR3, and SWR4), a plurality of second test control lines (e.g., three second test control lines SWB1, SWB2, SWB3), a plurality of third test control lines (e.g., including two third test control lines SWG1, SWG2), a plurality of first test data lines (e.g., two first test data lines DR1, DR2), a plurality of second test data lines (e.g., two second test data lines DB1, DB2), and a third test data line DG. The four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines, and one third test data line in the circuit setting area may be of the same layer structure and all extend along the second direction D2.

[0105] In some examples, the first second test control line SWB1, the first first test control line SWR1, the first first test data line DR1, the first second test data line DB1, the second second test control line SWB2, the second first test control line SWR2, the first third test control line SWG1, the third test data line DG, the second third test control line SWG2, the second second test data line DR2, the third first test control line SWR3, the third second test control line SWB3, the fourth first test control line SWR4 and the second second test data line DB2 can be arranged in the first direction D1 along the direction away from the display area. Among them, the first second test control line SWB1 and the first first test control line SWR1 can be adjacent in the first direction D1, the first first test data line DR1 and the first second test data line DB1 can be adjacent in the first direction D1, the second second test control line SWB2, the second first test control line SWR2 and the first third test control line SWG1 are adjacent in the first direction D1, the second third test control line SWG2 and the second first test data line DR2 are adjacent in the first direction D1, and the third first test control line SWR3, the third second test control line SWB3 and the fourth first test control line SWR4 can be adjacent in the first direction D1.

[0106] In some examples, in the first first-type test circuit group, the first test transistor T1 may be located between the first first test control line SWR1 and the first first test data line DR1, and connected to the first first test control line SWR1 and the first first test data line DR1; the second test transistor T2 may be located between the first second test data line DB1 and the second second test control line SWB2, and connected to the first second test data line DB1 and the second second test control line SWB2; the third test transistor T3 may be located between the first third test control line SWG1 and the third test data line DG, and connected to the first third test control line SWG1 and the first third test control line SWG2; The third test data line DG is connected; the sixth test transistor T6 can be located between the third test data line DG and the second third test control line SWG2, and is connected to the third test data line DG and the second third test control line SWG2; the fourth test transistor T4 can be located between the second first test data line DR2 and the third first test control line SWR3, and is connected to the second first test data line DR2 and the third second test control line SWB3; the fifth test transistor T5 can be located between the fourth first test control line SWR4 and the second second test data line DB2, and is connected to the fourth first test control line SWR4 and the second second test data line DB2.

[0107] In some examples, such as Fig. 7A As shown, the first semiconductor layer of the circuit setting area of ​​the first frame region may include: an active layer T10 of a first test transistor T1, an active layer T20 of a second test transistor T2, an active layer T30 of a third test transistor T3, an active layer T40 of a fourth test transistor T4, an active layer T50 of a fifth test transistor T5, and an active layer T60 of a sixth test transistor T6. The active layer T10 of the first test transistor T1, the active layer T20 of the second test transistor T2, and the active layer T30 of the third test transistor T3 of a first type test circuit group may be aligned along the first direction D1, the active layer T60 of the sixth test transistor T6, the active layer T40 of the fourth test transistor T4, and the active layer T50 of the fifth test transistor T5 may be arranged in sequence along the first direction D1, and the active layer T60 of the sixth test transistor T6 and the active layer T30 of the third test transistor T3 may be slightly misaligned in the second direction D2.

[0108] In some examples, such as Figure 7B As shown, the first gate metal layer of the circuit setting area of ​​the first border area may include: a gate T11 of a first test transistor T1, a gate T21 of a second test transistor T2, a gate T31 of a third test transistor T3, a gate T41 of a fourth test transistor T4, a gate T51 of a fifth test transistor T5, a gate T61 of a sixth test transistor T6, a plurality of data lead lines (for example, including a second data lead line 52 and a fourth data lead line 54), and a plurality of connection blocks (for example, including a first connection block 311 and a second connection block 312).

[0109] In some examples, the orthographic projections of the gate T11 of the first test transistor T1, the gate T31 of the third test transistor T3, and the gate T51 of the fifth test transistor T5 on the substrate may be roughly in the shape of a horizontal flip of the letter L, the orthographic projections of the gate T21 of the second test transistor T2 and the gate T41 of the fourth test transistor T4 on the substrate may be roughly in the shape of the letter L rotated 180 degrees clockwise, and the orthographic projection of the gate T61 of the sixth test transistor T6 on the substrate may be roughly in the shape of a vertical flip of the letter L.

[0110] In some examples, the second data lead line 52 and a first connection block 311 may be an integral structure, and the orthographic projection of the first connection block 311 on the substrate may be located on a side of the active layer T30 of the third test transistor T3 close to the second test transistor T2 in the first direction D1. The fourth data lead line 54 and a second connection block 312 may be an integral structure, and the orthographic projection of the second connection block 312 on the substrate may be located on a side of the active layer T60 of the sixth test transistor T6 far from the third test transistor T3 in the first direction D1.

[0111] In some examples, the second data lead line 52 is in a zigzag shape extending along the first direction D1, and the bending position is located between the second test transistor T2 and the third test transistor T3. The fourth data lead line 54 is in a straight line shape extending along the first direction D1.

[0112] In some examples, such as Figure 7C As shown, the second gate metal layer of the circuit setting area of ​​the first border area may include: multiple data lead lines (for example, including a first data lead line 51 and a third data lead line 53), multiple connection blocks (for example, including a third connection block 313, a fourth connection block 314, a fifth connection block 315 and a sixth connection block 316).

[0113] In some examples, the first data lead line 51 may be a straight line extending along the first direction D1 and located at one side of a first type test circuit group along the second direction D2. The first data lead line 51 may be an integral structure with the third connection block 313 and the fourth connection block 314, the third connection block 313 is connected to the side of the first data lead line 51 close to the first test transistor T1, and the third connection block 313 may be located at a side of the active layer T10 of the first test transistor T1 away from the second test transistor T2; the fourth connection block 314 may be connected to the side of the first data lead line 51 close to the second test transistor T2, and the fourth connection block 314 may be located at a side of the active layer T20 of the second test transistor T2 away from the first test transistor T1.

[0114] In some examples, the third data lead line 53 may be in the shape of a zigzag extending along the first direction D1, and may be an integral structure with the fifth connection block 315 and the sixth connection block 316. The bending position of the third data lead line 53 may be located between the active layer T30 of the third test transistor T3 and the active layer T60 of the sixth test transistor T6. The fifth connection block 315 is connected to a side of the third data lead line 53 close to the fourth test transistor T4, and the fifth connection block 315 may be located on a side of the active layer T40 of the fourth test transistor T4 close to the fifth test transistor T5; the sixth connection block 316 may be connected to a side of the third data lead line 53 close to the fifth test transistor T5, and the sixth connection block 316 may be located on a side of the active layer T50 of the fifth test transistor T5 close to the fourth test transistor T4.

[0115] In some examples, the first data lead line 51, the second data lead line 52, the third data lead line 53, and the fourth data lead line 54 may be arranged along the second direction D2. The active layer T10 of the first test transistor T1 and the active layer T20 of the second test transistor T2 may be located between the first data lead line 51 and a portion of the second data lead line 52, the active layer T30 of the third test transistor T3 may be located between another portion of the second data lead line 52 and a portion of the third data lead line 53, and the active layer T60 of the sixth test transistor T6, the active layer T40 of the fourth test transistor T4, and the active layer T50 of the fifth test transistor T5 may be located between another portion of the third data lead line 53 and the fourth data lead line 54.

[0116] In some examples, such as Figure 6 As shown, the first source-drain metal layer of the circuit setting area of ​​the first frame area may include: a plurality of test control lines (for example, including first test control lines SWR1, SWR2, SWR3, SWR4, second test control lines SWB1, SWB2, SWB3, and third test control lines SWG1, SWG2), a plurality of test data lines (for example, including first test data lines DR1, DR2, second test data lines DB1, DB2, and third test data lines DG), and a plurality of connection electrodes (for example, including first connection electrodes 411, second connection electrodes 412, third connection electrodes 413, fourth connection electrodes 414, fifth connection electrodes 415, and sixth connection electrodes 416). The orthographic projections of the first connection electrodes 411 to the sixth connection electrodes 416 on the substrate may be roughly strip-shaped extending along the first direction D1.

[0117] In some examples, the first connection electrode 411 can be connected to the third connection block 313 and the second region of the active layer T10 of the first test transistor T1; since the third connection block 313 and the first data lead line 51 are an integral structure, the first test transistor T1 is electrically connected to the first data lead line 51. The first region of the active layer T10 of the first test transistor T1 can be connected to the first first test data line DR1. The gate T11 of the first test transistor T1 can be connected to the first first test control line SWR1.

[0118] In some examples, the second connection electrode 412 can be connected to the fourth connection block 314 and the second region of the active layer T20 of the second test transistor T2. Since the fourth connection block 314 and the first data lead line 51 are an integral structure, the second test transistor T2 is electrically connected to the first data lead line 51. The first region of the active layer T20 of the second test transistor T2 can be connected to the first second test data line DB1. The gate T21 of the second test transistor T2 can be connected to the second second test control line SWB2.

[0119] In some examples, the third connection electrode 413 can be connected to the first connection block 311 and the second region of the active layer T30 of the third test transistor T3. Since the first connection block 311 and the second data lead line 52 are an integral structure, the third test transistor T3 is electrically connected to the second data lead line 52. The first region of the active layer T30 of the third test transistor T3 can be connected to the third test data line DG. The gate T31 of the third test transistor T3 can be connected to the first third test control line SWG1.

[0120] In some examples, the sixth connection electrode 416 can be connected to the second connection block 312 and the second region of the active layer T60 of the sixth test transistor T6. Since the second connection block 312 and the fourth data lead line 54 are an integral structure, the electrical connection between the sixth test transistor T6 and the fourth data lead line 54 can be achieved. The first region of the active layer T60 of the sixth test transistor T6 can be connected to the third test data line DG. The gate T61 of the sixth test transistor T6 can be connected to the second third test control line SWG2.

[0121] In some examples, the fourth connection electrode 414 can be connected to the fifth connection block 315 and the second region of the active layer T40 of the fourth test transistor T4. Since the fifth connection block 315 and the third data lead line 53 are an integral structure, the electrical connection between the fourth test transistor T4 and the third data lead line 53 can be achieved. The first region of the active layer T40 of the fourth test transistor T4 can be connected to the second first test data line DR2. The gate T41 of the fourth test transistor T4 can be connected to the third second test control line SWB3.

[0122] In some examples, the fifth connection electrode 415 can be connected to the sixth connection block 316 and the second region of the active layer T50 of the fifth test transistor T5. Since the sixth connection block 316 and the third data lead line 53 are an integral structure, the electrical connection between the fifth test transistor T5 and the third data lead line 53 can be achieved. The first region of the active layer T50 of the fifth test transistor T5 can be connected to the second second test data line DB2. The gate T51 of the fifth test transistor T5 can be connected to the fourth first test control line SWR4.

[0123] In this example, the six transistors of the first type of test circuit are arranged along the first direction, which can save the wiring space occupied by the first type of test circuit in the second direction, and is conducive to increasing the wiring arrangement space on both sides of the circuit setting area in the second direction, facilitating the setting of the remaining wiring.

[0124] Figure 8 Another equivalent circuit diagram of multiple first-type test circuit groups according to at least one embodiment of the present disclosure is shown. Fig. 9It is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Fig. 10A for Fig. 9 A schematic diagram of a first semiconductor layer and a first gate metal layer in FIG. Fig. 10B for Fig. 9 Schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in FIG. This example shows the film layer structure of the substrate as shown in FIG. Figure 2B The order of the first-type test data signals provided by the plurality of first-type test circuit groups in this example may be the aforementioned second order. Figure 8 and Fig. 9 Six first-type test circuit groups are used as examples for illustration, and each first-type test circuit group includes a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404. The first test circuit 401 may include two first test transistors T1a and T1b, two second test transistors T2a and T2b, the second test circuit 402 may include two third test transistors T3a and T3b, the third test circuit 403 may include two fourth test transistors T4a and T4b, two fifth test transistors T5a and T5b, and the fourth test circuit 404 may include two sixth test transistors T6a and T6b.

[0125] Below Figure 8 and Fig. 9 The first first-category test circuit group is used as an example for explanation. The first test circuit 401, the second test circuit 402, the fourth test circuit 404 and the third test circuit 403 of the first-category test circuit of the first-category test circuit group can be arranged in sequence along the first direction D1 in a direction away from the display area AA. Among them, the first test transistors T1a and T1b, the second test transistors T2a and T2b, the third test transistors T3a and T3b, the sixth test transistors T6a and T6b, the fourth test transistors T4a and T4b, and the fifth test transistors T5a and T5b can be arranged in sequence along the first direction D1 in a direction away from the display area AA.

[0126] In some examples, the plurality of data lead lines may be divided into a plurality of groups of data lead lines, each group of data lead lines may include: a first data lead line 51 , a second data lead line 52 , a third data lead line 53 , and a fourth data lead line 54 .

[0127] In some examples, the first border area may also be provided with a plurality of first test control lines (e.g., two first test control lines SWR1 and SWR2), a plurality of second test control lines (e.g., four second test control lines SWB1, SWB2, SWB3, and SWB4), a plurality of third test control lines (e.g., two third test control lines SWG1 and SWG2), a plurality of first test data lines (e.g., four first test data lines DR1, DR2, DR3, and DR4), a plurality of second test data lines (e.g., four second test data lines DB1, DB2, DB3, and DB4), and a plurality of third test data lines (e.g., three third test data lines DG1, DG2, and DG3). The two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines, and three third test data lines in the circuit setting area may be of the same layer structure and all extend along the second direction D2.

[0128] In some examples, the first second test control line SWB1, the first first test data line DR1, the second first test data line DR2, the first first test control line SWR1, the second second test control line SWB2, the first second test data line DB1, the second second test data line DB2, the first third test control line SWG1, the first third test data line DG1, the second third test data line DG2, the third third test data line DG3, the second third test control line SWG2, the third second test control line SWB3, the third first test data line DR3, the fourth first test data line DR4, the second first test control line SWR2, the fourth second test control line SWB4, the third second test data line DB3 and the fourth second test data line DB4 can be arranged in the first direction D1 along a direction away from the display area. Among them, the first second test control line SWB1 and the first first test data line DR1 can be adjacent in the first direction D1, the second first test data line DR2, the first first test control line SWR1, the second second test control line SWB2, and the first second test data line DB1 can be adjacent in the first direction D1, the second second test data line DB2, the first third test control line SWG1 and the first third test data line DG1 can be adjacent in the first direction D1, the third third test data line DG3, the second third test control line SWG2, the third second test control line SWB3, and the third first test data line DR3 can be adjacent in the first direction D1, and the fourth first test data line DR4, the second first test control line SWR2, the fourth second test control line SWB4, and the third second test data line DB3 can be adjacent in the first direction D1.

[0129] In some examples, such as Fig. 10A and Fig. 10B As shown, the active layer T10a of the first test transistor T1a, the active layer T10b of the first test transistor T1b, the active layer T20a of the second test transistor T2a, and the active layer T20b of the second test transistor T2b can be aligned along the first direction D1. The gate T11a of the first test transistor T1a and the gate T11b of the first test transistor T1b can be an integrated structure. The gate T21a of the second test transistor T2a and the gate T21b of the second test transistor T2b can be an integrated structure.

[0130] In some examples, the active layer T30a of the third test transistor T3a and the active layer T30b of the third test transistor T3b may be aligned along the first direction D1. The gate T31a of the third test transistor T3a and the gate T31b of the third test transistor T3b may be an integral structure.

[0131] In some examples, the active layer T60a of the sixth test transistor T6a and the active layer T60b of the sixth test transistor T6b may be aligned along the first direction D1. The gate T61a of the sixth test transistor T6a and the gate T61b of the sixth test transistor T6b may be an integral structure.

[0132] In some examples, the active layer T40a of the fourth test transistor T4a, the active layer T40b of the fourth test transistor T4b, the active layer T50a of the fifth test transistor T5a, and the active layer T50b of the fifth test transistor T5b may be aligned along the first direction D1. The gate T41a of the fourth test transistor T4a and the gate T41b of the fourth test transistor T4b may be an integral structure. The gate T51a of the fifth test transistor T5a and the gate T51b of the fifth test transistor T5b may be an integral structure.

[0133] In some examples, the first data lead line 51 is located in the second gate metal layer and is an integral structure with the third connection block 313 and the fourth connection block 314. The orthographic projection of the third connection block 313 on the substrate may be located between the active layer T10a of the first test transistor T1a and the active layer T10b of the first test transistor T1b. The orthographic projection of the fourth connection block 314 on the substrate may be located between the active layer T20a of the second test transistor T2a and the active layer T20b of the second test transistor T2b.

[0134] In some examples, a first region of the active layer T10a of the first test transistor T1a may be connected to a first first test data line DR1, a second region of the active layer T10b of the first test transistor T1b may be connected to a second first test data line DR2, and gates of the first test transistor T1a and the first test transistor T1b may be connected to a first first test control line SWR1. A second region of the active layer T10a of the first test transistor T1a and a second region of the active layer T10b of the first test transistor T1b may be connected to the third connection block 313 via a seventh connection electrode 417 located at the first source-drain metal layer.

[0135] In some examples, a first region of the active layer T20a of the second test transistor T2a may be connected to the first second test data line DB1, and a first region of the active layer T20b of the second test transistor T2b may be connected to the second second test data line DB2. The gates of the second test transistor T2a and the second test transistor T2b may be connected to the second second test control line SWB2. A second region of the active layer T20a of the second test transistor T2a and a second region of the active layer T20b of the second test transistor T2b may be connected to the fourth connection block 314 via an eighth connection electrode 418 located at the first source-drain metal layer.

[0136] In some examples, the second data lead line 52 may be located in the first gate metal layer and may be integrally formed with the first connection block 311. The orthographic projection of the first connection block 311 on the substrate may be located between the active layer T30a of the third test transistor T3a and the active layer T30b of the third test transistor T3b.

[0137] In some examples, a first region of the active layer T30a of the third test transistor T3a may be connected to the first third test data line DG1, and a first region of the active layer T30b of the third test transistor T3b may be connected to the second third test data line DG2. The gates of the third test transistors T3a and T3b may be connected to the first third test control line SWG1. A second region of the active layer T30a of the third test transistor T3a and a second region of the active layer T30b of the third test transistor T3b may be connected to the first connection block 311 via a ninth connection electrode 419 located at the first source-drain metal layer.

[0138] In some examples, the third data lead line 53 may be located at the second gate metal layer and may be an integral structure with the fifth connection block 315 and the sixth connection block 316. The orthographic projection of the fifth connection block 315 on the substrate may be located between the active layer T40a of the fourth test transistor T4a and the active layer T40b of the fourth test transistor T4b. The orthographic projection of the sixth connection block 316 on the substrate may be between the active layer T50a of the fifth test transistor T5a and the active layer T50b of the fifth test transistor T5b.

[0139] In some examples, the first region of the active layer T40a of the fourth test transistor T4a may be connected to the third first test data line DR3, and the first region of the active layer T40b of the fourth test transistor T4b may be connected to the fourth first test data line DR4. The gates of the fourth test transistors T4a and T4b may be connected to the third second test control line SWB3. The second region of the active layer T40a of the fourth test transistor T4a and the second region of the active layer T40b of the fourth test transistor T4b may be connected to the fifth connection block 315 via the tenth connection electrode 420 located at the first source-drain metal layer.

[0140] In some examples, the first region of the active layer T50a of the fifth test transistor T5a can be connected to the third second test data line DB3, and the first region of the active layer T50b of the fifth test transistor T5b can be connected to the fourth second test data line DB4. The gates of the fifth test transistors T5a and T5b can be connected to the second first test control line SWR2. The second region of the active layer T50a of the fifth test transistor T5a and the second region of the active layer T50b of the fifth test transistor T5b can be connected to the sixth connection block 316 through the eleventh connection electrode 421 located at the first source-drain metal layer.

[0141] In some examples, the fourth data lead line 54 may be located in the first gate metal layer and may be integrally formed with the second connection block 312. The orthographic projection of the second connection block 312 on the substrate may be located between the active layer T60a of the sixth test transistor T6a and the active layer T60b of the sixth test transistor T6b.

[0142] In some examples, the first region of the active layer T60a of the sixth test transistor T6a can be connected to the second third test data line DG2, and the first region of the active layer T60b of the sixth test transistor T6b can be connected to the third third test data line DG3. The gates of the sixth test transistors T6a and T6b can be connected to the second third test control line SWG2. The second region of the active layer T60a of the sixth test transistor T6a and the second region of the active layer T60b of the sixth test transistor T6b can be connected to the second connection block 312 through the twelfth connection electrode 422 located at the first source-drain metal layer.

[0143] In some examples, Fig. 9 In the first first-category test circuit group, the first test transistors T1a and T1b may be located between the first first test data line DR1 and the second first test data line DR2; the second test transistors T2a and T2b may be located between the first second test data line DB1 and the second second test data line DB2; the third test transistors T3a and T3b may be located between the first third test data line DG1 and the second third test data line DG2; the sixth test transistors T6a and T6b may be located between the second third test data line DG2 and the third third test data line DG3; the fourth test transistors T4a and T4b may be located between the third first test data line DR3 and the fourth first test data line DR4; and the fifth test transistors T5a and T5b may be located between the third second test data line DB3 and the fourth second test data line DB4.

[0144] In this example, the first type of test circuit includes twelve transistors, and the twelve transistors are arranged along the first direction, which can save the wiring space occupied by the first type of test circuit in the second direction and ensure the stability of the test circuit. The rest of the description of the display substrate of this example can refer to the description of the above embodiment, so it will not be repeated here.

[0145] Fig.11 Another equivalent circuit diagram of multiple first-type test circuit groups according to at least one embodiment of the present disclosure is shown. Fig.12 It is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Fig.13 for Fig.12 Schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in FIG. This example shows the film layer structure of the substrate as shown in FIG. Figure 2B The example is used for explanation. The order of the first type of test data signals provided by the test circuit of this example can be the same as the order of the data signals provided by the first contact pad of the first signal access area, that is, in this example, the data connection line can be set in the display area, and the order of the data signals required by the data line can be the same as the order of the data signals provided by the data lead line.

[0146] In some examples, such as Figures 11 to 13 As shown, the display substrate may include: a plurality of first-type test circuit groups located in a circuit setting area of ​​a first frame region and arranged along a second direction D2, Fig.11 and Fig.12Four first-category test circuit groups are used as an example for illustration. Each first-category test circuit group may include two first-category test circuits arranged along the first direction D1. Each first-category test circuit may include: a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404. In a first-category test circuit group, the first first test circuit 401, the first second test circuit 402, the first fourth test circuit 404, the first third test circuit 403, the second second test circuit 402, the second fourth test circuit 404, the second first test circuit 401, and the second third test circuit 403 may be arranged in sequence along the first direction D1.

[0147] In some examples, the plurality of data lead lines may be divided into a plurality of groups of data lead lines, each group of data lead lines may include the following eight data lead lines: a first data lead line 51, a second data lead line 52, a third data lead line 53, a fourth data lead line 54, a fifth data lead line 55, a sixth data lead line 56, a seventh data lead line 57, and an eighth data lead line 58. A first type test circuit group of this example may be configured to provide a first type test data signal to two columns of pixel circuits.

[0148] In some examples, the first border area may be provided with a plurality of first test control lines (e.g., four first test control lines SWR1, SWR2, SWR3, and SWR4), a plurality of second test control lines (e.g., four second test control lines SWB1, SWB2, SWB3, and SWB4), a plurality of third test control lines (e.g., including four third test control lines SWG1, SWG2, SWG3, and SWG4), a plurality of first test data lines (e.g., four first test data lines DR1, DR2, DR3, and DR4), a plurality of second test data lines (e.g., four second test data lines DB1, DB2, DB3, and DB4), and a plurality of third test data lines (e.g., including two third test data lines DG1 and DG2). The four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines, and two third test data lines in the circuit setting area may be of the same layer structure and all extend along the second direction D2.

[0149] In some examples, the first first test control line SWR1, the first first test data line DR1, the first second test data line DB1, the first second test control line SWB1, the first third test control line SWG1, the first third test data line DG1, the second third test control line SWG2, the second second test control line SWB2, the second first test data line DR2, the second second test data line DB2, the second second test control line SWR2, the third third test control line SWG3, the second third test data line DG2, the fourth fourth test control line SWG4, the third first test control line SWR3, the third first test data line DR3, the third second test data line DB3, the third second test control line SWB3, the fourth second test control line SWB4, the fourth first test data line DR4, the fourth second test data line DB4, and the fourth first test control line SWR4 can be arranged along the first direction D1, for example, in a direction away from the display area.

[0150] Among them, the first first test data line DR1 and the first second test data line DB1 can be adjacent in the first direction D1, the first second test control line SWB1 and the first third test control line SWG1 can be adjacent in the first direction D1, the second third test control line SWG2 and the second second test control line SWB2 can be adjacent in the first direction D1, the second first test data line DR2 and the second second test data line DB2 can be adjacent in the first direction D1, the second first test control line SWR2 and the third third test control line SWG3 can be adjacent in the first direction D1, the fourth third test control line SWG4 and the third first test control line SWR3 can be adjacent in the first direction D1, the third first test data line DR3 and the third second test data line DB3 can be adjacent in the first direction D1, the third second test control line SWB3 and the fourth second test control line SWB4 can be adjacent in the first direction D1, and the fourth first test data line DR4 and the fourth second test data line DB4 can be adjacent in the first direction D1.

[0151] In some examples, a first test transistor T1 may be set between the first first test control line SWR1 and the first first test data line DR1, a second test transistor T2 may be set between the first second test data line DB1 and the first second test control line SWB1, a third test transistor T3 may be set between the first third test control line SWG1 and the first third test data line DG1, a sixth test transistor T6 may be set between the first third test data line DG1 and the second third test control line SWG2, a fourth test transistor T4 may be set between the second second test control line SWB2 and the second first test data line DR2, and a fifth test transistor T5 may be set between the second second test data line DB2 and the second first test control line SWR2. A third test transistor T3 may be set between the third third test control line SWG3 and the second third test data line DG2, a sixth test transistor T6 may be set between the second third test data line DG2 and the fourth third test control line SWG4, a first test transistor T1 may be set between the third first test control line SWR3 and the third first test data line DR3, a second test transistor T2 may be set between the third second test data line DB3 and the third second test control line SWB3, a fourth test transistor T4 may be set between the fourth second test control line SWB4 and the fourth first test data line DR4, and a fifth test transistor T5 may be set between the fourth first test data line DR4 and the fourth first test control line SWR4.

[0152] In some examples, the first data lead line 51 may be an integral structure with a third connection block 313 and a fourth connection block 314, the third connection block 313 being connected to the first first test transistor T1, and the fourth connection block 314 being connected to the first second test transistor T2. The second data lead line 52 may be an integral structure with a first connection block 311, and the first connection block 311 being connected to the first third test transistor T3. The third data lead line 53 may be an integral structure with a fifth connection block 315 and a sixth connection block 316, the fifth connection block 315 being connected to the first fourth test transistor T4, and the sixth connection block 316 being connected to the first fifth test transistor T5. The fourth data lead line 54 may be an integral structure with a second connection block 312, and the second connection block 312 being connected to the first sixth test transistor T6. The fifth data lead line 55 may be an integral structure with another third connection block 313 and another fourth connection block 314, the third connection block 313 is connected to the second first test transistor T1, and the fourth connection block 314 is connected to the second second test transistor T2. The sixth data lead line 56 may be an integral structure with another first connection block 311, and the first connection block 311 is connected to the second third test transistor T3. The seventh data lead line 57 may be an integral structure with another fifth connection block 315 and another sixth connection block 316, the fifth connection block 315 is connected to the second fourth test transistor T4, and the sixth connection block 316 is connected to the second fifth test transistor T5. The eighth data lead line 58 may be an integral structure with another second connection block 312, and the second connection block 312 is connected to the second sixth test transistor T6.

[0153] In this example, each first-type test circuit includes six transistors, and the twelve transistors of the two first-type test circuits are arranged along the first direction, which can save the wiring space occupied by the first-type test circuit group in the second direction, and is conducive to increasing the wiring arrangement space on both sides of the circuit setting area in the second direction, which is convenient for the setting of the remaining wiring. The rest of the description of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0154] Fig.14Another equivalent circuit diagram of a plurality of first-class test circuit groups of at least one embodiment of the present disclosure. The order of the first-class test data signals provided by the test circuit of this example can be the same as the order of the data signals provided by the first contact pad of the first signal access area, that is, in this example, the data connection line can be set in the display area, and the order of the data signals required by the data line can be the same as the order of the data signals provided by the data lead line. For example, the first data lead line 51 and the third data lead line 53 can each be configured to provide the first-class test data signal to a column of sub-pixels including the first sub-pixel and the second sub-pixel, and the second data lead line 52 and the fourth data lead line 54 can each be configured to provide the first-class test data signal to a column of third sub-pixels.

[0155] In some examples, such as Fig.14 As shown, each first-category test circuit group may include a first-category test circuit, and the first test circuit 401, the second test circuit 402, the fourth test circuit 404, and the third test circuit 403 of the first-category test circuit may be along the first direction D1. Two first test control lines SWR1 and SWR2, two second test control lines SWB1 and SWB2, two third test control lines SWG1 and SWG2, two first test data lines DR1 and DR2, two second test data lines DB1 and DB2, and one third test data line DG may be of the same layer structure and extend at least along the second direction D2.

[0156] In some examples, the first first test control line SWR1, the first first test data line DR1, the first second test data line DB1, the first second test control line SWB1, the first third test control line SWG1, the third test data line DG, the second third test control line SWG2, the second first test data line DR2, the second second test control line SWB2, the second first test control line SWR2 and the second second test data line DB2 can be arranged sequentially along the first direction D1.

[0157] Among them, the first test transistor T1 can be located between the first first test control line SWR1 and the first first test data line DR1, the second test transistor T2 can be located between the first second test data line DB1 and the first second test control line SWB1, the third test transistor T3 can be located between the first third test control line SWG1 and the third test data line DG, the sixth test transistor T6 can be located between the third test data line DG and the second third test control line SWG2, the fourth test transistor T4 can be located between the second first test data line DR2 and the second second test control line SWB2, and the fifth test transistor T5 can be located between the second first test control line SWR2 and the second second test data line DB2.

[0158] In this example, the six transistors of the first type of test circuit are arranged along the first direction, which can save the wiring space occupied by the first type of test circuit group along the second direction. The rest of the description of this example can refer to the description of the above embodiment, so it will not be repeated here.

[0159] Fig.15 An equivalent circuit diagram of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure. Fig.16 It is a plan view of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure. Fig.17 for Fig.16 Schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in FIG.

[0160] In some examples, a plurality of second-class test circuit groups may be provided in the first border area, and the plurality of second-class test circuit groups may be located on one side of the plurality of first-class test circuit groups away from the display area. The second-class test circuit group may include: at least one second-class test circuit arranged along the first direction D1. The second-class test circuit may include: a fifth test circuit 405, a sixth test circuit 406, a seventh test circuit 407, and an eighth test circuit 408. The fifth test circuit 405 and the seventh test circuit 407 may each be configured to provide a second-class test data signal to a column of sub-pixels including the first sub-pixel and the second sub-pixel, and the sixth test circuit 406 and the eighth test circuit 408 may each be configured to provide a second-class test data signal to a column of third sub-pixels. For example, the fifth test circuit 405 may be connected to the first data lead line 51, the sixth test circuit 406 may be connected to the second data lead line 52, the seventh test circuit 407 may be connected to the third data lead line 53, and the eighth test circuit 408 may be connected to the fourth data lead line 54.

[0161] In some examples, the fifth test circuit 405 may include: at least one seventh test transistor T7. The sixth test circuit 406 may include: at least one eighth test transistor T8. The seventh test circuit 407 may include at least one ninth test transistor T9. The eighth test circuit 408 may include at least one tenth test transistor T10. The tenth test transistor T10, the ninth test transistor T9, the eighth test transistor T8, and the seventh test transistor T7 of a second type test circuit group may be arranged in sequence along the first direction D1 in a direction away from the display area.

[0162] In some examples, the first border area may be provided with a plurality of fourth test control lines (e.g., two fourth test control lines SWD1 and SWD2), a plurality of fourth test data lines (e.g., two fourth test data lines DD1-1 and DD1-2), and two fifth test data lines (e.g., two fifth test data lines DD2-1 and DD2-2). The fourth test data line may be configured to provide a fourth test data signal, and the fifth test data line may be configured to provide a fifth test data signal. The second type of test circuit may be configured to provide a second type of test data signal (e.g., including a fourth test data signal and a fifth test data signal) to a plurality of data lines during a black and white display test to perform a black and white display test.

[0163] In some examples, the gates of the seventh test transistor T7, the eighth test transistor T8, the ninth test transistor T9, and the tenth test transistor T10 are all connected to the fourth test control line. For example, the gate T71 of the seventh test transistor T7 and the gate T81 of the eighth test transistor T8 may be an integral structure and connected to the second fourth test control line SWD2 located at the first source-drain metal layer. The first region of the active layer T70 of the seventh test transistor T7 and the fourteenth connection electrode 424 located at the second gate metal layer may be connected through the twenty-first connection electrode 431 located at the first source-drain metal layer, the first region of the active layer T80 of the eighth test transistor T8 and the fourteenth connection electrode 424 located at the second gate metal layer may be connected through the twentieth connection electrode 430 located at the first source-drain metal layer, and the fourteenth connection electrode 424 may be connected to the second fourth test data line DD1-2 located at the first source-drain metal layer. The second region of the active layer T70 of the seventh test transistor T7 may be connected to the first data lead-out line 51 located at the second gate metal layer through the twenty-second connection electrode 432 located at the first source-drain metal layer. The second region of the active layer T80 of the eighth test transistor T8 may be connected to the second data lead line 52 located in the first gate metal layer through the nineteenth connection electrode 429 located in the first source-drain metal layer.

[0164] In some examples, the gate T91 of the ninth test transistor T9 and the gate T101 of the tenth test transistor T10 may be an integral structure and connected to the first fourth test control line SWD1 located at the first source-drain metal layer. The first region of the active layer T90 of the ninth test transistor T9 and the thirteenth connection electrode 423 located at the second gate metal layer may be connected through the seventeenth connection electrode 427 located at the first source-drain metal layer, the first region of the active layer T100 of the tenth test transistor T10 and the thirteenth connection electrode 423 located at the second gate metal layer may be connected through the sixteenth connection electrode 426 located at the first source-drain metal layer, and the thirteenth connection electrode 423 may be connected to the first fifth test data line DD2-1 located at the first source-drain metal layer. The second region of the active layer T90 of the ninth test transistor T9 may be connected to the third data lead-out line 53 located at the second gate metal layer through the eighteenth connection electrode 428 located at the first source-drain metal layer. The second region of the active layer T100 of the tenth test transistor T10 may be connected to the fourth data lead line 54 located in the first gate metal layer through the fifteenth connection electrode 425 located in the first source-drain metal layer.

[0165] In this example, the second type of test circuit includes four transistors. The four transistors of the second type of test circuit are arranged along the first direction, which can save the wiring space occupied by the second type of test circuit in the second direction.

[0166] Fig.18 FIG. 1 is a schematic diagram of local wiring in the first border area of ​​at least one embodiment of the present disclosure. In some examples, such as Fig.18 As shown, the circuit setting area B133 of the first frame area can be located on the side of the first signal access area B131 close to the bending area B12. The first frame area can be provided with a plurality of first frame power lines (such as two first frame power lines VDD1 and VDD2), a plurality of second frame power lines (such as three second frame power lines VSS1, VSS2 and VSS3), a plurality of third frame power lines (such as two third frame power lines VGLa and VGLb), a plurality of fourth frame power lines (such as two fourth frame power lines VGHa and VGHb), and a plurality of groups of initial signal lines (such as including a first group of initial signal lines INITa, a second group of initial signal lines INITb, a third group of initial signal lines INITc and a fourth group of initial signal lines INITd). The plurality of first frame power lines, the plurality of second frame power lines, the plurality of third frame power lines, the plurality of fourth frame power lines and the plurality of groups of initial signal lines can extend to the second signal access area B132 and be connected to the corresponding second contact pads in the second signal access area B132.

[0167] In some examples, the first frame power line can be configured to provide a first power signal to the pixel circuit of the sub-pixel of the display area, the second frame power line can be configured to provide a second power signal to the light-emitting element of the sub-pixel of the display area, and the first power signal can be greater than the second power signal. The third frame power line can be configured to provide a third power signal to the gate drive circuit set in the second frame area and the third frame area, and the fourth frame power line can be configured to provide a fourth power signal to the gate drive circuit set in the second frame area and the third frame area, and the third power signal can be greater than the fourth power signal. The gate drive circuit can be configured to provide a pixel control signal to the pixel circuit of the sub-pixel of the display area. Multiple groups of initial signal lines can be configured to provide initial signals to the pixel circuit of the sub-pixel of the display area.

[0168] In some examples, the third second frame power line VSS3 may be located in the middle of the two first frame power lines VDD1 and VDD2, the portion of the third second frame power line VSS3 extending along the first direction D1 in the second sub-region B13 may be located on both sides of the circuit setting area B133, and the portion of the third second frame line VSS3 extending along the second direction D2 in the second sub-region B13 may be located on one side of the circuit setting area B133 close to the bending area B12. The first second frame power line VSS1 may be located on the side of the first first frame power line VDD1 away from the third second frame power line VSS3, and the second second frame power line VSS2 may be located on the side of the second first frame power line VDD2 away from the third second frame power line VSS3.

[0169] In some examples, the second group of initial signal lines INITb may be located between the first second frame power line VSS1 and the first first frame power line VDD1, and the third group of initial signal lines INITc may be located between the second second frame power line VSS2 and the second first frame power line VDD2. The first group of initial signal lines INITa may be located on a side of the first second frame power line VSS1 away from the first first frame power line VDD1, and the fourth group of initial signal lines INITd may be located on a side of the second second frame power line VSS2 away from the second first frame power line VDD2.

[0170] In some examples, the first third frame power line VGLa may be located between the first group of initial signal lines INITa and the first second frame power line VSS1. The second third frame power line VGLb may be located between the fourth group of initial signal lines INITd and the second second frame power line VSS2. The first fourth frame power line VGHa may be located on a side of the first group of initial signal lines INITa away from the first third frame power line VGLa, and the second fourth frame power line VGHb may be located on a side of the fourth group of initial signal lines INITd away from the second third frame power line VGLb.

[0171] In this example, after the test circuit of the circuit setting area B133 is compressed along the second direction in the manner of the aforementioned embodiment, the increased routing space on both sides of the circuit setting area B133 along the second direction D2 can be conducive to the arrangement of multiple second frame power lines, multiple groups of initial signal lines, multiple third frame power lines and multiple fourth frame power lines, which can further optimize the current density. By setting three second frame power lines, the cross-voltage of the second power signal can be effectively reduced, and the power consumption can be reduced. By setting two groups of third frame power lines and two groups of fourth frame power lines, the voltage drop of the third power signal and the fourth power signal can be improved. By setting multiple groups of initial signal lines, poor display such as three-point screen and dark display on both sides can be improved.

[0172] Fig.19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.19 As shown, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator, or any other product or component with a display function. However, this embodiment is not limited thereto.

[0173] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0174] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising: a display area and a first frame area located at one side of the display area along a first direction; A plurality of pixel units and a plurality of data lines are arranged on the substrate and located in the display area, the plurality of pixel units are electrically connected to the plurality of data lines, and the pixel unit includes a plurality of sub-pixels; A plurality of data lead-out lines are located in the first frame area, and the plurality of data lead-out lines are electrically connected to the plurality of data lines; A plurality of first-type test circuit groups, located in the first border area and connected to the plurality of data lead-out lines; At least one of the multiple first-class test circuit groups includes at least one first-class test circuit arranged along the first direction; the first-class test circuit includes a plurality of transistors arranged along the first direction, and the first-class test circuit is configured to provide a first-class test data signal to a column of pixel units, and the column of pixel units includes a plurality of pixel units arranged along the first direction.

2. The display substrate according to claim 1, characterized in that: The plurality of sub-pixels of the pixel unit include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light; The first type of test circuits includes: a first test circuit, a second test circuit, a third test circuit and a fourth test circuit; the first test circuit, the second test circuit, the third test circuit and the fourth test circuit each include at least one transistor; The first test circuit is configured to provide a first type of test data signal to a first sub-pixel of an e-th row of pixel units in the column of pixel units in a first period, and to provide a first type of test data signal to a second sub-pixel of an e+1-th row of pixel units in the column of pixel units in a second period; The second test circuit is configured to provide a first type of test data signal to a column of third sub-pixels in the column of pixel units; The third test circuit is configured to provide a first type of test data signal to a first sub-pixel of an e+1-th row of pixel units in the column of pixel units in the first time period, and to provide a first type of test data signal to a second sub-pixel of an e-th row of pixel units in the column of pixel units in the second time period; wherein e is a positive integer; The fourth test circuit is configured to provide a first type of test data signal to the third sub-pixels in another column of the one column of pixel units.

3. The display substrate according to claim 2, characterized in that: The first test circuit, the second test circuit, the fourth test circuit and the third test circuit of the at least one first-type test circuit group are arranged in sequence along the first direction.

4. The display substrate according to claim 2, characterized in that: The display substrate further includes: a plurality of first test control lines, a plurality of second test control lines, a plurality of third test control lines, a plurality of first test data lines, a plurality of second test data lines and at least one third test data line located in the first frame area; The first test circuit comprises: at least one first test transistor and at least one second test transistor, a gate of the at least one first test transistor is connected to a first test control line among the plurality of first test control lines, a first electrode of the at least one first test transistor is connected to a first test data line among the plurality of first test data lines, a gate of the at least one second test transistor is connected to a second test control line among the plurality of second test control lines, a first electrode of the at least one second test transistor is connected to a second test data line among the plurality of second test data lines, and a second electrode of the at least one first test transistor and a second electrode of the at least one second test transistor are connected to the same data lead line among the plurality of data lead lines; The second test circuit comprises: at least one third test transistor, a gate of the at least one third test transistor is connected to a third test control line among the plurality of third test control lines, a first electrode of the at least one third test transistor is connected to the at least one third test data line, and a second electrode of the at least one third test transistor is connected to a data lead line among the plurality of data lead lines; The third test circuit comprises: at least one fourth test transistor and at least one fifth test transistor, a gate of the at least one fourth test transistor is connected to another second test control line among the plurality of second test control lines, a first electrode of the at least one fourth test transistor is connected to another first test data line among the plurality of first test data lines, a gate of the at least one fifth test transistor is connected to another first test control line among the plurality of first test control lines, a first electrode of the at least one fifth test transistor is connected to another second test data line among the plurality of second test data lines, and a second electrode of the at least one fourth test transistor and a second electrode of the at least one fifth test transistor are connected to the same data lead line among the plurality of data lead lines; The fourth test circuit comprises: at least one sixth test transistor, a gate of the at least one sixth test transistor is connected to another third test control line among the plurality of third test control lines, a first electrode of the at least one sixth test transistor is connected to the at least one third test data line, and a second electrode of the sixth test transistor is connected to one data lead line among the plurality of data lead lines; The first test circuit, the second test circuit, the third test circuit, and the fourth test circuit are connected to different data pin-out lines.

5. The display substrate according to claim 4, characterized in that: The display substrate comprises: four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines and one third test data line; The first second test control line, the first first test control line, the first first test data line, the first second test data line, the second second test control line, the second first test control line, the first third test control line, the third test data line, the second third test control line, the second first test data line, the third first test control line, the third second test control line, the fourth first test control line and the second second test data line are arranged in sequence along the first direction; The first type of test circuit of the at least one first type of test circuit group comprises: a first test transistor, a second test transistor, a third test transistor, a fourth test transistor, a fifth test transistor and a sixth test transistor; The first test transistor is connected to the first first test control line and the first first test data line, and is located between the first first test control line and the first first test data line in the first direction; The second test transistor is connected to the first second test data line and the second second test control line, and is located between the first second test data line and the second second test control line in the first direction; The third test transistor is connected to the first third test control line and the third test data line, and is located between the first third test control line and the third test data line in the first direction; The fourth test transistor is connected to the second first test data line and the third second test control line, and is located between the second first test data line and the third first test control line in the first direction; The fifth test transistor is connected to the fourth first test control line and the second second test data line, and is located between the fourth first test control line and the second second test data line in the first direction.

6. The display substrate according to claim 4, characterized in that: The display substrate comprises: two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines and three third test data lines; The first second test control line, the first first test data line, the second first test data line, the first first test control line, the second second test control line, the first second test data line, the second second test data line, the first third test control line, the first third test data line, the second third test data line, the third third test data line, the second third test control line, the third second test control line, the third first test data line, the fourth first test data line, the second first test control line, the fourth second test control line, the third second test data line and the fourth second test data line are arranged in sequence along the first direction; The first type test circuit of the at least one first type test circuit group comprises: two first test transistors, two second test transistors, two third test transistors, two fourth test transistors, two fifth test transistors and two sixth test transistors; The two first test transistors are located between the first first test data line and the second first test data line in the first direction; The two second test transistors are located between the first second test data line and the second second test data line in the first direction; The two third test transistors are located between the first third test data line and the second third test data line in the first direction; The two sixth test transistors are located between the second third test data line and the third third test data line in the first direction; The two fourth test transistors are located between the third first test data line and the fourth first test data line in the first direction; The two fifth test transistors are located between the third second test data line and the fourth second test data line in the first direction.

7. The display substrate according to claim 6, characterized in that: The first first test transistor of the first type of test circuit is connected to the first first test data line and the first first test control line, and the second first test transistor is connected to the second first test data line and the first first test control line; A first second test transistor is connected to the first second test data line and the second second test control line, and a second second test transistor is connected to the second second test data line and the second second test control line; A first third test transistor is connected to the first third test data line and the first third test control line, and a second third test transistor is connected to the second third test data line and the first third test control line; a first sixth test transistor connected to the second third test data line and the second third test control line, and a second sixth test transistor connected to the third third test data line and the second third test control line; A first fourth test transistor is connected to the third first test data line and the third second test control line, and a second fourth test transistor is connected to the fourth first test data line and the third second test control line; The first fifth test transistor is connected to the third second test data line and the second first test control line, and the second fifth test transistor is connected to the fourth second test data line and the second first test control line.

8. The display substrate according to claim 4, characterized in that: The at least one first-category test circuit group includes two first-category test circuits arranged along the first direction, the first test circuit, the second test circuit, the fourth test circuit and the third test circuit of the first first-category test circuit are arranged in sequence along the first direction, and the second test circuit, the fourth test circuit, the first test circuit and the third test circuit of the second first-category test circuit are arranged in sequence along the first direction.

9. The display substrate according to claim 8, characterized in that: The display substrate comprises: four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines and two third test data lines; The first first test control line, the first first test data line, the first second test data line, the first second test control line, the first third test control line, the first third test data line, the second third test control line, the second second test control line, the second first test data line, the second second test data line, the second first test control line, the third third test control line, the second third test data line, the fourth third test control line, the third first test control line, the third first test data line, the third second test data line, the third second test control line, the fourth second test control line, the fourth first test data line, the fourth second test data line and the fourth first test control line are arranged sequentially along the first direction.

10. The display substrate according to claim 1, characterized in that: The display substrate also includes: a plurality of second-type test circuit groups, at least one of the plurality of second-type test circuit groups includes: at least one second-type test circuit arranged along the first direction, the second-type test circuit includes a plurality of transistors arranged along the first direction, and the second-type test circuit is configured to provide a second-type test data signal to the column of pixel units.

11. The display substrate according to claim 10, characterized in that: The second type of test circuits includes: a fifth test circuit, a sixth test circuit, a seventh test circuit and an eighth test circuit; The column of pixel units includes four columns of sub-pixels; the fifth test circuit, the sixth test circuit, the seventh test circuit and the eighth test circuit of the second type of test circuit are configured to provide second-type test data signals to the four columns of sub-pixels; the eighth test circuit, the seventh test circuit, the sixth test circuit and the fifth test circuit of the second type of test circuit are arranged sequentially along the first direction.

12. The display substrate according to claim 11, characterized in that: The fifth test circuit includes: at least one seventh test transistor, the sixth test circuit includes: at least one eighth test transistor, the seventh test circuit includes: at least one ninth test transistor, and the eighth test circuit includes: at least one tenth test transistor; The display substrate further includes: a plurality of fourth test control lines, a plurality of fourth test data lines and a plurality of fifth test data lines located in the first frame area; The gate of the seventh test transistor and the gate of the eighth test transistor are connected to the same fourth test control line among the plurality of fourth test control lines, the first electrode of the seventh test transistor and the first electrode of the eighth test transistor are connected to the same fourth test data line among the plurality of fourth test data lines, the second electrode of the seventh test transistor is connected to one data lead-out line among the plurality of data lead-out lines, and the second electrode of the eighth test transistor is connected to another data lead-out line among the plurality of data lead-out lines; The gate of the ninth test transistor and the gate of the tenth test transistor are connected to the same fourth test control line among the multiple fourth test control lines, the first electrode of the ninth test transistor and the first electrode of the tenth test transistor are connected to the same fifth test data line among the multiple fifth test data lines, the second electrode of the ninth test transistor is connected to another data lead-out line among the multiple data lead-out lines, and the second electrode of the tenth test transistor is connected to another data lead-out line among the multiple data lead-out lines.

13. The display substrate according to claim 1, characterized in that: The display substrate also includes: two first frame power lines and three second frame power lines located in the first frame area, the first second frame power line and the second second frame power line are located on both sides of the two first frame power lines and the third second frame power line, and the two first frame power lines are located on both sides of the third second frame power line.

14. The display substrate according to claim 13, characterized in that: The display substrate also includes: four groups of initial signal lines located in the first frame area, the first group of initial signal lines located on a side of the first second frame power line away from the third second frame power line, the second group of initial signal lines located on a side of the first second frame power line close to the third second frame power line, the third group of initial signal lines located on a side of the second second frame power line close to the third second frame power line, and the fourth group of initial signal lines located on a side of the second second frame power line away from the third second frame power line.

15. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 14.

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