Display panel, driving method and display device

Abstract

An embodiment of the present invention provides a display panel, a driving method and a display device, including: a display area and a peripheral area located outside the display area; the peripheral area is provided with multiple signal lines and multiple electrostatic protection circuits; one signal line is electrically connected to one electrostatic protection circuit; the electrostatic protection circuit is electrically connected to a first reference voltage signal terminal and a second reference voltage signal terminal, and is configured to connect or cut off the first reference voltage signal terminal and the signal line, or connect or cut off the second reference voltage signal terminal and the signal line; when the display panel is powered on, the second reference voltage signal terminal is loaded with the second reference voltage signal terminal at a first moment, the first reference voltage signal is loaded with the first reference voltage signal terminal at a second moment, and the signal line is loaded with the third reference voltage signal at a third moment or a fourth moment, the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is not earlier than the second moment.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a driving method and a display device. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) have the advantages of self-luminescence and low energy consumption, and are one of the hot topics in the current research field of display device applications. Among them, organic light-emitting diodes (OLEDs) are a type of organic thin-film electroluminescent device. Due to their simple preparation process, fast response speed, high brightness, wide viewing angle, active luminescence, and easy realization of flexible displays, they have broad application prospects. Summary of the Invention

[0003] A display panel provided in an embodiment of the present invention includes: a base substrate, the base substrate including a display area and a peripheral area located outside the display area; the peripheral area is provided with a plurality of signal traces and a plurality of electrostatic protection circuits; one of the signal traces is electrically connected to one of the electrostatic protection circuits;

[0004] The electrostatic protection circuit is electrically connected to the first reference voltage signal terminal and the second reference voltage signal terminal, and is configured to connect or disconnect the first reference voltage signal terminal from the signal trace, or connect or disconnect the second reference voltage signal terminal from the signal trace;

[0005] When the display panel is powered on, a second reference voltage signal is loaded onto the second reference voltage signal terminal at a first moment, a first reference voltage signal is loaded onto the first reference voltage signal terminal at a second moment, and a third reference voltage signal is loaded onto the signal line at a third moment or a fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is no earlier than the second moment.

[0006] In some possible implementations, the electrostatic protection circuit includes a first electrostatic protection circuit and a second electrostatic protection circuit;

[0007] The first electrostatic protection circuit is electrically connected to the first reference voltage signal terminal and the signal trace, and is configured to conduct the signal trace and the first reference voltage signal terminal when the voltage value of the third reference voltage signal loaded on the signal trace is greater than the voltage value of the first reference voltage signal, and to cut off the signal trace and the first reference voltage signal terminal when the voltage value of the third reference voltage signal loaded on the signal trace is less than the voltage value of the first reference voltage signal;

[0008] The second electrostatic protection circuit is electrically connected to the second reference voltage signal end and the signal trace, and is configured to connect the signal trace and the second reference voltage signal end when the voltage value of the third reference voltage signal loaded on the signal trace is less than the voltage value of the second reference voltage signal, and to cut off the signal trace and the second reference voltage signal end when the voltage value of the third reference voltage signal loaded on the signal trace is greater than the voltage value of the second reference voltage signal.

[0009] In some possible implementations, the first electrostatic protection circuit includes: a first transistor and a second transistor;

[0010] The gate of the first transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the first transistor is electrically connected to the first reference voltage signal terminal;

[0011] The gate of the second transistor is electrically connected to the first electrode of the second transistor, the first electrode of the second transistor is electrically connected to the signal wiring, and the second electrode of the second transistor is electrically connected to the first electrode of the first transistor.

[0012] In some possible implementations, the second electrostatic protection circuit includes: a third transistor and a fourth transistor;

[0013] The gate of the third transistor is electrically connected to the first electrode of the third transistor, and the second electrode of the third transistor is electrically connected to the signal wiring;

[0014] The gate of the fourth transistor is electrically connected to the first electrode of the fourth transistor, the first electrode of the fourth transistor is electrically connected to the second reference voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor.

[0015] An embodiment of the present invention provides a method for driving a display panel, comprising:

[0016] In a stage where electrostatic discharge is not required, the electrostatic protection circuit cuts off the first reference voltage signal terminal and the signal wiring, and cuts off the second reference voltage signal terminal and the signal wiring;

[0017] During the high-voltage electrostatic discharge phase, the electrostatic protection circuit connects the first reference voltage signal terminal to the signal line.

[0018] In the low-voltage electrostatic discharge stage, the electrostatic protection circuit connects the second reference voltage signal terminal to the signal line;

[0019] When the display panel is powered on, a second reference voltage signal is loaded onto the second reference voltage signal terminal at a first moment, a first reference voltage signal is loaded onto the first reference voltage signal terminal at a second moment, and a third reference voltage signal is loaded onto the signal line at a third moment or a fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is no earlier than the second moment.

[0020] In some possible implementations, a voltage value of the first reference voltage signal is greater than a voltage value of the second reference voltage signal.

[0021] In some possible implementations, in the stage where electrostatic release is not required, the voltage value of the first reference voltage signal is not less than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is not less than the voltage value of the second reference voltage signal.

[0022] In some possible implementations, during the high-voltage electrostatic release phase, the voltage value of the first reference voltage signal is less than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is greater than the voltage value of the second reference voltage signal.

[0023] In some possible implementations, during the low-voltage electrostatic release phase, the voltage value of the first reference voltage signal is greater than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is less than the voltage value of the second reference voltage signal.

[0024] A display device provided by an embodiment of the present invention includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Some structural schematic diagrams of display panels provided by embodiments of the present invention;

[0026] Figure 2 Other structural schematic diagrams of display panels provided by embodiments of the present invention;

[0027] Figure 3 Some further structural schematic diagrams of display panels provided by embodiments of the present invention;

[0028] Figure 4Some further structural schematic diagrams of display panels provided by embodiments of the present invention;

[0029] Figure 5 Some further structural schematic diagrams of display panels provided by embodiments of the present invention;

[0030] Figure 6 Some further structural schematic diagrams of display panels provided by embodiments of the present invention;

[0031] Figure 7 A schematic structural diagram of a gate drive circuit provided in an embodiment of the present invention;

[0032] Figure 8 A flowchart of a method for driving a display panel provided by an embodiment of the present invention;

[0033] Figure 9 Some signal timing diagrams provided for embodiments of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0036] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0037] With the advancement of OLED display technology, electronic components are becoming increasingly smaller, and users of OLED products are increasingly demanding higher electrical performance. For example, during the production, manufacturing, testing, and use of OLED display panels, certain external factors often cause the accumulation of static electricity on the display panel. When the accumulation reaches a certain level, electrostatic discharge (ESD) occurs. ESD generates extremely high voltage and current, which can easily break down components in the circuit or damage signal traces, causing signal anomalies or even interruptions, resulting in poor display quality.

[0038] Currently, some OLED products require external compensation functions, and the gate drive circuits in OLED products are generally compatible with external compensation functions. Because the gate drive circuit is compatible with external compensation functions, it requires a wide variety of clock alternating current (AC) and direct current (DC) signals, and the signal levels are complex. Therefore, considering the static electricity problems during the manufacturing process and use, it is necessary to set up multiple sets of static electricity protection circuits to release static electricity and prevent static electricity from damaging circuits and components, thereby ensuring the normal operation of the gate drive circuit. The stability of the static electricity protection circuit is particularly important to avoid problems such as display quality and display effects being affected by the malfunction of the static electricity protection circuit.

[0039] In view of the above problems, an embodiment of the present invention provides a display panel, such as Figure 1 and Figure 2 As shown, it includes: a base substrate 100, the base substrate 100 includes a display area AA and a peripheral area BB located outside the display area AA; the peripheral area BB is provided with multiple signal traces 10 and multiple electrostatic protection circuits 20; one signal trace 10 is electrically connected to one electrostatic protection circuit 20;

[0040] The electrostatic protection circuit 20 is electrically connected to the first reference voltage signal terminal VREF1 and the second reference voltage signal terminal VREF2, and is configured to connect or disconnect the first reference voltage signal terminal VREF1 and the signal trace 10, or connect or disconnect the second reference voltage signal terminal VREF2 and the signal trace 10;

[0041] When the display panel is powered on, the second reference voltage signal is loaded to the second reference voltage signal terminal VREF2 at a first moment, the first reference voltage signal is loaded to the first reference voltage signal terminal VREF1 at a second moment, and the third reference voltage signal is loaded to the signal line 10 at a third moment or a fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is not earlier than the second moment.

[0042] In an embodiment of the present invention, a plurality of signal lines and a plurality of electrostatic protection circuits are provided in a peripheral area; a signal line is electrically connected to an electrostatic protection circuit; and the electrostatic protection circuit is enabled to connect or disconnect the first reference voltage signal terminal to the signal line, or to connect or disconnect the second reference voltage signal terminal to the signal line; thus, the signal line and the circuit electrically connected to the signal line (for example, Figure 2 The gate drive circuit 30), that is, the electrostatic protection circuit discharges electrostatic energy through the first reference voltage signal terminal or the second reference voltage signal terminal, thereby avoiding damage to the signal wiring and circuit, thereby avoiding display abnormalities and improving display effects;

[0043] And when the display panel is powered on, the second reference voltage signal is loaded on the second reference voltage signal terminal at the first moment, the first reference voltage signal is loaded on the first reference voltage signal terminal at the second moment, and the third reference voltage signal is loaded on the signal line at the third moment or the fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is not earlier than the second moment. This setting can protect the electrostatic protection circuit and prevent the electrostatic protection circuit from being turned on when it does not need to release static electricity. It can reduce the number of working times of the components in the electrostatic protection circuit, thereby increasing the life of the electrostatic protection circuit, and ensuring the electrostatic release capability of the electrostatic protection circuit, preventing the electrostatic release capability of the electrostatic protection circuit from weakening, improving the stability of the product, and further protecting the display panel and ensuring the display effect.

[0044] In some embodiments of the present invention, Figure 3 As shown, the electrostatic protection circuit 20 includes a first electrostatic protection circuit 201 and a second electrostatic protection circuit 202;

[0045] The first electrostatic protection circuit 201 is electrically connected to the first reference voltage signal terminal VREF1 and the signal line 10, and is configured to connect the signal line 10 to the first reference voltage signal terminal VREF1 when the voltage value of the third reference voltage signal loaded on the signal line 10 is greater than the voltage value of the first reference voltage signal, and to cut off the signal line 10 from the first reference voltage signal terminal VREF1 when the voltage value of the third reference voltage signal loaded on the signal line 10 is less than the voltage value of the first reference voltage signal;

[0046] The second electrostatic protection circuit 202 is electrically connected to the second reference voltage signal terminal VREF2 and the signal line 10, and is configured to connect the signal line 10 and the second reference voltage signal terminal VREF2 when the voltage value of the third reference voltage signal loaded on the signal line 10 is less than the voltage value of the second reference voltage signal, and to cut off the signal line 10 and the second reference voltage signal terminal VREF2 when the voltage value of the third reference voltage signal loaded on the signal line 10 is greater than the voltage value of the second reference voltage signal.

[0047] Exemplarily, if static electricity has not accumulated on the signal trace, the first electrostatic protection circuit and the second electrostatic protection circuit disconnect the signal trace from the first reference voltage signal terminal and the second reference voltage signal terminal respectively; if the static electricity accumulated on the signal trace is high-voltage static electricity, the high-voltage static electricity can be transmitted to the first reference voltage signal terminal through the first electrostatic protection circuit for release; if the static electricity accumulated on the signal trace is low-voltage static electricity, the low-voltage static electricity can be transmitted to the second reference voltage signal terminal for release through the second electrostatic protection circuit.

[0048] It should be noted that the voltage value of the first reference voltage signal loaded on the first reference voltage signal terminal is the highest voltage value of the signal required by the display panel, and the voltage value of the second reference voltage signal loaded on the second reference voltage signal terminal is the lowest voltage value of the signal required by the display panel. Therefore, the voltage value of the third reference voltage signal loaded on the signal trace is less than or equal to the voltage value of the first reference voltage signal, or the voltage value of the third reference voltage signal loaded on the signal trace is greater than or equal to the voltage value of the second reference voltage signal. If the static electricity accumulated on the signal trace is high voltage, the voltage value of the third reference voltage signal on the signal trace is much greater than the voltage values ​​of the first reference voltage signal and the second reference voltage signal. If the static electricity accumulated on the signal trace is low voltage, the voltage value of the third reference voltage signal on the signal trace is much less than the voltage values ​​of the first reference voltage signal and the second reference voltage signal.

[0049] In some embodiments of the present invention, Figure 4 As shown, the first electrostatic protection circuit 201 includes: a first transistor M1 and a second transistor M2;

[0050] The gate of the first transistor M1 is electrically connected to the first electrode of the first transistor M1 , and the second electrode of the first transistor M1 is electrically connected to the first reference voltage signal terminal VREF1 ;

[0051] The gate of the second transistor M2 is electrically connected to the first electrode of the second transistor M2 , the first electrode of the second transistor M2 is electrically connected to the signal trace 10 , and the second electrode of the second transistor M2 is electrically connected to the first electrode of the first transistor M1 .

[0052] For example, the first transistor M1 and the second transistor M2 may be configured as oxide thin film transistors.

[0053] For example, Figure 4 As shown, the first transistor M1 and the second transistor M2 are N-type transistors. When the gate-source voltage difference Vgs of the first transistor M1 and the second transistor M2 is greater than the threshold voltage Vth of the first transistor M1 and the second transistor M2, the channels of the first transistor M1 and the second transistor M2 are opened, that is, the source and the drain of the first transistor M1 and the second transistor M2 can be conductive, and the first transistor M1 and the second transistor M2 are in the on state; when the gate-source voltage difference Vgs of the first transistor M1 and the second transistor M2 is less than the threshold voltage Vth of the first transistor M1 and the second transistor M2, the channels of the first transistor M1 and the second transistor M2 are cut off, that is, the source and the drain of the first transistor M1 and the second transistor M2 are not conductive, and the first transistor M1 and the second transistor M2 are in the off state; in most cases, the threshold voltage Vth of the N-type transistor is greater than 0.

[0054] Therefore, the embodiment of the present invention controls that when the display panel is powered on, the second reference voltage signal is loaded to the second reference voltage signal terminal at a first moment, the first reference voltage signal is loaded to the first reference voltage signal terminal at a second moment, and the third reference voltage signal is loaded to the signal line at a fourth moment; wherein the first moment is earlier than the second moment, and the fourth moment is not earlier than the second moment; such a setting can ensure that the gate-source voltage difference Vgs of the first transistor M1 and the second transistor M2 is less than the threshold voltage Vth of the first transistor M1 and the second transistor M2 each time the power is turned on, thereby ensuring that the first transistor M1 and the second transistor M2 are in a cut-off state, avoiding the first transistor M1 and the second transistor M2 from being turned on when the power is just turned on, thereby avoiding the first transistor M1 and the second transistor M2 from deteriorating as the number of power-ons increases, that is, ensuring the static electricity release capability of the first transistor M1 and the second transistor M2, and avoiding a reduction in product life.

[0055] It should be noted that if the fourth moment is earlier than the second moment, the gate-source voltage difference Vgs of the first transistor M1 and the second transistor M2 will be greater than the threshold voltage Vth of the first transistor M1 and the second transistor M2 each time the power is turned on, so that the first transistor M1 and the second transistor M2 are in the turned-on state, which will increase the number of times the first transistor M1 and the second transistor M2 are turned on, thereby causing the first transistor M1 and the second transistor M2 to degrade.

[0056] In some embodiments of the present invention, Figure 4As shown, the second electrostatic protection circuit 202 includes: a third transistor M3 and a fourth transistor M4;

[0057] The gate of the third transistor M3 is electrically connected to the first electrode of the third transistor M3 , and the second electrode of the third transistor M3 is electrically connected to the signal trace 10 ;

[0058] The gate of the fourth transistor M4 is electrically connected to the first electrode of the fourth transistor M4 , the first electrode of the fourth transistor M4 is electrically connected to the second reference voltage signal terminal VREF2 , and the second electrode of the fourth transistor M4 is electrically connected to the first electrode of the third transistor M3 .

[0059] Exemplarily, the third transistor M3 and the fourth transistor M4 may be configured as oxide thin film transistors.

[0060] For example, Figure 4 As shown, the third transistor M3 and the fourth transistor M4 are N-type transistors. When the gate-source voltage difference Vgs of the third transistor M3 and the fourth transistor M4 is greater than the threshold voltage Vth of the third transistor M3 and the fourth transistor M4, the channels of the third transistor M3 and the fourth transistor M4 are opened, that is, the source and the drain of the third transistor M3 and the fourth transistor M4 can be conductive, and the third transistor M3 and the fourth transistor M4 are in the on state; when the gate-source voltage difference Vgs of the third transistor M3 and the fourth transistor M4 is less than the threshold voltage Vth of the third transistor M3 and the fourth transistor M4, the channels of the third transistor M3 and the fourth transistor M4 are cut off, that is, the source and the drain of the third transistor M3 and the fourth transistor M4 are not conductive, and the third transistor M3 and the fourth transistor M4 are in the off state; in most cases, the threshold voltage Vth of the N-type transistor is greater than 0.

[0061] Therefore, in an embodiment of the present invention, when the display panel is powered on, the second reference voltage signal is loaded onto the second reference voltage signal terminal at a first moment, the first reference voltage signal is loaded onto the first reference voltage signal terminal at a second moment, and the third reference voltage signal is loaded onto the signal line at a third moment; wherein the first moment is earlier than the second moment, and the third moment is between the first moment and the second moment, that is, the third moment is not earlier than the first moment; such an arrangement can ensure that the gate-source voltage difference Vgs of the third transistor M3 and the fourth transistor M4 is less than the threshold voltage Vth of the third transistor M3 and the fourth transistor M4 each time the display panel is powered on, thereby ensuring that the third transistor M3 and the fourth transistor M4 are in a cut-off state, preventing the third transistor M3 and the fourth transistor M4 from being turned on when the display panel is just powered on, thereby preventing the third transistor M3 and the fourth transistor M4 from deteriorating with increasing power-on times, that is, ensuring the static electricity release capability of the third transistor M3 and the fourth transistor M4, thereby preventing a reduction in product life.

[0062] It should be noted that if the third moment is earlier than the first moment, the gate-source voltage difference Vgs of the third transistor M3 and the fourth transistor M4 will first be greater than the threshold voltage Vth of the third transistor M3 and the fourth transistor M4 each time the power is turned on, so that the third transistor M3 and the fourth transistor M4 are in the turned-on state, which increases the number of times the third transistor M3 and the fourth transistor M4 are turned on, thereby causing the third transistor M3 and the fourth transistor M4 to degrade.

[0063] Exemplarily, the display panel may include a plurality of pixel units arranged in an array. Each pixel unit may include sub-pixels of multiple different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve a color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve a color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0064] Exemplarily, a plurality of signal traces are electrically connected to the gate drive circuit, wherein, for example Figure 5 As shown, the signal trace 10 may include: a first clock signal line CLKD, a second clock signal line CLKE, a third clock signal line CLKF, a fourth clock signal line CLKA, a first power signal line VDDA, a second power signal line VDDB, a third power signal line VDD, a frame start signal line STV, an enable signal line OE, a first control signal line CN, a second control signal line CNB, a reference voltage signal line VGL1, a reference voltage signal line VGL2, and a reference voltage signal line VGL3. The gate drive circuit operates in response to the signals applied to the signal traces.

[0065] For example, Figure 6 As shown, the display panel may further include: a plurality of gate lines GA, a plurality of data lines DA, a gate driving circuit 30, and a source driving circuit 40. The gate driving circuit 30 is electrically connected to the gate lines GA and the controller 200, respectively, and the source driving circuit 40 is electrically connected to the data lines DA and the controller 200, respectively. The controller 200 may input control signals to the signal lines electrically connected to the gate driving circuit 30, thereby causing the gate driving circuit 30 to input signals to the gate lines GA to drive the gate lines GA.

[0066] Furthermore, the controller 200 can obtain the original display data of the image to be displayed in the current display frame, and send the display data to be displayed to the source driver circuit 40, so that the source driver circuit 40 can load the data voltage to the data line DA in the display panel according to the display data, thereby charging the sub-pixels, so that the sub-pixels are charged with the corresponding data voltage, and the image display function is realized. Exemplarily, the source driver circuit 40 can be set to multiple, and different source driver circuits are electrically connected to different data lines. For example, Figure 1 As shown, the source driver circuit 40 can be provided with two, wherein one source driver circuit 40 is electrically connected to half of the data lines, and the other source driver circuit 40 is electrically connected to the other half of the data lines. Of course, the source driver circuit 40 can also be provided with three, four, or more, which can be designed and determined according to the needs of actual application and is not limited here.

[0067] In addition, it should be noted that the gate drive circuit can be as follows Figure 6 The arrangement shown is provided on both sides of the display panel, and the gate drive circuits on both sides of the display panel can jointly drive the same gate line, or the gate drive circuit can be provided on only one side of the display panel, or the gate drive circuits on both sides of the display panel can respectively drive the gate lines corresponding to sub-pixels in different rows. In the embodiment of the present invention, the number of gate drive circuits provided in the display panel is not further limited here and can be determined according to the needs of the actual application.

[0068] For example, Figure 7As shown, the gate drive circuit 30 may include: a plurality of transistors T1-T39, wherein the gates of the transistors T1 and T2 are electrically connected to the enable signal line OE, the first electrode of the transistor T1 is electrically connected to the input signal terminal CRn-2, the second electrode of the transistor T1 is electrically connected to the first electrode of the transistor T2, the second electrode of the transistor T2 is electrically connected to the first plate of the capacitor C1; the second plate of the capacitor C1 is electrically connected to the third power signal line VDD; the gate of the transistor T3 is electrically connected to the first plate of the capacitor C1, the first electrode of the transistor T3 is electrically connected to the first electrode of the transistor T2, and the second electrode of the transistor T3 is electrically connected to the third power signal line VDD; the gate of the transistor T4 is electrically connected to the first plate of the capacitor C1, the first electrode of the transistor T3 is electrically connected to the first electrode of the transistor T2, and the second electrode of the transistor T3 is electrically connected to the third power signal line VDD; The first electrode of the transistor T4 is electrically connected to the fourth clock signal line CLKA, and the second electrode of the transistor T4 is electrically connected to the first electrode of the transistor T5; the gates of the transistors T5 and T6 are electrically connected to the fourth clock signal line CLKA, the second electrode of the transistor T5 is electrically connected to the first electrode of the transistor T6, and the second electrode of the transistor T6 is electrically connected to the first node N1; the gate of the transistor T7 is electrically connected to the first node N1, the first electrode of the transistor T7 is electrically connected to the first electrode of the transistor T6, and the second electrode of the transistor T7 is electrically connected to the third power supply signal line VDD; the gates of the transistors T8 and T9 are electrically connected to the input signal terminal CRn-2, and the first electrode of the transistor T8 is electrically connected to the first node N1. The control signal line CN is electrically connected, the second electrode of the transistor T8 is electrically connected to the first electrode of the transistor T9, and the second electrode of the transistor T9 is electrically connected to the first electrode of the transistor T10; the gates of the transistors T10 and T11 are electrically connected to the input signal terminal CRn+3, the second electrode of the transistor T10 is electrically connected to the first electrode of the transistor T11, and the second electrode of the transistor T11 is electrically connected to the second control signal line CNB; the gates of the transistors T12 and T13 are electrically connected to the frame start signal line STV, the first electrode of the transistor T12 is electrically connected to the first node N1, the second electrode of the transistor T12 is electrically connected to the first electrode of the transistor T13, and the second electrode of the transistor T13 is electrically connected to the reference voltage signal line VG L1 is electrically connected; the gates of the transistors T14 and T15 are electrically connected to the third control signal line QBB, the first electrode of the transistor T14 is electrically connected to the first node N1, the second electrode of the transistor T14 is electrically connected to the first electrode of the transistor T15, and the second electrode of the transistor T15 is electrically connected to the reference voltage signal line VGL1; the gates of the transistors T16 and T17 are electrically connected to the second node N2, the first electrode of the transistor T16 is electrically connected to the first electrode of the transistor T14, the second electrode of the transistor T16 is electrically connected to the second electrode of the transistor T14, the first electrode of the transistor T17 is electrically connected to the first electrode of the transistor T15, and the second electrode of the transistor T17 is electrically connected to the second electrode of the transistor T15;The gates of the transistors T18 and T19 are electrically connected to the first power signal line VDDA, the first electrode of the transistor T18 is electrically connected to the first power signal line VDDA, the second electrode of the transistor T18 is electrically connected to the first electrode of the transistor T19, and the second electrode of the transistor T19 is electrically connected to the gate of the transistor T20; the first electrode of the transistor T20 is electrically connected to the first power signal line VDDA, and the second electrode of the transistor T20 is electrically connected to the first electrode of the transistor T21; the gate of the transistor T21 is electrically connected to the first node N1, and the second electrode of the transistor T21 is electrically connected to the reference voltage signal line VGL1; the gate of the transistor T22 is electrically connected to the first node N1, and the first electrode of the transistor T22 is electrically connected to the gate of the transistor T20 , the second electrode of the transistor T22 is electrically connected to the reference voltage signal line VGL3; the gate of the transistor T23 is electrically connected to the fourth clock signal line CLKA, the first electrode of the transistor T23 is electrically connected to the second node N2, and the second electrode of the transistor T23 is electrically connected to the first electrode of the transistor T24; wherein the second node N is electrically connected to the fourth control signal line QBA; the gate of the transistor T24 is electrically connected to the fifth control signal line Hn, and the second electrode of the transistor T24 is electrically connected to the reference voltage signal line VGL1; the gate of the transistor T25 is electrically connected to the input signal terminal CRn-2, the first electrode of the transistor T25 is electrically connected to the first control signal line CN, and the second electrode of the transistor T25 is electrically connected to the first electrode of the transistor T26; the transistor T The gate of the transistor T26 is electrically connected to the input signal terminal CRn+3, and the second electrode of the transistor T26 is electrically connected to the second control signal line CNB; the gate of the transistor T27 is electrically connected to the first electrode of the transistor T26, the first electrode of the transistor T27 is electrically connected to the second node N2, and the second electrode of the transistor T27 is electrically connected to the reference voltage signal line VGL1; the gate of the transistor T28 is electrically connected to the gate of the transistor T27, the first electrode of the transistor T28 is electrically connected to the third control signal line QBB, and the second electrode of the transistor T28 is electrically connected to the reference voltage signal line VGL1; the gate of the transistor T29 is electrically connected to the fourth control signal line QBA, the first electrode of the transistor T29 is electrically connected to the gate of the transistor T28, and the second electrode of the transistor T29 is electrically connected to the reference voltage signal line VGL1. a gate of the transistor T32 is electrically connected to the third control signal line QBB or the fourth control signal line QBA, a first electrode of the transistor T32 is electrically connected to the input signal terminal CRn, and a second electrode of the transistor T32 is electrically connected to the reference voltage signal line VGL1; a gate of the transistor T30 is electrically connected to the third control signal line QBB, a first electrode of the transistor T30 is electrically connected to the gate of the transistor T28, and a second electrode of the transistor T30 is electrically connected to the reference voltage signal line VGL1; a gate of the transistor T31 is electrically connected to the second node N2, a first electrode of the transistor T31 is electrically connected to the input signal terminal CRn, and a second electrode of the transistor T31 is electrically connected to the reference voltage signal line VGL1; a gate of the transistor T32 is electrically connected to the third control signal line QBB or the fourth control signal line QBA, a first electrode of the transistor T32 is electrically connected to the input signal terminal CRn, and a second electrode of the transistor T32 is electrically connected to the reference voltage signal line VGL1;The gate of the transistor T33 is electrically connected to the second node N2, the first electrode of the transistor T33 is electrically connected to the output signal terminal G1n, and the second electrode of the transistor T33 is electrically connected to the reference voltage signal line VGL2; the gate of the transistor T34 is electrically connected to the third control signal line QBB or the fourth control signal line QBA, the first electrode of the transistor T34 is electrically connected to the output signal terminal G1n, and the second electrode of the transistor T34 is electrically connected to the reference voltage signal line VGL2; the gate of the transistor T35 is electrically connected to the second node N2, the first electrode of the transistor T35 is electrically connected to the output signal terminal G2n, and the second electrode of the transistor T35 is electrically connected to the reference voltage signal line VGL2; the gate of the transistor T36 is electrically connected to the third control signal line QBB or the fourth control signal line QBA, the first electrode of the transistor T36 is electrically connected to the output signal terminal G2n, and the second electrode of the transistor T36 is electrically connected to the reference voltage signal line VGL2 The gate of transistor T37 is electrically connected to the first node N1, the first electrode of transistor T37 is electrically connected to the first clock signal line CLKD, and the second electrode of transistor T37 is electrically connected to the input signal terminal CRn. The gate of transistor T38 is electrically connected to the first node N1, the first electrode of transistor T38 is electrically connected to the second clock signal line CLKE, and the second electrode of transistor T38 is electrically connected to the output signal terminal G1n. The gate of transistor T39 is electrically connected to the first node N1, the first electrode of transistor T39 is electrically connected to the third clock signal line CLKF, and the second electrode of transistor T39 is electrically connected to the output signal terminal G2n. The first plate of second capacitor C2 is electrically connected to the first node N1, and the second plate of second capacitor C2 is electrically connected to the output signal terminal G1n. The first plate of third capacitor C3 is electrically connected to the first node N1, and the second plate of third capacitor C3 is electrically connected to the output signal terminal G2n.

[0069] For example, the power-on timing of the signal lines electrically connected to the gate drive circuit can affect the conduction and cutoff of the transistors in the electrostatic protection circuit. If the power-on timing is incorrect, the transistors in the electrostatic protection circuit may be turned on when the display panel is powered on, causing the transistors in the electrostatic protection circuit to be turned on first each time the display panel is powered on. This causes the transistors in the electrostatic protection circuit to be turned on multiple times, thereby affecting the lifespan of the transistors in the electrostatic protection circuit and, in turn, the electrostatic discharge capability of the electrostatic protection circuit. If the electrostatic discharge capability of the electrostatic protection circuit is weakened, this may cause damage to the signal lines or the transistors in the gate drive circuit, thereby affecting the entire display panel, resulting in unstable operation of the display panel or poor display quality. Therefore, an embodiment of the present invention controls the second reference voltage signal terminal to be loaded with the second reference voltage signal at a first moment, the first reference voltage signal to be loaded with the first reference voltage signal terminal at a second moment, and the third reference voltage signal to be loaded with the signal line at a third moment or a fourth moment when the display panel is powered on, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is no earlier than the second moment. This setting can protect the electrostatic protection circuit and prevent the electrostatic protection circuit from turning on when it does not need to release static electricity. It can reduce the number of working times of components in the electrostatic protection circuit, thereby increasing the life of the electrostatic protection circuit and ensuring the electrostatic release ability of the electrostatic protection circuit, preventing the electrostatic release ability of the electrostatic protection circuit from weakening, improving the stability of the product, and further protecting the display panel and ensuring the display effect.

[0070] Some embodiments of the present invention provide a method for driving a display panel, such as Figure 8 As shown, it specifically includes: S100, in a stage where no electrostatic release is required, the electrostatic protection circuit cuts off the first reference voltage signal terminal and the signal wiring, and cuts off the second reference voltage signal terminal and the signal wiring;

[0071] S200, in the high-voltage electrostatic discharge stage, the electrostatic protection circuit connects the first reference voltage signal terminal to the signal trace;

[0072] S300, in the low-voltage electrostatic discharge stage, the electrostatic protection circuit connects the second reference voltage signal terminal to the signal trace;

[0073] In which, when the display panel is powered on, the second reference voltage signal is loaded on the second reference voltage signal end at the first moment, the first reference voltage signal is loaded on the first reference voltage signal end at the second moment, and the third reference voltage signal is loaded on the signal line at the third moment or the fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is not earlier than the second moment.

[0074] In some embodiments of the present invention, a voltage value of the first reference voltage signal is greater than a voltage value of the second reference voltage signal.

[0075] In some embodiments of the present invention, in a stage where electrostatic release is not required, the voltage value of the first reference voltage signal is not less than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is not less than the voltage value of the second reference voltage signal.

[0076] In some embodiments of the present invention, during the high-voltage electrostatic release phase, the voltage value of the first reference voltage signal is smaller than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is larger than the voltage value of the second reference voltage signal.

[0077] In some embodiments of the present invention, during the low-voltage electrostatic release phase, the voltage value of the first reference voltage signal is greater than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is less than the voltage value of the second reference voltage signal.

[0078] The following will Figure 4 As an example, combined with the structure diagram shown Figure 9 The signal timing diagram shown is further explained;

[0079] Among them, vref1 represents the first reference voltage signal loaded on the first reference voltage signal terminal, vref2 represents the second reference voltage signal loaded on the second reference voltage signal terminal, vref3-1 represents the reference voltage signal line in the signal trace 10 and the third reference voltage signal loaded on the reference voltage signal line, vref3-2 represents the third reference voltage signal loaded on the first power signal line and the second power signal line in the signal trace 10, and tcon represents the voltage signal of the timing controller in the controller.

[0080] For example, the voltage value of the first reference voltage signal vref1 is 24V, the voltage value of the second reference voltage signal vref2 is -10V, the voltage value of the third reference voltage signal vref3-1 is -6V, and the voltage value of the third reference voltage signal vref3-2 is 20V.

[0081] When the display panel is just powered on, the voltage signal of the timing controller in the controller is 12V. At the first time t1, the second reference voltage signal vref2 is applied to the second reference voltage signal terminal. At this time, the voltage value of the second reference voltage signal terminal is -10V, and the signals on the first reference voltage signal terminal, the reference voltage signal line and the reference voltage signal line in the signal routing, and the first power signal line and the second power signal line in the signal routing are all 0V. The gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor are all 0V.

[0082] At a third time t3, a third reference voltage signal vref3-1 is applied to the reference voltage signal line and the reference voltage signal line in the signal routing. At this time, the voltage value of the second reference voltage signal end is -10V, the voltage value of the reference voltage signal line and the reference voltage signal line in the signal routing is -6V, and the signals on the first reference voltage signal end and the first power signal line and the second power signal line in the signal routing are all 0V; wherein the gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor are all 0V;

[0083] At a second time t2, the first reference voltage signal vref1 is applied to the first reference voltage signal terminal. At this time, the voltage value of the second reference voltage signal terminal is -10V, the voltage values ​​of the reference voltage signal line and the reference voltage signal line in the signal trace are -6V, the voltage value of the first reference voltage signal terminal is 24V, and the signals of the first power signal line and the second power signal line in the signal trace are both 0V; wherein the gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor are all 0V;

[0084] At a fourth time t4, a third reference voltage signal vref3-2 is applied to the first power signal line and the second power signal line in the signal trace. At this time, the voltage value of the second reference voltage signal end is -10V, the voltage values ​​of the reference voltage signal line and the reference voltage signal line in the signal trace are -6V, the voltage value of the first reference voltage signal end is 24V, and the voltage values ​​of the first power signal line and the second power signal line in the signal trace are 20V. The gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor are all 0V.

[0085] In summary, it can be seen that at every moment, the gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor is 0V, that is, the first transistor, the second transistor, the third transistor, and the fourth transistor are all in the off state. It can be seen that the embodiment of the present invention ensures that the first transistor, the second transistor, the third transistor, and the fourth transistor are always in the off state when the display panel is powered on, thereby preventing transistor degradation and increasing transistor life. This ensures that the transistors can operate normally when electrostatic discharge is required, thereby preventing damage to the gate drive circuit and signal wiring, improving product stability, and thus ensuring the display effect and display quality of the display panel.

[0086] When the display panel is powered on, static electricity has not yet accumulated and is in a stage where no static electricity release is required. In this stage, the gate-source voltage difference Vgs of the first transistor, the second transistor, the third transistor, and the fourth transistor is 0V, and the first transistor, the second transistor, the third transistor, and the fourth transistor are all in a cut-off state.

[0087] After working for a period of time, a large amount of static electricity will accumulate on the signal line. If the static electricity on the signal line is high-voltage static electricity, the voltage value of the third reference voltage signal on the signal line is much greater than the voltage value of the second reference voltage signal and the voltage value of the first reference voltage signal. At this time, it is in the high-voltage static electricity release stage. In this stage, the gate-source voltage difference Vgs of the first transistor and the second transistor is much greater than their threshold voltage Vth, and the gate-source voltage difference Vgs of the third transistor and the fourth transistor is 0V, that is, the first transistor and the second transistor are in the on state, and the third transistor and the fourth transistor are in the off state. The high-voltage static electricity on the signal line can be transmitted to the first reference voltage signal terminal through the first transistor and the second transistor for release;

[0088] If the static electricity on the signal line is low-voltage static electricity, so that the voltage value of the third reference voltage signal on the signal line is much smaller than the voltage value of the second reference voltage signal and the voltage value of the first reference voltage signal, then it is in the low-voltage static electricity release stage. In this stage, the gate-source voltage difference Vgs of the first transistor and the second transistor is 0V, and the gate-source voltage difference Vgs of the third transistor and the fourth transistor is much larger than their threshold voltage Vth, that is, the first transistor and the second transistor are in the cut-off state, and the third transistor and the fourth transistor are in the on state. The low-voltage static electricity on the signal line can be transmitted to the second reference voltage signal end through the third transistor and the fourth transistor for release.

[0089] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, and thus the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0090] In specific implementations, in embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present invention.

[0091] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0092] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, characterized in that: include: a base substrate, the base substrate comprising a display area and a peripheral area located outside the display area; The peripheral area is provided with a plurality of signal lines and a plurality of electrostatic protection circuits; One of the signal traces is electrically connected to an electrostatic protection circuit; The electrostatic protection circuit is electrically connected to the first reference voltage signal terminal and the second reference voltage signal terminal, and is configured to connect or disconnect the first reference voltage signal terminal from the signal trace, or connect or disconnect the second reference voltage signal terminal from the signal trace; When the display panel is powered on, a second reference voltage signal is loaded onto the second reference voltage signal terminal at a first moment, a first reference voltage signal is loaded onto the first reference voltage signal terminal at a second moment, and a third reference voltage signal is loaded onto the signal line at a third moment or a fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is no earlier than the second moment.

2. The display panel according to claim 1, wherein The electrostatic protection circuit includes a first electrostatic protection circuit and a second electrostatic protection circuit; The first electrostatic protection circuit is electrically connected to the first reference voltage signal terminal and the signal trace, and is configured to conduct the signal trace and the first reference voltage signal terminal when the voltage value of the third reference voltage signal loaded on the signal trace is greater than the voltage value of the first reference voltage signal, and to cut off the signal trace and the first reference voltage signal terminal when the voltage value of the third reference voltage signal loaded on the signal trace is less than the voltage value of the first reference voltage signal; The second electrostatic protection circuit is electrically connected to the second reference voltage signal end and the signal trace, and is configured to connect the signal trace and the second reference voltage signal end when the voltage value of the third reference voltage signal loaded on the signal trace is less than the voltage value of the second reference voltage signal, and to cut off the signal trace and the second reference voltage signal end when the voltage value of the third reference voltage signal loaded on the signal trace is greater than the voltage value of the second reference voltage signal.

3. The display panel according to claim 2, wherein: The first electrostatic protection circuit includes: a first transistor and a second transistor; The gate of the first transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the first transistor is electrically connected to the first reference voltage signal terminal; The gate of the second transistor is electrically connected to the first electrode of the second transistor, the first electrode of the second transistor is electrically connected to the signal wiring, and the second electrode of the second transistor is electrically connected to the first electrode of the first transistor.

4. The display panel according to claim 2, wherein: The second electrostatic protection circuit includes: a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the first electrode of the third transistor, and the second electrode of the third transistor is electrically connected to the signal wiring; The gate of the fourth transistor is electrically connected to the first electrode of the fourth transistor, the first electrode of the fourth transistor is electrically connected to the second reference voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor.

5. A method for driving a display panel according to any one of claims 1 to 4, characterized in that: include: In a stage where electrostatic discharge is not required, the electrostatic protection circuit cuts off the first reference voltage signal terminal and the signal wiring, and cuts off the second reference voltage signal terminal and the signal wiring; During the high-voltage electrostatic discharge phase, the electrostatic protection circuit connects the first reference voltage signal terminal to the signal line. In the low-voltage electrostatic discharge stage, the electrostatic protection circuit connects the second reference voltage signal terminal to the signal line; When the display panel is powered on, a second reference voltage signal is loaded onto the second reference voltage signal terminal at a first moment, a first reference voltage signal is loaded onto the first reference voltage signal terminal at a second moment, and a third reference voltage signal is loaded onto the signal line at a third moment or a fourth moment, wherein the first moment is earlier than the second moment, the third moment is between the first moment and the second moment, and the fourth moment is no earlier than the second moment.

6. The driving method according to claim 5, wherein: A voltage value of the first reference voltage signal is greater than a voltage value of the second reference voltage signal.

7. The driving method according to claim 6, wherein: In the stage where electrostatic release is not required, the voltage value of the first reference voltage signal is not less than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is not less than the voltage value of the second reference voltage signal.

8. The driving method according to claim 6, wherein: In the high-voltage electrostatic release stage, the voltage value of the first reference voltage signal is smaller than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is larger than the voltage value of the second reference voltage signal.

9. The driving method according to claim 6, wherein: In the low-voltage electrostatic release stage, the voltage value of the first reference voltage signal is greater than the voltage value of the third reference voltage signal, and the voltage value of the third reference voltage signal is less than the voltage value of the second reference voltage signal.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 4.

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