Display panel

Abstract

The application relates to the technical field of display, and particularly discloses a display panel, which comprises a display area and a non-display area surrounding the display area; the display area is provided with a plurality of pixel driving circuits, each of the pixel driving circuits comprises a light-emitting control signal end; the non-display area is provided with a plurality of light-emitting control circuits, the output ends of the light-emitting control circuits are connected to the light-emitting control signal ends of the corresponding pixel driving circuits; each of the light-emitting control circuits comprises a group of voltage signal ends, the display panel is provided with at least two groups of voltage signal lines, and each group of voltage signal ends is connected to one of the groups of voltage signal lines. The voltage signal ends of the light-emitting control circuits are not all connected to one group of voltage signal lines, but can be shared by at least two groups of voltage signal lines, so that the problem that a driving chip cannot normally output a voltage signal line due to excessive load caused by the fact that only one group of voltage signal lines is arranged in the prior art can be avoided, and the display panel can be normally displayed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] Since the active light-emitting organic diode display panel (AMOLED) has incomparable advantages over liquid crystal display (LCD) in display color saturation, power consumption and foldability, it gradually occupies the market of high-end mobile phones. Unlike LCD, AMOLED is equipped with DC+PWM dimming technology. In PWM dimming, the EM signal in a frame is realized by multiple pulses to alternately switch the screen between on and off. It is generally believed in the industry that the more the number of EM pulses, the more beneficial to the human eye, but the increase in the number of EM pulses will affect the normal display of the display panel to some extent. SUMMARY

[0003] Therefore, it is necessary to provide a display panel to solve the above problems. The display panel comprises a display area and a non-display area surrounding the display area; the display area is provided with a plurality of pixel driving circuits, each of the pixel driving circuits comprises a light-emitting control signal end; the non-display area is provided with a plurality of light-emitting control circuits, and the output end of each light-emitting control circuit is connected to the light-emitting control signal end of the corresponding pixel driving circuit.

[0004] Each of the light-emitting control circuits comprises a group of voltage signal ends, and the display panel is provided with at least two groups of voltage signal lines, and each group of voltage signal ends is connected to one of the groups of voltage signal lines.

[0005] In one embodiment, the display panel is provided with two groups of voltage signal lines, the voltage signal ends of part of the light-emitting control circuits are connected to the first group of voltage signal lines, and the voltage signal ends of the other light-emitting control circuits are connected to the second group of voltage signal lines.

[0006] In one embodiment, the display panel comprises a length direction and a width direction, each of the light-emitting control circuits is arrayed on at least one side of the display area in the width direction, and the light-emitting control circuits of adjacent rows are staggered, the voltage signal ends of the light-emitting control circuits of odd-numbered rows are connected to the first group of voltage signal lines, and the voltage signal ends of the light-emitting control circuits of even-numbered rows are connected to the second group of voltage signal lines.

[0007] In one embodiment, the non-display area is further provided with a plurality of gate driving circuits, each of the pixel driving circuits comprises a gate driving signal end, the output end of each of the gate driving circuits is connected to the gate driving signal end of the corresponding pixel driving circuit, and each of the gate driving circuits comprises a group of voltage signal ends.

[0008] The gate drive circuits are distributed on at least one side of the display area in the width direction, and the gate drive circuits of adjacent rows are arranged in a staggered manner in the column direction. The voltage signal ends of the gate drive circuits of odd-numbered rows are connected to the second group of voltage signal lines, and the voltage signal ends of the gate drive circuits of even-numbered rows are connected to the first group of voltage signal lines.

[0009] In one of the embodiments, the gate drive circuits and the light-emitting control circuits are arranged alternately in the length direction.

[0010] In one of the embodiments, the light-emitting control circuits are arranged in a cascaded manner, and the output end of a previous row of light-emitting control circuits is connected to the input end of a next row of light-emitting control circuits.

[0011] In one of the embodiments, the gate drive circuits are arranged in a cascaded manner, and the output end of a previous row of gate drive circuits is connected to the input end of a next row of gate drive circuits.

[0012] In one of the embodiments, the voltage signal ends include first voltage signal ends and second voltage signal ends, and the voltage signal lines include first voltage signal lines and second voltage signal lines. The first voltage signal lines are connected to the first voltage signal ends, and the second voltage signal lines are connected to the second voltage signal ends.

[0013] In one of the embodiments, the first voltage signal lines provide low-level signals, and the second voltage signal lines provide high-level signals.

[0014] In one of the embodiments, each group of voltage signal lines is connected to a driving chip.

[0015] The display panel provided by the embodiments of the present application is provided with at least two groups of voltage signal lines, and the voltage signal ends of each light-emitting control circuit can be connected to one of the groups of voltage signal lines. That is, the voltage signal ends of the light-emitting control circuits are not all connected to one group of voltage signal lines, but can be distributed to at least two groups of voltage signal lines. Thus, the problem that the driving chip cannot normally output voltage signal lines due to excessive load caused by the provision of only one group of voltage signal lines in the prior art can be avoided, and the normal display of the display panel can be ensured. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 Timing diagram of pixel driving circuit;

[0017] Figure 2 Timing diagram of EM signal when there are four pulses;

[0018] Figure 3 Structural diagram of display panel in prior art;

[0019] Figure 4A connection diagram of a voltage signal end of a light emitting control circuit and a gate drive circuit and a voltage signal line in a display panel according to an embodiment of the present application is provided.

[0020] Figure 5 A structure diagram of a display panel according to an embodiment of the present application is provided.

[0021] Figure 6 A connection diagram of a voltage signal end of a light emitting control circuit and a gate drive circuit and a voltage signal line in a display panel according to an embodiment of the present application is provided.

[0022] Legend of reference signs:

[0023] 100, display area;

[0024] 200, non-display area; E, light emitting control circuit; S, gate drive circuit; 210, voltage signal end; VGL, first voltage signal end; VGH, second voltage signal end; 300, voltage signal line; 310, first group of voltage signal lines; 320, second group of voltage signal lines; PVGL, first voltage signal line; PVGH, second voltage signal line;

[0025] Y, length direction; X, width direction. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0027] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0028] The terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] Since the active light-emitting organic diode display panel (AMOLED) has incomparable advantages in display color saturation, power consumption, and foldability compared with liquid crystal display (LCD), it gradually occupies the market of high-end mobile phones. Unlike LCD, AMOLED is equipped with DC+PWM dimming technology. When PWM dimming, the EM signal in a frame is realized by multiple pulses to alternately switch the screen between on and off. It is generally believed in the industry that the more the number of EM pulses, the more beneficial to the human eye, but the increase in the number of EM pulses will affect the normal display of the display panel to some extent.

[0031] Specifically, when the number of EM pulses increases, the number of EM circuits that need to work simultaneously also increases. For example, referring to Figure 1 and Figure 2 When there are 4 pulses, there are 4 EM circuits simultaneously performing high-low level switching driving. Assuming there are 32 pulses, there are 32 EM circuits simultaneously performing high-low level switching driving, which will cause the load and power consumption of the EM circuits to increase by 32 times. In addition, the power supply end of each EM circuit is generally connected to the driving IC through the same group of power signal lines. When too many EM circuits work simultaneously, the heavy load will cause the driving IC to be unable to normally output voltage to the power signal line, thereby causing display abnormalities.

[0032] To solve the above problems, the embodiments of the present application provide a display panel.

[0033] Referring to Figure 5 and Figure 6 The display panel provided by the embodiments of the present application includes a display area 100 and a non-display area 200 surrounding the display area 100; the display area 100 is provided with a plurality of pixel driving circuits, each of the pixel driving circuits includes a light-emitting control signal end; the non-display area 200 is provided with a plurality of light-emitting control circuits E, and the output end of each light-emitting control circuit E is connected to the light-emitting control signal end of the corresponding pixel driving circuit.

[0034] Each of the light-emitting control circuits E includes a group of voltage signal ends 210, and the display panel is provided with at least two groups of voltage signal lines 300, and each group of voltage signal ends 210 is connected to one of the groups of voltage signal lines 300.

[0035] Specifically, the display area 100 includes a plurality of light emitting units, each of which is connected to a corresponding pixel driving circuit, and each of the light emitting units can emit light by the pixel driving circuit. The pixel driving circuit includes a light emitting control signal end and a gate driving signal end, the gate driving signal end is connected to a corresponding gate driving circuit S, and the light emitting control signal end is connected to a corresponding light emitting control circuit E, that is, the gate driving circuit S outputs the gate driving signal to the gate driving signal end to write data to the pixel driving circuit, and the light emitting control circuit E outputs the light emitting control signal to the light emitting control signal end to drive the light emitting unit to emit light.

[0036] Each of the light emitting control circuits E and the gate driving circuits S can be provided in the non-display area 200. Each of the light emitting control circuits E can be provided in cascade, that is, the output end of the light emitting control circuit E of the previous row is connected to the light emitting control signal end of the corresponding pixel driving circuit and the input end of the light emitting control circuit E of the next row. Each of the gate driving circuits S can also be provided in cascade, that is, the output end of the gate driving circuit S of the previous row is connected to the gate driving signal end of the corresponding pixel driving circuit and the input end of the gate driving circuit S of the next row.

[0037] The light emitting control circuit E and the gate driving circuit S each have a group of voltage signal ends 210, which can include a first voltage signal end VGL and a second voltage signal end VGH, wherein the first voltage signal end VGL and the second voltage signal end VGH are connected to different voltages.

[0038] The group of voltage signal lines 300 can include a first voltage signal line PVGL and a second voltage signal line PVGH, and the first voltage signal line PVGL and the second voltage signal line PVGH respectively provide different voltage values, for example, the first voltage signal line PVGL can provide a low-level signal, and the second voltage signal line PVGH can provide a high-level signal. The first voltage signal line PVGL can be connected to the first voltage signal end VGL, and the second voltage signal line PVGH can be connected to the second voltage signal end VGH.

[0039] Referring to Figure 3 and Figure 4 In the conventional technology, only one group of voltage signal lines 300 is generally provided, and the voltage signal ends 210 of each of the light emitting control circuits E and the gate driving circuits S are connected to the group of voltage signal lines 300, that is, the group of voltage signal lines 300 is shared. When there are multiple pulses, the number of light emitting control circuits E that simultaneously perform high-low level switching driving is large, and since the voltage signal ends 210 of all the light emitting control circuits E are connected to the same group of voltage signal lines 300, this will cause the driving IC to be unable to normally output voltage to the voltage signal lines 300 due to excessive load, thereby causing display abnormalities.

[0040] In the embodiment, at least two groups of voltage signal lines 300 are provided, and the voltage signal end 210 of each light-emitting control circuit E is connected to one of the groups of voltage signal lines 300, that is, the voltage signal end 210 of the light-emitting control circuit E can be connected to different groups of voltage signal lines 300 according to actual needs, so as to avoid the problem of display abnormality caused by connection to the same group of voltage signal lines 300.

[0041] In the embodiment, at least two groups of voltage signal lines 300 are provided, and the voltage signal end 210 of each light-emitting control circuit E is connected to one of the groups of voltage signal lines 300, that is, the voltage signal end 210 of the light-emitting control circuit E can be connected to different groups of voltage signal lines 300 according to actual needs, so as to avoid the problem of display abnormality caused by connection to the same group of voltage signal lines 300.

[0042] Referring to Figure 6 In one of the embodiments, the display panel is provided with two groups of voltage signal lines 300, and the voltage signal end 210 of part of the light-emitting control circuits E is connected to the first group of voltage signal lines 310, and the voltage signal end 210 of the other light-emitting control circuits E is connected to the second group of voltage signal lines 320.

[0043] The two groups of voltage signal lines 300 can relieve the problem of excessive load and display abnormality caused by one group of voltage signal lines 300, and avoid increasing too much wiring space.

[0044] Referring to Figure 5 In one of the embodiments, the display panel includes a length direction Y and a width direction X, the length direction Y is the column direction, and the width direction X is the row direction. The light-emitting control circuits E are arrayed on at least one side of the display area 100 in the width direction X, and each light-emitting control circuit E can be arranged on one side of the display area 100 in the width direction X, or can be uniformly arranged on both sides of the display area 100 in the width direction X.

[0045] In the embodiment, the light-emitting control circuits E of adjacent rows are staggered. Specifically, the light-emitting control circuits E on the same side of the display area 100 in the width direction X can be distributed in an S shape along the length direction Y of the display panel, the light-emitting control circuits E of odd-numbered rows can be located in the same column, the light-emitting control circuits E of even-numbered rows can be located in the same column, and the light-emitting control circuits E of odd-numbered rows and even-numbered rows are located in different columns.

[0046] Referring to Figure 6 The voltage signal end 210 of the light-emitting control circuit E of the odd-numbered row is connected to the first group of voltage signal lines 310, and the voltage signal end 210 of the light-emitting control circuit E of the even-numbered row is connected to the second group of voltage signal lines 320.

[0047] By staggering the light-emitting control circuits E of adjacent rows and connecting the voltage signal terminals 210 of the light-emitting control circuits E of odd-numbered rows to the same set of voltage signal lines 300 and connecting the voltage signal terminals 210 of the light-emitting control circuits E of even-numbered rows to the same set of voltage signal lines 300, wiring is facilitated and uniform control of the light-emitting control circuits E of odd-numbered rows or even-numbered rows is facilitated.

[0048] With reference to Figure 5 In one embodiment, the gate drive circuits S are distributed on at least one side of the display area 100 in the width direction X, and each gate drive circuit S can be arranged on one side of the display area 100 in the width direction X in the non-display area 200 or can be uniformly arranged on both sides of the display area 100 in the width direction X in the non-display area 200.

[0049] In this embodiment, the gate drive circuits S of adjacent rows are staggered in the column direction. Specifically, each gate drive circuit S on the same side of the display area 100 in the width direction X can be distributed in an S shape along the length direction Y of the display panel, the gate drive circuits S of odd-numbered rows can be located in the same column, the gate drive circuits S of even-numbered rows can be located in the same column, and the gate drive circuits S of odd-numbered rows and even-numbered rows are located in different columns. Among them, the gate drive circuits S of odd-numbered rows are located in the same column as the light-emitting control circuits E of even-numbered rows, and the gate drive circuits S of even-numbered rows are located in the same column as the light-emitting control circuits E of odd-numbered rows. In the length direction Y, the gate drive circuits S and the light-emitting control circuits E are arranged alternately.

[0050] With reference to Figure 6 The voltage signal terminals 210 of the gate drive circuits S of odd-numbered rows are connected to the second set of voltage signal lines 320, and the voltage signal terminals 210 of the gate drive circuits S of even-numbered rows are connected to the first set of voltage signal lines 310. That is, the voltage signal terminals 210 of the gate drive circuits S of odd-numbered rows and the voltage signal terminals 210 of the light-emitting control circuits E of even-numbered rows share the second set of voltage signal lines 320, and the voltage signal terminals 210 of the gate drive circuits S of even-numbered rows and the voltage signal terminals 210 of the light-emitting control circuits E of odd-numbered rows share the first set of voltage signal lines 310. Since the gate drive circuits S of odd-numbered rows are located in the same column as the light-emitting control circuits E of even-numbered rows, and the gate drive circuits S of even-numbered rows are located in the same column as the light-emitting control circuits E of odd-numbered rows, wiring of the first set of voltage signal lines 310 and the second set of voltage signal lines 320 is facilitated.

[0051] In this embodiment, each set of voltage signal lines 300 is connected to a driving chip, and the driving chip controls each set of voltage signal lines 300 to output corresponding voltage values to the light-emitting control circuits E and the gate drive circuits S.

[0052] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the application encompasses all such possible combinations.

[0053] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area surrounding the display area; the display area is provided with a plurality of pixel driving circuits, each of which comprises a light-emitting control signal end; the non-display area is provided with a plurality of light-emitting control circuits, and the output end of each light-emitting control circuit is connected to the light-emitting control signal end of the corresponding pixel driving circuit; Each of the light-emitting control circuits comprises a group of voltage signal ends, and the display panel is provided with two groups of voltage signal lines; The display panel comprises a length direction and a width direction, each of the light-emitting control circuits is arrayed on at least one side in the width direction of the display area, and the light-emitting control circuits in adjacent rows are staggered, the voltage signal ends of the light-emitting control circuits in odd-numbered rows are connected to the first group of voltage signal lines, and the voltage signal ends of the light-emitting control circuits in even-numbered rows are connected to the second group of voltage signal lines.

2. The display panel of claim 1, wherein, The non-display area is also provided with a plurality of gate driving circuits, each of the pixel driving circuits comprises a gate driving signal end, the output end of each of the gate driving circuits is connected to the gate driving signal end of the corresponding pixel driving circuit, and each of the gate driving circuits comprises a group of voltage signal ends; Each of the gate driving circuits is distributed on at least one side in the width direction of the display area, and the gate driving circuits in adjacent rows are staggered in the column direction, the voltage signal ends of the gate driving circuits in odd-numbered rows are connected to the second group of voltage signal lines, and the voltage signal ends of the gate driving circuits in even-numbered rows are connected to the first group of voltage signal lines.

3. The display panel of claim 2, wherein, In the length direction, the gate driving circuits and the light-emitting control circuits are arranged alternately.

4. The display panel of claim 1, wherein, Each of the light-emitting control circuits is arranged in cascade, and the output end of a previous row of light-emitting control circuits is connected to the input end of a next row of light-emitting control circuits.

5. The display panel of claim 2, wherein, Each of the gate driving circuits is arranged in cascade, and the output end of a previous row of gate driving circuits is connected to the input end of a next row of gate driving circuits.

6. The display panel of any of claims 1-5, wherein, One group of the voltage signal ends comprises a first voltage signal end and a second voltage signal end, and one group of voltage signal lines comprises a first voltage signal line and a second voltage signal line, the first voltage signal line is connected to the first voltage signal end, and the second voltage signal line is connected to the second voltage signal end.

7. The display panel of claim 6, wherein, The first voltage signal line provides a low-level signal, and the second voltage signal line provides a high-level signal.

8. The display panel of claim 1, wherein, Each group of voltage signal lines is connected to a driving chip.

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