Memory cell and operating method thereof

Abstract

The invention provides a memory cell and an operating method thereof. The memory cell includes a substrate, a first electrode and a second electrode on the substrate, a memory layer, and a semiconductor insertion layer. The second electrode is located on the side, away from the substrate, of the first electrode, and bias voltage is applied between the first electrode and the second electrode. The storage layer is located between the first electrode and the second electrode and is in contact with the first electrode, and the material of the storage layer comprises positively charged first particles. The semiconductor insertion layer is located between the second electrode and the storage layer, and the semiconductor insertion layer is of a P type and makes contact with the storage layer. And the free hole of the P-type semiconductor insertion layer is moved out under the action of an electric field of read operation, so that an impurity center with negative electricity is generated in the semiconductor insertion layer. The impurity center is adjacent to the second electrode to inhibit the first particles from moving towards the part, close to the first electrode, in the storage layer, so that the original distribution state of the first particles can be maintained as much as possible, the stability of threshold voltage is maintained as much as possible, and the read interference resistance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage unit and an operating method thereof. Background Art

[0002] Unlike 3D X-point memory, data stored in Selector Only Memory (SOM) uses the difference in threshold voltage to store data. The results of the memory cell prototype design show that even with a processing size of 15nm, the high threshold voltage state (reset) and the low threshold voltage state (set) can be maintained. In addition, the write time of Selector Only Memory is short, and the write time can be basically consistent between the high threshold voltage state and the low threshold voltage state.

[0003] However, the study found that only selecting the memory still has the problem of read disturbance during the reading process, especially the interference with reading the "0" state. Summary of the invention

[0004] The embodiments of the present application provide a storage unit, which improves the device's ability to resist read disturbance, so as to at least partially solve the above-mentioned technical problems.

[0005] An embodiment of the present application provides a storage unit, comprising: a substrate; a first electrode and a second electrode located on the substrate, the second electrode being located on a side of the first electrode away from the substrate, and a bias voltage being applied between the first electrode and the second electrode; a storage layer located between the first electrode and the second electrode, the storage layer being in contact with the first electrode, the material of the storage layer comprising first particles, the first particles being positively charged; a semiconductor intercalation layer located between the second electrode and the storage layer, the semiconductor intercalation layer being of P type, and the semiconductor intercalation layer being in contact with the storage layer.

[0006] In some embodiments, the first particles include germanium particles, the semiconductor intercalation layer is a germanium layer doped with second particles, and the second particles are P-type particles.

[0007] In some embodiments, the second particles include at least one of boron particles, indium particles, aluminum particles, and gallium particles.

[0008] In some embodiments, the material of the storage layer includes a chalcogenide compound containing germanium.

[0009] In some embodiments, the storage layer includes a first region and a second region, the distance from the first region to the second electrode is greater than the distance from the second region to the second electrode; when a bias is applied to the first electrode and the second electrode, the atomic percentage concentration of the first particles in the first region is different from the atomic percentage concentration of the first particles in the second region.

[0010] In some embodiments, when a read operation is performed on the memory cell, the first electrode is used to apply a first level, the second electrode is used to apply a second level, and the second level is greater than the first level.

[0011] In some embodiments, when the memory cell stores a "0" state, the atomic percentage concentration of the first particles in the first region is less than the atomic percentage concentration of the first particles in the second region; when the memory cell stores a "1" state, the atomic percentage concentration of the first particles in the first region is greater than the atomic percentage concentration of the first particles in the second region.

[0012] In some embodiments, the storage unit is a storage unit in a select-only memory.

[0013] An embodiment of the present application also provides an operating method of a storage unit as in any of the above embodiments, comprising: performing a read operation on the storage unit, the read operation comprising: applying a first level to the first electrode, applying a second level to the second electrode, and the second level is higher than the first level.

[0014] In some embodiments, it also includes: performing a write operation on the storage unit, the write operation including: performing a write "0" operation, applying a third level to the first electrode, applying a fourth level to the second electrode, and the third level is higher than the fourth level; performing a write "1" operation, applying a fifth level to the first electrode, applying a sixth level to the second electrode, and the sixth level is higher than the fifth level.

[0015] In the memory cell of the embodiment of the present application, an asymmetric P-type semiconductor intercalation layer is constructed by inserting a P-type semiconductor intercalation layer between the second electrode and the memory layer, and the free holes of the P-type semiconductor intercalation layer are moved out under the electric field of the read operation, thereby generating a negatively charged impurity center in the semiconductor intercalation layer. The impurity center is adjacent to the second electrode and can attract the positively charged first particles in the second region, inhibiting the first particles from moving to the part of the memory layer close to the first electrode, so that the original distribution state of the first particles can be maintained as much as possible, thereby maintaining the stability of the threshold voltage as much as possible, and improving the device's ability to resist read disturbance.

[0016] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0019] Figure 1 is a schematic diagram of the structure of a storage unit provided by an embodiment;

[0020] Figure 2 yes Figure 1 A graph showing the current variation of the storage layer of the storage unit during the read cycle;

[0021] Figure 3 yes Figure 1 A curve diagram showing the change in activation energy of the storage layer material during the read cycle of the storage unit;

[0022] Figure 4 is a schematic diagram of the structure of a storage unit provided in some embodiments of the present application;

[0023] Figure 5 yes Figure 4 Bader charge distribution diagram of germanium particles and selenium particles in the storage layer obtained by first-principles simulation;

[0024] Figure 6 yes Figure 4 A schematic diagram of the structure of the storage unit in the middle when storing the "0" state;

[0025] Figure 7 yes Figure 4 A schematic diagram of the structure of the storage unit in the middle when storing the "1" state;

[0026] Figure 8 yes Figure 6 A schematic diagram of the distribution of the first particles and the third particles in the middle storage layer;

[0027] Fig. 9 yes Figure 7 A schematic diagram of the distribution of the first particles and the third particles in the middle storage layer;

[0028] Fig.10 yes Figure 4 A schematic diagram of the structure of the storage unit in the read "0" operation state;

[0029] Fig.11 yes Figure 4A flowchart of an operation method of a storage unit in FIG.

[0030] Description of reference numerals:

[0031] 10. Memory cell; 1. Substrate; 11. First electrode; 12. Second electrode; 13. Memory layer; 130. First particle; 131. First region; 132. Second region; 14. Semiconductor intercalation layer; 141. Second particle; 142. Impurity center; A1. First region; A2. Second region; A3. Third region. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] See also Figure 1 to Figure 3 , Figure 1 is a schematic diagram of the structure of a storage unit provided by an embodiment, Figure 2 yes Figure 1 The current variation curve of the storage layer in the storage unit during the read cycle, Figure 3 yes Figure 1 Activation energy variation curve of the storage layer material during the read cycle of the storage unit.

[0034] The memory cell 10 includes a first electrode 11, a second electrode 12, and a memory layer 13 located between the first electrode 11 and the second electrode 12. The material of the memory layer 13 includes first particles 130, and the first particles 130 are positively charged. The distribution state of the first particles 130 in the memory layer 13 mainly determines the threshold voltage of the memory layer 13 or the memory cell 10.

[0035] When performing a read "0" operation, a first level is applied to the first electrode 11, and a second level is applied to the second electrode 12, and the second level is higher than the first level. Therefore, when performing a read "0" operation, the first particles 130 are easily moved downward (towards the portion of the storage layer 13 close to the first electrode 11) under the action of the electric field, that is, the distribution of the first particles 130 in the storage layer 13 changes, resulting in a change in the threshold voltage, and then read "0" interference occurs.

[0036] Figure 2 The curve C1 represents the variation curve of the current of the storage layer 13 during the reading "1" cycle. Figure 2 Curve C2 represents the variation curve of the current of the storage layer 13 during the read “0” cycle.

[0037] contrast Figure 2 It can be seen from the curves C2 and C1 that the current of the storage layer 13 remains basically unchanged after accumulating multiple read "1" cycles, while the current of the storage layer 13 suddenly increases after accumulating multiple read "0" cycles. For example, the current suddenly increases when the read "0" cycle is accumulated for 108 times, indicating that read "0" interference occurs when the read "0" cycle is accumulated for 108 times.

[0038] Figure 3 The curve C3 represents the change curve of the activation energy of the storage layer 13 material during the reading "1" cycle. Figure 3 Curve C4 represents the change curve of the activation energy of the storage layer 13 material during the read “0” cycle.

[0039] contrast Figure 3 It can be seen from the curves C4 and C3 in FIG that the activation energy of the storage layer 13 remains substantially unchanged after multiple cycles of reading “1”, while the activation energy of the storage layer 13 material decreases after multiple cycles of reading “0”. The decrease in activation energy will cause a decrease in the threshold voltage, thereby causing read “0” interference. For example, when the activation energy suddenly decreases after 108 cycles of reading “0”, it indicates that read “0” interference occurs after 108 cycles of reading “0”.

[0040] Among them, the threshold voltage state of the memory cell 10 is mainly related to the distribution of the first particles 130 in the memory layer 13. When the distribution state of the first particles 130 in the memory layer 13 changes after multiple read "0" operations, the threshold voltage will change, thereby causing read "0" interference. In the embodiment of the present application, read "0" interference refers to the read result being 1 due to the change in the threshold voltage during the read "0" operation.

[0041] Based on the above problems, an embodiment of the present application provides a storage unit, comprising: a substrate; a first electrode and a second electrode located on the substrate, the second electrode being located on a side of the first electrode away from the substrate, and the first electrode and the second electrode being used to apply a bias voltage; a storage layer located between the first electrode and the second electrode, the storage layer being in contact with the first electrode, the material of the storage layer comprising first particles, the first particles being positively charged; a semiconductor intercalation layer located between the second electrode and the storage layer, the semiconductor intercalation layer being of P type, and the semiconductor intercalation layer being in contact with the storage layer.

[0042] In the embodiment of the present application, a P-type semiconductor intercalation layer is inserted between the second electrode and the storage layer to construct an asymmetric P-type semiconductor intercalation layer. Under the action of the electric field of the read operation, the free holes of the P-type semiconductor intercalation layer are moved out, thereby generating a negatively charged impurity center in the semiconductor intercalation layer. The impurity center is adjacent to the second electrode and can attract the positively charged first particles in the storage layer, inhibiting the first particles from moving downward (i.e., the part of the storage layer close to the first electrode), so that the original distribution state of the first particles can be maintained as much as possible, thereby maintaining the stability of the threshold voltage as much as possible, and improving the device's ability to resist read disturbance.

[0043] The structure of the storage unit provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0044] See also Figure 4 , Figure 4 1 is a schematic diagram of the structure of the storage unit provided in some embodiments of the present application. It should be noted that the storage unit 10 is a structure that has not been stored and read, that is, a structure at the time of leaving the factory. The storage unit 10 can be a storage unit in a selector only memory (SOM).

[0045] The memory cell 10 includes a substrate 1, a first electrode 11 and a second electrode 12 located on the substrate 1, a memory layer 13 and a semiconductor intercalation layer 14, wherein the second electrode 12 is located on a side of the first electrode 11 away from the substrate 1, and a bias voltage is applied between the first electrode 11 and the second electrode 12. The memory layer 13 is located between the first electrode 11 and the second electrode 12, and the memory layer 13 is in contact with the first electrode 11. The material of the memory layer 13 includes first particles 130, and the first particles 130 are positively charged. The semiconductor intercalation layer 14 is located between the second electrode 12 and the memory layer 13, and the semiconductor intercalation layer 14 is of P type, and the semiconductor intercalation layer 14 is in contact with the memory layer 13.

[0046] The storage layer 13 is in direct contact with the first electrode 11 , and the semiconductor insertion layer 14 is in direct contact with the storage layer 13 .

[0047] It should be noted that the first electrode 11, the second electrode 12, the storage layer 13 and the semiconductor intercalation layer 14 constitute a storage unit of the selected memory only, and the substrate 1 is to reflect that the second electrode 12 is the top electrode and the first electrode 11 is the bottom electrode. The first electrode 11 and the second electrode 12 are respectively connected to the address line (such as the bit line and the word line) to realize the operation of the storage unit.

[0048] In some embodiments, the sum of the thicknesses of the first electrode 11 , the second electrode 12 , and the storage layer 13 may be 15 nm to 30 nm, and the thickness of the semiconductor intercalation layer 14 may be greater than 0 and less than or equal to 5 mm.

[0049] In some embodiments, the first particles 130 include germanium particles, that is, the material of the storage layer 13 includes germanium particles.

[0050] In some embodiments, the material of the storage layer 13 includes a chalcogenide compound containing germanium. For example, the material of the storage layer 13 may include germanium (Ge) particles, selenium (Se) particles, copper (Cu) particles, arsenic (As) particles, indium (In) and antimony (Te) particles. When the memory cell 10 is in an initial state, the various particles in the storage layer 13 are uniformly distributed in the storage layer 13.

[0051] In some embodiments, the semiconductor intercalation layer 14 is a germanium layer doped with second particles 141, the second particles 141 are P-type particles, and a large number of positively charged free holes (i.e., P-type particles) exist in the P-type semiconductor intercalation layer 14. Since the substrate of the semiconductor intercalation layer 14 is germanium, which is the same as the first particles 130 (germanium particles) in the storage layer 13, the introduction of additional elements can be reduced, thereby improving the preparation yield, reducing defects and reducing costs.

[0052] In some embodiments, the second particles 141 may include at least one of boron particles, indium particles, aluminum particles, and gallium particles.

[0053] In some embodiments, the substrate of the semiconductor intercalation layer 14 may also be SiGe, that is, the semiconductor intercalation layer 14 is a SiGe layer doped with second particles 141 .

[0054] In some embodiments, the substrate of the semiconductor insertion layer 14 may also be silicon (Si) or silicon carbide (SiC).

[0055] When the substrate of the semiconductor intercalation layer 14 is silicon (Si) or silicon carbide (SiC), the second particles 141 may include nitrogen, that is, the semiconductor intercalation layer 14 is a silicon layer or a silicon carbide layer doped with nitrogen.

[0056] See also Figure 5 , Figure 5 yes Figure 4 The Bader charge distribution diagram of the germanium particles and selenium particles in the storage layer obtained by first principle simulation. It can be seen that the germanium particles lose electrons in the amorphous system of the storage layer 13 and behave as cations; the selenium particles gain electrons and behave as anions with negative charges. Therefore, when the first particles 130 in the storage layer 13 are germanium, the first particles 130 are positively charged.

[0057] See also Figure 6 and Figure 7 , Figure 6 yes Figure 4 The schematic diagram of the structure of the storage unit when storing the "0" state. Figure 7 yes Figure 4 Schematic diagram of the structure of the storage unit when storing the "1" state.

[0058] The storage layer 13 may include a first region 131 and a second region 132, wherein the distance between the first region 131 and the second electrode 12 is greater than the distance between the second region 132 and the second electrode 12. That is, the first region 131 is closer to the first electrode 11 than the second region 132, that is, the second region 132 is close to the semiconductor intercalation layer 14, and the first region 131 is close to the first electrode 11.

[0059] In some embodiments, the distance from the first region 131 to the second electrode 12 may be the thickness of the first region 131 plus the thickness of the semiconductor intercalation layer 14, and the distance from the second region 132 to the second electrode 12 may be the thickness of the semiconductor intercalation layer 14. It should be noted that the "thickness" in the embodiments of the present application refers to the size of the structure along the film stacking direction.

[0060] In some embodiments, the thickness of the first region 131 may be equal to the thickness of the second region 132 .

[0061] When the first electrode 11 and the second electrode 12 are biased, the atomic percentage concentration of the first particles 130 in the first region 131 is different from the atomic percentage concentration of the first particles 130 in the second region 132. Therefore, by applying a bias to the first electrode 11 and the second electrode 12, the concentration distribution of the first particles 130 can be changed to obtain different threshold voltages, so that different threshold voltages can be used to store data, such as storing "0" or "1".

[0062] The "atomic percentage concentration" refers to the ratio of the number of the first particles 130 to the number of all particles in the storage layer 13. It should be noted that the "concentration" in the embodiments of the present application refers to the atomic percentage concentration.

[0063] like Figure 6 As shown, when the memory cell 10 stores a “0” state, the atomic percentage concentration of the first particles 130 in the first region 131 is less than the atomic percentage concentration of the first particles 130 in the second region 132 .

[0064] The storage unit 10 can store the "0" state through a write "0" operation. For example, a third level is applied to the first electrode 11 and a fourth level is applied to the second electrode 12, and the third level is higher than the fourth level. Therefore, the first particles 130 will move to the second area 132 under the action of the electric field, so that the concentration of the first particles 130 in the second area 132 is greater than the concentration of the first particles 130 in the first area 131.

[0065] Due to the influence of the third level and the fourth level, the semiconductor intercalation layer will also produce negatively charged impurity centers, thereby constructing an internal electric field with the first particles in the second region, increasing the ability of the reverse electric field (direction from the first electrode to the second electrode), thereby optimizing the current and time required for the device to write "0" (or reset).

[0066] like Figure 7 As shown, when the memory cell 10 stores a “1” state, the atomic percentage concentration of the first particles 130 in the first region 131 is greater than the atomic percentage concentration of the first particles 130 in the second region 132 .

[0067] The storage unit 10 can store the "1" state through a write "1" operation. For example, a fifth level is applied to the first electrode 11 and a sixth level is applied to the second electrode 12, and the sixth level is higher than the fifth level. Therefore, the first particles 130 will move toward the first area 131 under the action of the electric field, so that the concentration of the first particles 130 in the first area 131 is greater than the concentration of the first particles 130 in the second area 132.

[0068] In some embodiments, the material of the semiconductor intercalation layer 14 further includes a third particle (not shown), which may be selenium. When the first electrode 11 and the second electrode 12 are biased, the atomic percentage concentration of the third particle in the first region 131 is different from the atomic percentage concentration of the third particle in the second region 132.

[0069] Depend on Figure 5 It can be seen that the selenium particles are negatively charged after obtaining electrons in the storage layer 13, so the distribution of the selenium particles in the storage layer 13 is opposite to the distribution of the germanium particles in the storage layer 13 during storage. When the storage unit 10 stores the "0" state, the level of the first electrode 11 is greater than the level of the second electrode 12, and the negatively charged selenium particles will move to the first area 131, so that the atomic percentage concentration of the third particles in the first area 131 is greater than the atomic percentage concentration of the third particles in the second area 132. When the storage unit 10 stores the "1" state, the level of the first electrode 11 is less than the level of the second electrode 12, and the negatively charged selenium particles will move to the second area 132, so that the atomic percentage concentration of the third particles in the second area 132 is greater than the atomic percentage concentration of the third particles in the first area 131.

[0070] In some embodiments, the material of the semiconductor intercalation layer 14 further includes fourth particles (not shown), which may be copper particles. When the first electrode 11 and the second electrode 12 are biased, the atomic percentage concentration of the fourth particles in the first region 131 is different from the atomic percentage concentration of the fourth particles in the second region 132.

[0071] The copper particles lose electrons in the storage layer 13 and are positively charged. When the storage unit 10 stores the "0" state, the level of the first electrode 11 is greater than the level of the second electrode 12, and the positively charged copper particles move to the second region 132, so the atomic percentage concentration of the fourth particles in the second region 132 is greater than the atomic percentage concentration of the fourth particles in the first region 131. When the storage unit 10 stores the "1" state, the level of the first electrode 11 is less than the level of the second electrode 12, and the positively charged copper particles move to the first region 131, so the atomic percentage concentration of the fourth particles in the first region 131 is greater than the atomic percentage concentration of the fourth particles in the second region 132.

[0072] See also Figure 8 and Fig. 9 , Figure 8 yes Figure 6 Schematic diagram of the distribution of the first particles and the third particles in the storage layer, Fig. 9 yes Figure 7 Schematic diagram of the distribution of the first particles and the third particles in the storage layer. The horizontal axis corresponding to the position of the bottom surface of the first electrode 11 is 0, the horizontal axis represents the distance between each position of the storage unit 10 and the bottom surface of the first electrode 11, and the vertical axis represents the atomic percentage concentration at the corresponding position.

[0073] Figure 8 and Fig. 9 Along the direction of the horizontal axis, there are the first region A1, the second region A2 and the third region A3. The first region A1 corresponds to the position of the first electrode 11, that is, the length of the horizontal axis corresponding to the first region A1 represents the thickness of the first electrode 11; the second region A2 corresponds to the position of the storage layer 13, that is, the length of the horizontal axis corresponding to the second region A2 represents the thickness of the storage layer 13; the third region A3 corresponds to the position of the second electrode 12, that is, the length of the horizontal axis corresponding to the third region A3 can represent the thickness of the second electrode 12. The horizontal axis in the second region A2 corresponds to the position of the storage layer 13 that is gradually far away from the first electrode 11, that is, corresponds to the position of the storage layer 13 that is gradually close to the second electrode 12.

[0074] The curve L1 represents the distribution of the first particles 130 at different thickness positions of the storage layer 13 , and the curve L2 represents the distribution of the third particles at different thickness positions of the storage layer 13 .

[0075] The position corresponding to the horizontal coordinate in the middle of the second area A2 can be used as the boundary between the first area 131 and the second area 132 in the storage layer 13. The concentration of the first particles 130 in the first area 131 changes gradually, and the concentration of the first particles 130 in the second area 132 also changes gradually. The atomic percentage concentration of the first particles 130 in the first area 131 can be regarded as the ratio of the number of all the first particles 130 in the first area 131 to the number of all the particles in the storage layer 13, and the atomic percentage concentration of the first particles 130 in the second area 132 can be regarded as the ratio of the number of all the first particles 130 in the second area 132 to the number of all the particles in the storage layer 13.

[0076] Depend on Figure 8 From the curve L1, it can be seen that when the memory cell 10 stores the "0" state, the first particles 130 are mainly located near the second electrode 12, and the first particles 130 are mainly concentrated in the second region 132, so the atomic percentage concentration of the first particles 130 in the second region 132 is greater than the atomic percentage concentration of the first particles 130 in the first region 131. Fig. 9 It can be seen from the curve L1 that when the memory cell 10 stores the “1” state, the first particles 130 are mainly located near the first electrode 11 , and the first particles 130 are mainly concentrated in the first region 131 , so the atomic percentage concentration of the first particles 130 in the first region 131 is greater than the atomic percentage concentration of the first particles 130 in the second region 132 .

[0077] Depend on Figure 8 From the curve L2, it can be seen that when the memory cell 10 stores the "0" state, the third particles are mainly located near the first electrode 11, and the third particles are mainly concentrated in the first region 131, so the atomic percentage concentration of the third particles in the first region 131 is greater than the atomic percentage concentration of the third particles in the second region 132. Fig. 9 It can be seen from the curve L2 that when the memory cell 10 stores the “1” state, the third particles are mainly located near the second electrode 12 , and the third particles are mainly concentrated in the second region 132 , so the atomic percentage concentration of the third particles in the second region 132 is greater than the atomic percentage concentration of the third particles in the first region 131 .

[0078] See also Fig.10 , Fig.10 yes Figure 4 Schematic diagram of the structure of the storage unit in the read "0" operation state.

[0079] When a read operation is performed on the storage unit 10 , the first electrode 11 is used to apply a first level, and the second electrode 12 is used to apply a second level, and the second level is greater than the first level.

[0080] The operation in which the level of the second electrode 12 is greater than the level of the first electrode 11 can be called a forward operation. Since the level of the second electrode 12 is also greater than the level of the first electrode 11 during the write "1" operation, the write "1" operation can also be called a forward operation; since the level of the second electrode 12 is less than the level of the first electrode 11 during the write "0" operation, the write "0" operation can be called a reverse operation.

[0081] It can be understood that performing a read operation when the memory cell 10 stores a "0" state is called a read "0" operation; performing a read operation when the memory cell 10 stores a "1" state is called a read "1" operation.

[0082] Since the voltage operation directions of the read "0" operation and the write "0" operation are opposite, that is, the electric field directions are opposite, so when performing a read "0" operation, the first particles 130 in the second area 132 tend to move toward the first area 131 under the action of the electric field. This will cause the distribution state of the first particles 130 in the storage layer 13 when the "0" state is originally stored to change, thereby causing the threshold voltage to change, and then read "0" interference will occur, that is, the read result may be "1".

[0083] like Fig.10 As shown, in the storage unit 10 provided by the embodiment of the present application, in the read operation state, the positively charged free holes in the P-type semiconductor intercalation layer 14 move toward the second electrode 12, thereby generating a negatively charged impurity center 142 in the semiconductor intercalation layer 14. The negatively charged impurity center 142 is adjacent to the second region 132, and can attract the positively charged first particles 130 in the second region 132, inhibiting the first particles 130 in the second region 132 from moving toward the first region 131, thereby maintaining the distribution of the first particles 130 in the storage layer 13 when the "0" state is originally stored as much as possible, thereby maintaining the stability of the threshold voltage and reducing the read "0" interference. In addition, this inhibitory effect has a strong electric field correlation and can change with the change of the electric field, that is, the greater the electric field strength formed by the bias voltage between the first electrode 11 and the second electrode 12 in the read operation state, the greater the inhibitory effect, thereby achieving adaptive adjustment of the inhibitory effect.

[0084] Accordingly, the present application also provides an operation method of the storage unit in any of the above embodiments, see Fig.11 , see Fig.11 , Fig.11 yes Figure 4 A flow chart of an operation method of a storage unit in FIG. 1 , wherein the operation method comprises:

[0085] Step S1, performing a read operation on the storage unit, the read operation comprising: applying a first level to the first electrode, applying a second level to the second electrode, and the second level is higher than the first level;

[0086] Step S2, performing a write operation on the storage unit, the write operation comprising: performing a write "0" operation, applying a third level to the first electrode, applying a fourth level to the second electrode, and the third level is higher than the fourth level.

[0087] In some embodiments, the write operation further includes: performing a write "1" operation, applying a fifth level to the first electrode, applying a sixth level to the second electrode, and the sixth level is higher than the fifth level.

[0088] The operation method of the storage unit can refer to the above Figure 6 , Figure 7 and Fig.10 The relevant description in will not be repeated here.

[0089] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0092] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A storage unit, characterized in that: include: substrate; A first electrode and a second electrode located on the substrate, the second electrode being located on a side of the first electrode away from the substrate, and a bias voltage being applied between the first electrode and the second electrode; A storage layer located between the first electrode and the second electrode, the storage layer is in contact with the first electrode, the material of the storage layer includes first particles, and the first particles are positively charged; A semiconductor intercalation layer is located between the second electrode and the storage layer, the semiconductor intercalation layer is P-type, and the semiconductor intercalation layer is in contact with the storage layer.

2. The storage unit according to claim 1, characterized in that The first particles include germanium particles, the semiconductor intercalation layer is a germanium layer doped with second particles, and the second particles are P-type particles.

3. The storage unit according to claim 2, characterized in that The second particles include at least one of boron particles, indium particles, aluminum particles, and gallium particles.

4. The storage unit according to any one of claims 1 to 3, characterized in that: The material of the storage layer includes a chalcogenide compound containing germanium.

5. The storage unit according to claim 1 or 3, characterized in that: The storage layer includes a first region and a second region, the distance from the first region to the second electrode is greater than the distance from the second region to the second electrode; when a bias is applied to the first electrode and the second electrode, the atomic percentage concentration of the first particles in the first region is different from the atomic percentage concentration of the first particles in the second region.

6. The storage unit according to claim 5, characterized in that When a read operation is performed on the storage unit, the first electrode is used to apply a first level, and the second electrode is used to apply a second level, and the second level is greater than the first level.

7. The storage unit according to claim 5, characterized in that When the memory cell stores a "0" state, the atomic percentage concentration of the first particles in the first region is less than the atomic percentage concentration of the first particles in the second region; When the memory cell stores a “1” state, the atomic percent concentration of the first particles in the first region is greater than the atomic percent concentration of the first particles in the second region.

8. The storage unit according to claim 1, characterized in that The storage unit is a storage unit in the selected memory only.

9. A method for operating a storage unit according to any one of claims 1 to 8, characterized in that: include: Performing a read operation on the storage unit, the read operation comprising: A first level is applied to the first electrode, and a second level is applied to the second electrode, and the second level is higher than the first level.

10. The operating method according to claim 9, characterized in that: Also includes: Performing a write operation on the storage unit, the write operation comprising: Performing a write "0" operation, applying a third level to the first electrode, applying a fourth level to the second electrode, and the third level is higher than the fourth level; A write “1” operation is performed, a fifth level is applied to the first electrode, a sixth level is applied to the second electrode, and the sixth level is higher than the fifth level.

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