Semiconductor device, memory system, and method for preventing interference of semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device, a memory system, and a method for anti-interference of a semiconductor device. The semiconductor device includes a substrate, a transistor, and a bit line. The substrate includes at least one storage plane region, wherein the storage plane region includes a first area at an edge of the storage plane region and a second area different from the first area. The transistor is disposed in the storage plane region and includes a source and a drain. The bit line is connected to one of the source and the drain. The plurality of bit lines includes a first type of bit line and a second type of bit line. The first type of bit line extends in a first direction parallel to the storage plane region in the first area. The second type of bit line extends in the first direction and passes through the first area and the second area. At least one of the plurality of first type of bit lines is connected to at least one of the plurality of second type of bit lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor design and fabrication, and more particularly, to a semiconductor device, a memory system, and a method for anti-interference of a semiconductor device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is one of the important storage components in electronic systems. For example, a semiconductor device can include memory cells composed of capacitors and transistors, where a plurality of memory cells can be arranged in a two-dimensional array. To further reduce the size of the two-dimensional array, the transistors can include Vertical Gate Transistors (VGTs).

[0003] However, as the feature size of the semiconductor device continues to shrink, the power consumption continues to decrease, and the capacitance value of the memory cell continues to decrease, the semiconductor device has a problem of a decrease in sense margin, making the interference of coupled noise on the semiconductor device increasingly prominent. SUMMARY

[0004] The present application provides a semiconductor device, a memory system, and a method for anti-interference of a semiconductor device, which can at least partially solve the above problems or other problems in the art.

[0005] In one aspect, the present application provides a semiconductor device, comprising: a substrate comprising at least one memory plane region, wherein the memory plane region comprises a first area at an edge of the memory plane region and a second area different from the first area; a transistor disposed in the memory plane region and comprising a source and a drain; a bit line connected to one of the source and the drain, wherein a plurality of the bit lines comprise a first type of bit line and a second type of bit line, the first type of bit line extends in a first direction parallel to the memory plane region in the first area, the second type of bit line extends in the first direction and passes through the first area and the second area; and at least one of the plurality of the first type of bit line is connected to at least one of the plurality of the second type of bit line.

[0006] In one embodiment of the present application, the transistor further comprises a gate structure; and the semiconductor device further comprises a word line connected to the gate structure, wherein a plurality of the word lines comprise a first type of word line extending in a second direction intersecting the first direction in the first area; and at least one of the plurality of the first type of word line is connected to at least one of the plurality of the second type of bit line.

[0007] In one embodiment of the present application, the plurality of word lines further comprises second type word lines extending along the second direction and passing through the first region and the second region; and the plurality of first type word lines comprises first type first word lines and first type second word lines, wherein the first type first word lines are located between the second type word lines and the first type second word lines in the first direction; and at least one of the plurality of first type second word lines is connected with at least one of the plurality of second type bit lines.

[0008] In one embodiment of the present application, the semiconductor device further comprises a first electronic switch connecting at least one of the plurality of first type word lines with at least two of the plurality of second type bit lines.

[0009] In one embodiment of the present application, the plurality of first type bit lines comprises first type first bit lines and first type second bit lines, wherein the first type first bit lines are located between the second type bit lines and the first type second bit lines in a second direction, the second direction intersecting the first direction; and at least one of the plurality of first type second bit lines is connected with at least one of the plurality of second type bit lines.

[0010] In one embodiment of the present application, the semiconductor device further comprises a second electronic switch connecting at least one of the plurality of first type bit lines with at least two of the plurality of second type bit lines.

[0011] In one embodiment of the present application, the plurality of second type bit lines comprises a plurality of second type first bit lines, wherein the plurality of second type first bit lines are equidistantly spaced along a second direction, the second direction intersecting the first direction; and at least one of the plurality of first type bit lines is connected with at least one of the plurality of second type first bit lines.

[0012] In one embodiment of the present application, the semiconductor device further comprises a third electronic switch connecting at least one of the plurality of first type bit lines with at least one of the plurality of second type first bit lines.

[0013] In one embodiment of the present application, the transistor comprises a vertical gate transistor, the vertical gate transistor comprising a semiconductor body extending along a third direction perpendicular to the storage plane region, wherein the semiconductor body comprises two ends opposite in the third direction and at least one side surface between the two ends; the source and the drain are respectively disposed at the two ends; and a gate structure of the transistor is located at the at least one side surface.

[0014] Another aspect of the present application provides a storage system, which comprises the semiconductor device provided by any one of the aspects of the present application and a controller coupled to the semiconductor device, wherein the controller is configured to store data into the semiconductor device.

[0015] Yet another aspect of the present application provides a method for anti-interference of a semiconductor device, wherein the semiconductor device comprises a substrate and a bit line, wherein the substrate comprises at least one memory plane region, the memory plane region comprises a first area located at an edge of the memory plane region and a second area different from the first area, and the bit line comprises a first type of bit line and a second type of bit line, the first type of bit line extends in a first direction parallel to the memory plane region in the first area, the second type of bit line extends in the first direction and passes through the first area and the second area, at least one of the first type of bit line is connected to at least one of the second type of bit line, and wherein the method comprises: applying a first voltage signal to at least one of the first type of bit line, wherein the value of the first voltage signal Vblfix satisfies 0≤Vblfix≤Vdd, where Vdd is the highest working voltage of the second type of bit line.

[0016] In an embodiment of the present application, the semiconductor device further comprises a word line extending in a second direction intersecting the first direction, and a plurality of the word line comprises a first type of word line and a second type of word line, wherein the first type of word line extends in the second direction intersecting the first direction in the first area, the second type of word line extends in the second direction and passes through the first area and the second area, and the method further comprises: applying a second voltage signal to at least one of the first type of word line, wherein the value of the second voltage signal Vwlfix satisfies Vwlfix≤Vpt, where Vpt is the highest working voltage of the second type of word line.

[0017] In an embodiment of the present application, the plurality of the first type of word line comprises a first type of first word line and a first type of second word line, wherein the first type of first word line is located between the second type of word line and the first type of second word line in the first direction, and the method further comprises: applying the second voltage signal to at least one of the first type of second word line.

[0018] In an embodiment of the present application, the method further comprises: applying a third voltage signal different from the second voltage signal to at least one of the first type of first word line, wherein the value of the third voltage signal Vwln satisfies Vwln≤0.

[0019] In an embodiment of the present application, the value of the third voltage signal Vwln satisfies Vwln≤Vwlfix, where Vwlfix is the value of the second voltage signal.

[0020] In one embodiment of the present application, the semiconductor device further comprises a first electronic switch connecting at least one of the plurality of first type word lines and at least two of the plurality of second type bit lines, wherein a bit line addressing signal is applied to the first electronic switch.

[0021] In one embodiment of the present application, the plurality of first type bit lines comprises a first type first bit line and a first type second bit line, wherein in a second direction intersecting the first direction, the first type first bit line is located between the second type bit line and the first type second bit line, and the method further comprises: applying the first voltage signal to at least one of the plurality of first type second bit lines.

[0022] In one embodiment of the present application, the method further comprises: applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first type first bit lines.

[0023] In one embodiment of the present application, the method further comprises: the fourth voltage signal value Vblp and the first voltage signal value Vblfix satisfy: Vblp≤Vblfix.

[0024] In one embodiment of the present application, the semiconductor device further comprises a second electronic switch connecting at least one of the plurality of first type bit lines and at least two of the plurality of second type bit lines, wherein a bit line addressing signal is applied to the second electronic switch.

[0025] The semiconductor device, memory system and method for anti-interference of semiconductor device provided by at least one embodiment of the present application, the semiconductor device comprises a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line comprises a first type bit line located at the edge of the storage plane area and a second type bit line different from the first type bit line, the second type bit line has an addressing function, by connecting at least one of the plurality of first type bit lines and at least one of the plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby improving the self capacitance Cgnd of the second type bit line (the self capacitance Cgnd can be understood as the sum of all the remaining capacitances in the total capacitance Ctotal of the second type bit line except the bit line-to-bit line capacitance), on this basis, the total capacitance Ctotal of the second type bit line is also improved, thus the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple is improved, so that the interference of the coupling noise on the semiconductor device is reduced, and the sensing margin of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present application will become more apparent from the following detailed description, when read in conjunction with the accompanying drawings. In the drawings, which are not intended to limit the application, unless otherwise specified:

[0027] Figure 1 is a top view of a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 2 is Figure 1 is a schematic diagram showing the positional relationship between a bit line and a substrate;

[0029] Figure 3 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present application and a structure of a memory cell therein;

[0030] Figure 4 is a top view of a semiconductor device according to an exemplary embodiment of the present application;

[0031] Figure 5 is a sensing margin test effect diagram of a semiconductor device without taking anti-interference measures;

[0032] Figure 6 is a sensing margin test effect diagram of a semiconductor device according to an exemplary embodiment of the present application;

[0033] Figure 7 is a flowchart of a method of anti-interference of a semiconductor device according to an exemplary embodiment of the present application;

[0034] Figure 8 is a flowchart of a method of anti-interference of a semiconductor device according to an exemplary embodiment of the present application;

[0035] Figure 9 is a flowchart of a method of anti-interference of a semiconductor device according to an exemplary embodiment of the present application;

[0036] Figure 10 is a flowchart of a method of anti-interference of a semiconductor device according to an exemplary embodiment of the present application; and

[0037] Figure 11 is a schematic diagram of a memory system structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive of exemplary embodiments of the present application and is not intended to limit the scope of the present application in any way. Throughout the specification, like reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that the terms first, second, third, etc. are used herein only to separate one feature from another, and do not denote any order or precedence of the features, especially not any order of priority. Thus, a first area discussed in the present application can also be termed a second area, and vice versa, without departing from the teaching of the present application.

[0040] In the drawings, the thicknesses of components, sizes, and shapes can be exaggerated slightly for ease of explanation. The drawings are merely schematic and are not intended to be drawn to scale. As used herein, the terms "substantially", "approximately", and like terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or computing process.

[0041] It should also be understood that the terms "comprise", "comprising", "have", "having", "contain", "containing", and / or "include" and / or "including" when used in this specification and in the following claims are open-ended terms that is, terms that can be used to express that a feature, element, and / or component is present in the thing being described, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Also, when describing the embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the term "exemplary" is intended to mean an example or an illustration.

[0042] Unless otherwise defined, all terms used in this document including technical terms and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that the words "comprise", "comprising", "have", "having", "contain", "containing", and / or "include" and / or "including" when used in this specification and in the following claims are open-ended terms that is, terms that can be used to express that a feature, element, and / or component is present in the thing being described, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Also, when describing the embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the term "exemplary" is intended to mean an example or an illustration.

[0043] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other, as long as there is no conflict. In addition, the specific steps included in the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel, unless explicitly limited or contrary to the context.

[0044] Further, when "connected" or "coupled" is used in the present application, it can mean direct contact or indirect contact between the corresponding components, unless there is an explicit other limitation or can be derived from the context.

[0045] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0046] Some embodiments of the present application provide a semiconductor device. Figure 1 is a top view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 2 is Figure 1 is a schematic diagram showing the positional relationship between the bit lines 300 and the substrate 100. Figure 3 is a schematic diagram of a semiconductor device 1000 and a structure of a memory cell 200 therein according to an exemplary embodiment of the present application. Figure 4 is a top view of a semiconductor device 1000 according to an exemplary embodiment of the present application.

[0047] As shown in Figures 1-4 , the semiconductor device 1000 includes a substrate 100, a transistor 210, and bit lines 300. The substrate 100 includes at least one memory plane region 101, wherein the memory plane region 101 includes a first area 01 at an edge of the memory plane region 101 and a second area 02 different from the first area 01. The transistor 210 is disposed in the memory plane region 101 and includes a source 201 and a drain 202. The bit lines 300 are connected to one of the source 201 and the drain 202, wherein the plurality of bit lines 300 includes a first type of bit line 301 and a second type of bit line 302. The first type of bit line 301 extends in a first direction (y direction) parallel to the memory plane region 101 in the first area 01, for example, a first bit line 310, a second bit line 320, a third bit line 330, a fourth bit line 340, a fifth bit line 350, a sixth bit line 360, and a seventh bit line 370. The second type of bit line 302 extends in the y direction and passes through the first area 01 and the second area 02, for example, an eighth bit line 380 and a ninth bit line 390. At least one of the plurality of first type of bit lines 301 is connected to at least one of the plurality of second type of bit lines 302. It should be noted that the present application does not limit the number of the first type of bit lines or the second type of bit lines, and the specific position of each of the first type of bit lines or the second type of bit lines in the first area or the second area of the memory plane region.

[0048] It should be noted that the semiconductor device 1000 can be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, which is not limited by the present application.

[0049] According to the semiconductor device provided by at least one of the embodiments of the present application, the semiconductor device comprises a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line comprises a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, the capacitance of at least one first type of bit line can be superimposed on the capacitance of at least one second type of bit line by connecting the at least one first type of bit line with the at least one second type of bit line, thereby increasing the self-capacitance Cgnd of the second type of bit line (the self-capacitance Cgnd can be understood as the sum of all the remaining capacitances of the total capacitance Ctotal of the second type of bit line except the inter-bit line capacitance), on this basis, the total capacitance Ctotal of the second type of bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type of bit line and the coupling capacitance Ccouple, so that the interference of the coupling noise on the semiconductor device is reduced, and the sensing margin of the semiconductor device is improved. Figure 5 is a sensing margin test effect diagram of a semiconductor device without taking anti-interference measures; Figure 6 is a sensing margin test effect diagram of the semiconductor device 1000 according to the exemplary embodiments of the present application.

[0050] Reference is made to Figure 1 , Figure 5 and Figure 6 , the sensing margin of the semiconductor device is related to the self-capacitance Cgnd, the coupling capacitance Ccouple and the total capacitance Ctotal. Among them, the total capacitance Ctotal is the sum of the self-capacitance Cgnd and the self-capacitance Cgnd, the ratio of the self-capacitance Cgnd to the total capacitance Ctotal is α, and the sensing margin is proportional to the ratio α, so that after connecting at least one first type of bit line with at least one second type of bit line and superimposing the capacitance of the at least one first type of bit line on the capacitance of the at least one second type of bit line, the self-capacitance Cgnd of the second type of bit line and the total capacitance Ctotal of the second type of bit line can be increased, and accordingly, the ratio α and the sensing margin can be increased.

[0051] Specifically, in combination with Figures 1-4 , taking a DRAM as an example, the semiconductor device 1000 can comprise a storage unit 200 composed of a capacitor 220 and a transistor 210, and a plurality of storage units 200 can be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor 210 can comprise a vertical gate transistor. In this structure, the extension direction of the channel of the transistor is perpendicular to the storage plane area 101 of the substrate 100, and the source 201 and the drain 202 of the transistor 210 can be formed at both ends of the channel extension direction of the transistor 210, and the gate structure 203 of the transistor can be formed on at least one side of the channel.

[0052] In other words, the transistor 210 can include the semiconductor pillar 204, the gate structure 203, the source 201, and the drain 202. The plurality of semiconductor pillars 204 are arranged in an array, and the gate structure 203 can be located on at least one sidewall of the semiconductor pillars 204 in the y direction.

[0053] In one embodiment of the present application, a vertical gate transistor, such as a vertical Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), can replace a conventional planar transistor as a pass transistor of a memory cell to reduce the area occupied by the pass transistor, coupling capacitance, and interconnection wiring complexity. In some embodiments, unlike a planar transistor that forms an active region in a substrate, the vertical gate transistor can include a semiconductor pillar 204 that extends vertically in the z direction on the substrate 100. The semiconductor pillar 204 can extend above the top surface of the substrate 100 to expose not only a top surface of the semiconductor pillar 204 but also one or more sidewalls of the semiconductor pillar 204.

[0054] Optionally, the semiconductor pillar 204 can have a cuboid shape to expose four sidewalls thereof. However, it is understood by those skilled in the art that the semiconductor pillar 204 can have any suitable 3-dimensional shape, such as a polyhedron shape or a cylindrical shape. In other words, a cross-section of the semiconductor pillar 204 in a plane parallel to the x direction and the y direction (hereinafter referred to as the x-y plane) can have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape, where the x direction, the y direction, and the z direction intersect each other. It is understood that, consistent with the scope of the present application, for a semiconductor pillar having a cross-section in the above-mentioned plane with a circular or elliptical shape, the semiconductor pillar can still be considered to have a plurality of sidewalls such that the gate structure contacts more than one sidewall of the semiconductor pillar. As described below with respect to fabrication, the semiconductor pillar 204 can be formed from the substrate 100 by, for example, an etching or epitaxial process, and thus can have the same semiconductor material as the substrate 100.

[0055] As an option, the material of the substrate 100 can include, but is not limited to, silicon (e.g., single-crystalline silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. For example, the substrate 100 can be a silicon substrate. Accordingly, the semiconductor pillar 204 can include at least one of the above-mentioned materials.

[0056] The vertical gate transistor can include a gate structure 203 in contact with one or more sidewalls of the semiconductor pillar 204. For example, the gate structure 203 can be located on the y-direction sidewalls of the semiconductor pillar 204. Further, on this basis, the gate structure 203 can also be located on the remaining sidewalls of the semiconductor pillar 204, which is not limited in the present application.

[0057] In some embodiments, the vertical gate transistor can further include a source 201 and a drain 202 formed at two ends of the semiconductor pillar 204 in the z-direction, respectively, which can be understood as doped regions of the semiconductor pillar 204, and can also be referred to as source and drain electrodes. Optionally, one of the source 201 and the drain 202 is connected with the bit line 300; the other of the source 201 and the drain 202 is connected with the capacitor 220.

[0058] As an option, the source 201 and the drain 202 can be doped with any suitable P-type dopant, which can include any one or combination of boron (B) or gallium (Ga). As another option, the source 201 and the drain 202 can be doped with any suitable N-type dopant, which can include any one or combination of phosphorus (P), arsenic (As) and antimony (Sb). The source 201 and the drain 202 can be separated by the gate structure 203 in the z-direction. In other words, the gate structure 203 is formed between the source 201 and the drain 202 in the z-direction. Thus, the gate structure has a gate control capability, and when a gate voltage applied to the gate structure 203 is higher than a threshold voltage of the vertical gate transistor, one or more channels of the vertical gate transistor can be formed in the semiconductor pillar 204 between the source 201 and the drain 202 in the z-direction.

[0059] In some embodiments, the vertical gate transistor is a transistor including multiple gate structures (hereinafter referred to as a multi-gate vertical gate transistor). In other words, the gate structure 203 can be in contact with more than one sidewall of the semiconductor pillar 204 to form more than one gate structure, so that more than one channel can be formed between the source 201 and the drain in operation. For example, the gate structure 203 can be located on all sidewalls of the semiconductor pillar 204.

[0060] Unlike planar transistors including only a single planar gate, due to the 3-dimensional structure of the semiconductor pillar 204 and the gate structure 203 surrounding multiple sidewalls of the semiconductor pillar 204, the multi-gate vertical gate transistor has a larger gate control area compared to the planar transistor, to achieve better channel control with smaller subthreshold swing. Further, for the purpose of increasing transistor and memory cell density, for example, the gate structure 203 can also be in contact with only a single sidewall of the semiconductor pillar 204, for example, the gate structure 203 is in contact with one of the two sidewalls of the semiconductor pillar 204 opposite in the x-direction, which is not limited in the present application.

[0061] In addition, the semiconductor device 1000 further comprises a word line 400 connected with the gate structure 203. In some embodiments, the gate structure 203 and the word line 400 can be a continuous conductive structure, the gate structure 203 can be regarded as an extension of the word line 400 to couple the semiconductor pillar 204; or the word line 400 can be regarded as an extension of the gate structure 203 to couple to the peripheral circuit.

[0062] Optionally, the plurality of word lines 400 comprises a first type of word line 401 extending along a second direction (x direction) intersecting the y direction in the first region 01, for example, the first word line 410, the second word line 420, the third word line 430, the fourth word line 440, the fifth word line 450, the sixth word line 460, the seventh word line 470 and the eighth word line 480. At least one of the plurality of first type of word lines 401 is connected with at least one of the plurality of second type of bit lines 302. It is to be noted that the number of the first type of word lines is not limited in the present application, and the specific position of each of the first type of word lines in the first region of the storage plane region is not limited in the present application.

[0063] Similarly, by connecting at least one of the plurality of first type of word lines with at least one of the plurality of second type of bit lines, the capacitance of the at least one first type of word line is superimposed on the capacitance of the at least one second type of bit line, thereby increasing the self-capacitance Cgnd of the second type of bit line, and on this basis, the total capacitance Ctotal of the second type of bit line is also increased, so that while improving the sensing margin of the semiconductor device, the ratio between the total capacitance Ctotal of the second type of bit line and the coupling capacitance Ccouple is increased, so that the interference of the coupling noise on the semiconductor device is reduced.

[0064] In addition, in some embodiments of the present application, the plurality of word lines 400 further comprises a second type of word line 402 extending along the x direction and passing through the first region 01 and the second region 02. The first type of word line 401 can comprise a first type of first word line and a first type of second word line, wherein the first type of first word line is located between the second type of word line 402 and the first type of second word line in the y direction. For example, the first type of second word line can comprise the first word line 410, the second word line 420, the fifth word line 450 and the sixth word line 460, and the first type of first word line can comprise the third word line 430, the fourth word line 440, the seventh word line 470 and the eighth word line 480, wherein the first type of first word line (for example, the third word line 430, the fourth word line 440) is located between the second type of word line 402 and the first type of second word line (for example, the first word line 410, the second word line 420) in the y direction; the first type of first word line (for example, the seventh word line 470 and the eighth word line 480) is located between the second type of word line 402 and the first type of second word line (for example, the fifth word line 450, the sixth word line 460) in the y direction. At least one of the plurality of first type of second word lines is connected with at least one of the plurality of second type of bit lines 302.

[0065] Similarly, in some embodiments of the present application, the first type of bit lines 301 can include first type of first bit lines and first type of second bit lines, wherein the first type of first bit lines are located between the second type of bit lines 302 and the first type of second bit lines in the x direction. For example, the first type of second bit lines can include the first bit line 310, the second bit line 320, the fifth bit line 350 and the sixth bit line 360, and the first type of first bit lines can include the third bit line 330, the fourth bit line 340, the seventh bit line 370, wherein the first type of first bit lines (e.g., the third bit line 330, the fourth bit line 340) are located between the second type of bit lines 302 and the first type of second bit lines (e.g., the first bit line 310, the second bit line 320); the first type of first bit lines (e.g., the seventh bit line 370) are located between the second type of bit lines 302 and the first type of second bit lines (e.g., the fifth bit line 350, the sixth bit line 360). At least one of the plurality of first type of second bit lines is connected to at least one of the plurality of second type of bit lines 302.

[0066] In addition, considering that the number of the first type of word lines and the first type of bit lines is limited, it is difficult to increase the capacity of too many second type of bit lines; and in the case that the required capacitance of the second type of bit lines is too large and a single first type of word line or first type of bit line cannot effectively increase the capacity of the second type of bit lines, in order to better solve the problem of sensing margin reduction of the semiconductor device and reduce the interference of coupling noise on the semiconductor device, as an option, the semiconductor device 1000 can further include a second electronic switch (not shown) connecting at least one of the plurality of first type of bit lines 301 to at least two of the plurality of second type of bit lines 302; as another option, the semiconductor device 1000 can further include a first electronic switch (not shown) connecting at least one of the plurality of first type of word lines 401 to at least two of the plurality of second type of bit lines 302.

[0067] Optionally, the first electronic switch or the second electronic switch can be controlled by a bit line addressing signal, and when addressing to a certain second type of bit line 302, at least one of the plurality of first type of word lines 401 or at least one of the plurality of first type of bit lines 301 can be connected to the second type of bit line 302 through the first electronic switch or the second electronic switch according to the actual situation of the second type of bit line 302, so as to improve the self-capacitance Cgnd of the second type of bit line 302. In addition, by controlling the first electronic switch or the second electronic switch through the bit line addressing signal, the working second type of bit line 302 can be effectively increased in capacity flexibly according to the bit line addressing signal, and the interference of coupling noise can be reduced.

[0068] In some embodiments of the present application, the semiconductor device 1000 can include at least one memory plane region 101 formed with semiconductor pillars 204, and a plurality of semiconductor pillars 204 arranged in an array on the memory plane region, wherein the memory plane region 101 can include a first region 01 at the edge of the memory plane region and a second region 02 different from the first region. The plurality of first type bit lines 301 or the first type word lines 401 located in the first region 01 can be used for process and electrical buffering, and thus can also be referred to as virtual bit lines or virtual word lines.

[0069] In addition, in an embodiment of the present application, in order to better solve the problem of sensing tolerance reduction of the semiconductor device and reduce the interference of coupling noise on the semiconductor device, it is necessary to find a bit line (hereinafter referred to as a second type first bit line) in the second type bit line that is relatively greatly affected by coupling noise, so as to effectively apply the first type word line or the first type bit line to the second type first bit line, and improve the anti-interference ability of the semiconductor device. As an option, the second type bit line that is relatively greatly affected by coupling noise in the semiconductor device can be found by simulating the noise condition; as another option, the position of the second type bit line that is relatively greatly affected by coupling noise in the semiconductor device has a regularity and usually appears periodically in the bit line. Optionally, a plurality of second type bit lines 302 are sequentially arranged along the x direction, wherein a plurality of second type first bit lines are equally spaced along the x direction, for example, Figure 1 The plurality of second type bit lines 302 are sequentially arranged along the x direction, and the eighth bit line 380 and the ninth bit line 390 equally spaced can be the second type first bit line that is relatively greatly affected by coupling noise. At least one of the plurality of first type bit lines or at least one of the plurality of first type word lines can be connected to at least one of the plurality of second type first bit lines.

[0070] Optionally, the semiconductor device further includes a third electronic switch connecting at least one of the plurality of first type bit lines and at least one of the plurality of second type first bit lines. Optionally, the third electronic switch can also be controlled by a bit line addressing signal.

[0071] In addition, in an embodiment of the present application, the bit line 300 and the word line 400 can each include a conductor wiring layer, wherein the conductor wiring layer can include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc.

[0072] Thus, according to at least one embodiment of the present application, a semiconductor device is provided, which includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane region, the bit line includes a first type of bit line located at an edge of the storage plane region and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of the plurality of first type of bit lines with at least one of the plurality of second type of bit lines, a capacitance of the at least one first type of bit line is superimposed on a capacitance of the at least one second type of bit line, thereby increasing an own capacitance Cgnd of the second type of bit line (which can be understood as a sum of all remaining capacitances other than the inter-bit line capacitance in a total capacitance Ctotal of the second type of bit line), and on this basis, the total capacitance Ctotal of the second type of bit line is also increased, thereby increasing a ratio between the total capacitance Ctotal of the second type of bit line and a coupling capacitance Ccouple, so that interference of the coupling noise on the semiconductor device is reduced, and a sensing margin of the semiconductor device is improved.

[0073] Some embodiments of the present application provide a method 2000 for interference reduction of a semiconductor device. Figure 7 is a flow chart of the method 2000 for interference reduction of a semiconductor device according to an exemplary embodiment of the present application.

[0074] As shown in Figures 1-4 , Figure 7 the present application provides a method 2000 for interference reduction of a semiconductor device, which includes:

[0075] S1, applying a first voltage signal to at least one of the plurality of first type of bit lines 301, wherein the first voltage signal value Vblfix and a highest operating voltage Vdd of the second type of bit line 302 satisfy: 0≤Vblfix≤Vdd,

[0076] The semiconductor device 1000 includes a substrate 100, a transistor 210, and a bit line 300. The substrate 100 includes at least one memory plane region 101, wherein the memory plane region 101 includes a first area 01 at an edge of the memory plane region 101 and a second area 02 different from the first area 01. The transistor 210 is disposed in the memory plane region 101 and includes a source 201 and a drain 202. The bit line 300 is connected to one of the source 201 and the drain 202, wherein a plurality of bit lines 300 includes a first type of bit line 301 and a second type of bit line 302. The first type of bit line 301 extends in a first direction (y direction) parallel to the memory plane region 101 in the first area 01, for example, a first bit line 310, a second bit line 320, a third bit line 330, a fourth bit line 340, a fifth bit line 350, a sixth bit line 360, and a seventh bit line 370. The second type of bit line 302 extends in the y direction and passes through the first area 01 and the second area 02, for example, an eighth bit line 380 and a ninth bit line 390. At least one of the plurality of first type of bit lines 301 is connected to at least one of the plurality of second type of bit lines 302.

[0077] Optionally, the operating voltage of the second type of bit line 302 can include 0 volt, Vdd / 2, and Vdd, wherein Vdd can be understood as a voltage corresponding to the second type of bit line 302 when writing a state "1" in the memory cell 200.

[0078] According to the semiconductor device anti-interference method provided by at least one embodiment of the present application, the semiconductor device includes a substrate, a transistor, and a bit line, wherein the substrate defines a memory plane region, the bit line includes a first type of bit line at an edge of the memory plane region and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of the plurality of first type of bit lines to at least one of the plurality of second type of bit lines, the capacitance of the at least one first type of bit line is superimposed on the capacitance of the at least one second type of bit line, thereby increasing the self-capacitance Cgnd of the second type of bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type of bit line except for the inter-bit line capacitance), on this basis, the total capacitance Ctotal of the second type of bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type of bit line and the coupling capacitance Ccouple, so that the interference of the coupling noise on the semiconductor device is reduced, and the sensing margin of the semiconductor device is improved.

[0079] Further, in one embodiment of the present application, the semiconductor device 1000 can include a memory cell 200 composed of the capacitor 220 and the transistor 210, and a plurality of memory cells 200 can be arranged in a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor 210 can include a vertical gate transistor. In this structure, the transistor 210 can include a semiconductor pillar 204 extending in the z direction, a gate structure 203, a source 201, and a drain 202. A plurality of semiconductor pillars 204 are arranged in an array, and the gate structure 203 can be located at least on one sidewall of the semiconductor pillar 204 in the y direction, where the x direction, the y direction, and the z direction intersect.

[0080] The semiconductor device 1000 further includes a word line 400 connected to the gate structure 203. The word line 400 extends in the x direction. In some embodiments, the gate structure 203 and the word line 400 can be a continuous conductive structure, the gate structure 203 can be regarded as an extension of the word line 400 to couple the semiconductor pillar 204; or the word line 400 can be regarded as an extension of the gate structure 203 to couple to the peripheral circuit.

[0081] Optionally, the plurality of word lines 400 includes a first type of word line 401 and a second type of word line 402, where the first type of word line 401 extends in the x direction in a first region 01, such as a first word line 410, a second word line 420, a third word line 430, a fourth word line 440, a fifth word line 450, a sixth word line 460, a seventh word line 470, and an eighth word line 480. The second type of word line 402 extends in the x direction and passes through the first region 01 and the second region 02.

[0082] Figure 8 is a flowchart of a semiconductor device anti-interference method 2000 according to an exemplary embodiment of the present application.

[0083] As shown in Figure 7 and Figure 8 , the semiconductor device anti-interference method 2000 can further include:

[0084] Step S2, applying a second voltage signal to at least one of the plurality of first type of word lines 401, wherein the second voltage signal value Vwlfix and the highest operating voltage Vpt of the second type of word line 402 satisfy: Vwlfix≤Vpt.

[0085] In other words, in order to reduce the interference of coupled noise on the semiconductor device and improve the sensing tolerance of the semiconductor device, the semiconductor device anti-interference method 2000 can include at least one of step S1 and step S2.

[0086] Optionally, the highest operating voltage Vpt of the second type of word line 402 can be understood as the corresponding voltage of the second type of word line 402 when the transistor 210 of the memory cell 200 is turned on.

[0087] Optionally, the first type of word lines 01 includes first type of first word lines and first type of second word lines. The first type of first word lines are located between the second type of word lines 402 and the first type of second word lines in the y direction. For example, the first type of second word lines can include the first word line 410, the second word line 420, the fifth word line 450 and the sixth word line 460, and the first type of first word lines can include the third word line 430, the fourth word line 440, the seventh word line 470 and the eighth word line 480, wherein the first type of first word lines (e.g., the third word line 430, the fourth word line 440) are located between the second type of word lines 402 and the first type of second word lines (e.g., the first word line 410, the second word line 420) in the y direction; the first type of first word lines (e.g., the seventh word line 470 and the eighth word line 480) are located between the second type of word lines 402 and the first type of second word lines (e.g., the fifth word line 450, the sixth word line 460) in the y direction. At least one of the first type of second word lines is connected with at least one of the second type of bit lines 302. Thus, to strengthen the effect of the above-mentioned anti-interference, the semiconductor device anti-interference method 2000 further includes applying a second voltage signal to at least one of the first type of second word lines.

[0088] Likewise, in some embodiments of the present application, the first type of bit lines 301 can include first type of first bit lines and first type of second bit lines, wherein the first type of first bit lines are located between the second type of bit lines 302 and the first type of second bit lines in the x direction. For example, the first type of second bit lines can include the first bit line 310, the second bit line 320, the fifth bit line 350 and the sixth bit line 360, and the first type of first bit lines can include the third bit line 330, the fourth bit line 340, the seventh bit line 370, wherein the first type of first bit lines (e.g., the third bit line 330, the fourth bit line 340) are located between the second type of bit lines 302 and the first type of second bit lines (e.g., the first bit line 310, the second bit line 320); the first type of first bit lines (e.g., the seventh bit line 370) are located between the second type of bit lines 302 and the first type of second bit lines (e.g., the fifth bit line 350, the sixth bit line 360). At least one of the first type of second bit lines is connected with at least one of the second type of bit lines 302. To strengthen the effect of the above-mentioned anti-interference, the semiconductor device anti-interference method 2000 further includes applying a first voltage signal to at least one of the first type of second bit lines.

[0089] In addition, in the process of forming the semiconductor device, in order to ensure that the performance of the bit lines and the word lines is not affected, a virtual bit line or a virtual word line can be formed in the first area 01 where the storage plane area 101 is located at the edge, usually for process and electrical buffering. It can be understood that, in some embodiments, the first type of bit lines correspond to the virtual bit lines, the first type of word lines correspond to the virtual word lines, and the second type of bit lines and the second type of word lines have addressing functions.

[0090] Figure 9 is a flowchart of a method 2000 for anti-interference of a semiconductor device according to an example embodiment of the present application. Figure 10 is a flowchart of a method 2000 for anti-interference of a semiconductor device according to an example embodiment of the present application.

[0091] As shown in FIG. 1, to balance the voltage environment in which the second type of bit lines and the second type of word lines are located, and to reduce the possibility of leakage or breakdown of the second type of bit lines and the second type of word lines, as an option, step S1 applies a first voltage signal to at least one of the plurality of first type of bit lines 301, where the value Vblfix of the first voltage signal satisfies: 0≤Vblfix≤Vdd, where Vdd is the highest working voltage of the second type of bit lines 302. For example, the first voltage signal can be: Figures 7-10 Step S11 applies a first voltage signal to at least one of the plurality of first type of second bit lines.

[0092] Step S12 applies a fourth voltage signal different from the first voltage signal to at least one of the plurality of first type of first bit lines.

[0093] As another option, step S2 applies a second voltage signal to at least one of the plurality of first type of word lines 401, where the value Vwlfix of the second voltage signal satisfies: Vwlfix≤Vpt, where Vpt is the highest working voltage of the second type of word lines 402. For example, the second voltage signal can be:

[0094] Step S21 applies a second voltage signal to at least one of the plurality of first type of second word lines.

[0095] Step S22 applies a third voltage signal different from the second voltage signal to at least one of the plurality of first type of first word lines, where the value Vwln of the third voltage signal satisfies: Vwln≤0.

[0096] It should be noted that to reduce the interference of coupling noise on the semiconductor device, improve the sensing tolerance of the semiconductor device, balance the voltage environment in which the second type of bit lines and the second type of word lines are located, and reduce the possibility of leakage or breakdown of the second type of bit lines and the second type of word lines, the method 2000 for anti-interference of a semiconductor device can include at least one of steps S11, S12, S21 and S22.

[0097] Specifically, as an option, a third voltage signal different from the second voltage signal is applied to at least one of the plurality of first type of first word lines, where the value Vwln of the third voltage signal satisfies: Vwln≤0. Alternatively, the value Vwln of the third voltage signal and the value Vwlfix of the second voltage signal satisfy: Vwln≤Vwlfix.

[0098]

[0099] ​By applying a third voltage signal with a value less than or equal to zero to at least one of the plurality of first type first word lines, the voltage environment of the second type word lines can be balanced, and the possibility of leakage or breakdown of the second type word lines can be reduced.

[0100] Alternatively, a fourth voltage signal different from the first voltage signal is applied to at least one of the plurality of first type first bit lines. Optionally, the value Vblp of the fourth voltage signal satisfies: Vblp≤Vblfix. By applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first type first bit lines, the voltage environment of the second type bit lines can be balanced, and the possibility of leakage or breakdown of the second type bit lines can be reduced. To enhance the above effect, the value of the fourth voltage signal can be less than or equal to the value of the first voltage signal.

[0101] In addition, considering that the number of first type word lines and first type bit lines is limited, it is difficult to increase the capacity of too many second type bit lines; and in the case that the required capacitance of the second type bit lines is too large, and a single first type word line or first type bit line cannot effectively increase the capacity of the second type bit lines, in order to better solve the problem of sensing margin reduction of the semiconductor device and reduce the interference of coupling noise on the semiconductor device, as an option, the semiconductor device 1000 can further include a second electronic switch (not shown) connecting at least one of the plurality of first type bit lines 301 and at least two of the plurality of second type bit lines 302; as another option, the semiconductor device 1000 can further include a first electronic switch (not shown) connecting at least one of the plurality of first type word lines 401 and at least two of the plurality of second type bit lines 302.

[0102] As an option, the semiconductor device anti-interference method 2000 further includes: by controlling the first electronic switch or the second electronic switch through the bit line addressing signal, when addressing to a certain second type bit line 302, at least one of the plurality of first type word lines 401 or at least one of the plurality of first type bit lines 301 can be connected to the second type bit line 302 through the first electronic switch or the second electronic switch according to the actual situation of the second type bit line 302, to improve the self-capacitance Cgnd of the second type bit line 302. In addition, by controlling the first electronic switch or the second electronic switch through the bit line addressing signal, the working second type bit line 302 can be effectively increased in capacity according to the bit line addressing signal, and the interference of coupling noise can be reduced.

[0103] In addition, in one embodiment of the present application, in order to better solve the problem of sensing margin reduction of the semiconductor device and reduce the interference of coupling noise on the semiconductor device, a bit line (hereinafter referred to as a second type first bit line) in the second type bit line which is relatively greatly affected by the coupling noise is found, so as to effectively apply the first type word line or the first type bit line to the second type first bit line, and improve the anti-interference capability of the semiconductor device. As an option, the second type bit line which is relatively greatly affected by the coupling noise in the semiconductor device can be found by simulating the noise condition; as another option, the position of the second type bit line which is relatively greatly affected by the coupling noise in the semiconductor device has a rule, and is usually periodically present in the bit line. Optionally, the plurality of second type bit lines 302 are sequentially arranged along the x direction, wherein the plurality of second type first bit lines are equidistantly arranged along the x direction, for example, Figure 1 The plurality of second type bit lines 302 are sequentially arranged along the x direction, wherein the eighth bit line 380 and the ninth bit line 390 which are equidistantly arranged can be the second type first bit line which is relatively greatly affected by the coupling noise, and at least one of the plurality of first type bit lines or at least one of the plurality of first type word lines can be connected with at least one of the plurality of second type first bit lines.

[0104] Optionally, the semiconductor device further comprises a third electronic switch for connecting at least one of the plurality of first type bit lines with at least one of the plurality of second type first bit lines. Optionally, the third electronic switch can also be controlled by the bit line addressing signal.

[0105] Therefore, according to the method for improving the anti-interference capability of the semiconductor device provided by at least one embodiment of the present application, the semiconductor device comprises a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line comprises a first type bit line located at the edge of the storage plane area and a second type bit line different from the first type bit line, the second type bit line has an addressing function, by connecting at least one of the plurality of first type bit lines with at least one of the plurality of second type bit lines, the capacitance of the at least one first type bit line can be superimposed on the capacitance of the at least one second type bit line, thereby improving the self capacitance Cgnd of the second type bit line (the self capacitance Cgnd can be understood as the sum of all the remaining capacitances in the total capacitance Ctotal of the second type bit line except the bit line-to-bit line capacitance), on this basis, the total capacitance Ctotal of the second type bit line is also improved, thereby improving the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of the coupling noise on the semiconductor device is reduced, and the sensing margin of the semiconductor device is improved.

[0106] In addition, Figure 11 is a structural schematic diagram of a storage system 30000 according to one embodiment of the present application.

[0107] As Figure 11As shown, at least one embodiment of yet another aspect of the present application also provides a storage system 30000. The storage system 30000 can include the semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the present application will not repeat the same. The semiconductor device 20000 can be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, and the following will be described taking a three-dimensional semiconductor device as an example.

[0108] As an option, the three-dimensional semiconductor device can include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0109] The storage system 30000 can include the semiconductor device 20000 and the controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the present application will not repeat the same. The controller 32000 can control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 can perform an operation based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 can receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 can perform an internal operation corresponding to the command on the region selected by the address.

[0110] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC and a micro- MMC, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a storage device of a personal computer memory card international association (PCMCIA) card type, a storage device of a peripheral component interconnect (PCI) type, a storage device of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided by the present application has the same beneficial effects as the semiconductor device provided by the present application due to the provision of the semiconductor device provided by the present application, and will not be repeated here.

[0111] Although the exemplary preparation method and structure of the semiconductor device are described herein, it can be understood that one or more features can be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of the example layers are only exemplary.

[0112] The above description is only the preferred embodiment of the present application and the explanation of the technical principles. It should be understood by those skilled in the art that the protective scope of the present application is not limited to the technical solutions formed by the selected combinations of the above technical features, and also covers other technical solutions formed by the combinations of the above technical features or their equivalent features without departing from the technical concepts. For example, the technical solutions formed by the mutual replacement of the above features and the technical features disclosed in the present application (but not limited to) with similar functions.

Claims

1. A semiconductor device, characterized by, comprises a first region at an edge of the storage plane region and a second region different from the first region; a transistor disposed in the storage plane region and comprising a source, a drain, and a gate structure; a word line connected to the gate structure; and a bit line connected to one of the source and the drain, wherein a plurality of the bit lines comprises a first type of bit line and a second type of bit line, the first type of bit line extending in a first direction parallel to the storage plane region in the first region, the second type of bit line extending in the first direction and passing through the first region and the second region; a plurality of the word lines comprises a first type of word line extending in a second direction intersecting the first direction in the first region; at least one of the plurality of the first type of word lines is connected to at least one of the plurality of the second type of bit lines; and at least one of the plurality of the first type of bit lines is connected to at least one of the plurality of the second type of bit lines.

2. The semiconductor device of claim 1, wherein the plurality of the word lines further comprises a second type of word line extending in the second direction and passing through the first region and the second region; and the plurality of the first type of word lines comprises a first type first word line and a first type second word line, wherein the first type first word line is located between the second type word line and the first type second word line in the first direction; and at least one of the plurality of the first type second word lines is connected to at least one of the plurality of the second type of bit lines.

3. The semiconductor device of claim 1, wherein the semiconductor device further comprises a first electronic switch connecting at least one of the plurality of the first type of word lines to at least two of the plurality of the second type of bit lines.

4. The semiconductor device of claim 1, wherein the plurality of the first type of bit lines comprises a first type first bit line and a first type second bit line, wherein the first type first bit line is located between the second type bit line and the first type second bit line in a second direction, the second direction intersecting the first direction; and at least one of the plurality of the first type second bit lines is connected to at least one of the plurality of the second type of bit lines.

5. The semiconductor device of claim 1, wherein the semiconductor device further comprises a second electronic switch connecting at least one of the plurality of the first type of bit lines to at least two of the plurality of the second type of bit lines. the plurality of the second type of bit lines comprises a plurality of second type first bit lines, wherein the plurality of second type first bit lines are equally spaced in a second direction, the second direction intersecting the first direction; and at least one of the plurality of the first type of bit lines is connected to at least one of the plurality of second type first bit lines.

6. The semiconductor device of claim 1, wherein, 7. The semiconductor device of claim 6, wherein the semiconductor device further comprises a third electronic switch connecting at least one of the plurality of the first type of bit lines to at least one of the plurality of second type first bit lines.

8. The semiconductor device of any one of claims 1-7, wherein ​ ​ ​ The transistor includes a vertical gate transistor including a semiconductor body extending along a third direction perpendicular to the storage plane region, wherein the semiconductor body includes two ends opposite in the third direction and at least one side surface between the two ends; the source and the drain are respectively disposed at the two ends; and a gate structure of the transistor is located at the at least one side surface.

9. A storage system, characterized by The storage system includes a controller and a semiconductor device as claimed in any one of claims 1-8, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data.

10. A method of making a semiconductor device immune to interference, comprising: The semiconductor device includes a substrate, word lines, and bit lines, wherein the substrate includes at least one storage plane region, the storage plane region includes a first region at an edge of the storage plane region and a second region different from the first region, the bit lines include first type bit lines and second type bit lines, the first type bit lines extend along a first direction parallel to the storage plane region in the first region, the second type bit lines extend along the first direction and pass through the first region and the second region, and a plurality of the word lines include first type word lines extending along a second direction intersecting the first direction in the first region, wherein the method includes: connecting at least one of the plurality of the first type bit lines with at least one of the plurality of the second type bit lines; connecting at least one of the plurality of the first type word lines with at least one of the plurality of the second type bit lines; and applying a first voltage signal to at least one of the plurality of the first type bit lines, wherein a value Vblfix of the first voltage signal satisfies: 0≤Vblfix≤Vdd.

11. The method of claim 10, wherein, The word lines extend along the second direction, and a plurality of the word lines further include second type word lines, wherein the second type word lines extend along the second direction and pass through the first region and the second region, and the method further includes: applying a second voltage signal to at least one of the plurality of the first type word lines, wherein a value Vwlfix of the second voltage signal satisfies: Vwlfix≤Vpt.

12. The method of claim 11, wherein, The plurality of the first type word lines include first type first word lines and first type second word lines, wherein the first type first word lines are located between the second type word lines and the first type second word lines in the first direction, and the method further includes: applying the second voltage signal to at least one of the plurality of the first type second word lines.

13. The method of claim 12, wherein, The method further includes: applying a third voltage signal different from the second voltage signal to at least one of the plurality of the first type first word lines, wherein a value Vwln of the third voltage signal satisfies: Vwln≤0.

14. The method of claim 13, wherein, the value Vwln of the third voltage signal and the value Vwlfix of the second voltage signal satisfy: Vwln≤Vwlfix.

15. The method of any one of claims 11-14, wherein, The semiconductor device further includes a first electronic switch connecting at least one of the plurality of the first type word lines with at least two of the plurality of the second type bit lines, wherein a bit line addressing signal is applied to the first electronic switch.

16. The method of claim 11, wherein, The plurality of first type bit lines includes a first type first bit line and a first type second bit line, wherein in a second direction intersecting the first direction, the first type first bit line is located between the second type bit line and the first type second bit line, and the method further comprises: applying the first voltage signal to at least one of the plurality of first type second bit lines.

17. The method of claim 16, wherein, The method further comprises: applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first type first bit lines.

18. The method of claim 17, wherein, The method further comprises: a fourth voltage signal value Vblp and the first voltage signal value Vblfix satisfy: Vblp≤Vblfix.

19. The method of any one of claims 11, 16-18, wherein, The semiconductor device further comprises a second electronic switch connecting at least one of the plurality of first type bit lines and at least two of the plurality of second type bit lines, wherein a bit line addressing signal is applied to the second electronic switch.

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