Memory and storage system

Abstract

The invention relates to the technical field of semiconductors, in particular to a memory and a memory system, and the memory comprises a memory array which comprises a plurality of memory units arranged in an array along a first direction and a second direction, and the first direction is different from the second direction; the driver is connected with a plurality of control lines extending in the first direction or connected with a plurality of control lines extending in the second direction, and each control line connects the multiple storage units in the same row or the multiple storage units in the same column with the driver; the storage array comprises at least two driving areas, a control line between each storage unit in each driving area and the driver has a control line length, and the control line lengths of different driving areas are different; and the voltage adjusting devices correspond to the driving areas, are electrically connected with at least one storage unit of the corresponding driving area, and are used for adjusting the driving voltage transmitted to the storage units. The memory provided by the invention is suitable for avoiding read errors of the memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory and a storage system. Background Art

[0002] Phase Change Memory (PCM) is limited by the resistance (Rs) of the peripheral circuit, and the threshold voltage (Vt) of different memory cells varies.

[0003] The resistance of the peripheral circuit affects the threshold voltage (Vt) of the memory cell through the distance between the memory cell and the driver; the threshold voltage of the memory cell that is farther away from the driver is higher, and the threshold voltage of the memory cell that is closer to the driver is lower.

[0004] During the data reading process, the memory usually reads data from all memory cells based on a fixed read voltage. Since threshold voltages of different memory cells are different, read errors may occur during the data reading process based on the fixed read voltage. Summary of the invention

[0005] The main purpose of the present application is to provide a memory and a storage system, which are suitable for different storage units to adjust the read voltage, thereby avoiding memory read errors.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application proposes a memory, comprising: a storage array, comprising a plurality of storage cells arranged in an array along a first direction and a second direction, the first direction and the second direction being different; a driver, connected to a plurality of control lines extending along the first direction, or connected to a plurality of control lines extending along the second direction, each control line connecting a plurality of storage cells in a row or a plurality of storage cells in a column to the driver; the storage array comprises at least two driving areas, the control line between each storage cell in each driving area and the driver has a control line length, and the control line lengths of different driving areas are different; a voltage regulating device corresponding to the driving area, the voltage regulating device being electrically connected to at least one storage cell of the corresponding driving area, for regulating a driving voltage transmitted to the storage cell.

[0007] In some embodiments, the memory further includes: a plurality of switching devices, wherein a first end of the switching device receives a power supply voltage, a second end of the switching device is electrically connected to the corresponding storage unit, and a control end of the switching device is connected to the voltage regulating device.

[0008] In some embodiments, the voltage regulating device includes: a driving capacitor, wherein the capacitance of the driving capacitor electrically connected to different driving areas is different; the first electrode plate of the driving capacitor is connected to the control end of the switching device, and the second electrode plate of the driving capacitor is used to input the control voltage.

[0009] In some embodiments, the driving capacitors electrically connected to the plurality of storage cells in the same driving region have the same capacitance.

[0010] In some embodiments, the voltage regulating device includes: a driving resistor, wherein the resistance of the driving resistor electrically connected to different driving regions is different; a first end of the driving resistor is connected to a control end of the switching device, and a second end of the driving resistor is used to input a control voltage.

[0011] In some embodiments, the driving resistors electrically connected to a plurality of storage units in the same driving region have the same resistance value.

[0012] In some embodiments, the voltage regulating device is disposed within the driver.

[0013] In some embodiments, the driver includes a word line driver and a bit line driver; the control line length is the length of the word line from the memory cell to the word line driver; or, the control line length is the length of the bit line from the memory cell to the bit line driver; or, the control line length is the sum of the length of the word line from each memory cell to the word line driver and the length of the bit line from the memory cell to the bit line driver.

[0014] In some embodiments, the storage array is multi-layered, and the multi-layer storage array is stacked and arranged along a third direction, the third direction is perpendicular to the first direction and the second direction, and when the driving area of ​​each layer of the storage array is projected onto the storage array of an adjacent layer along the third direction, the projection pattern of the driving area overlaps with the driving area of ​​the adjacent layer of the storage array; the parameters of the voltage regulating device electrically connected to the corresponding driving areas are different.

[0015] In a second aspect, the present application further proposes a storage system, comprising: the memory mentioned in the first aspect above; and a controller connected to the memory, for controlling the memory to store data.

[0016] The memory provided in the present application divides the memory array into different drive areas based on the difference in control line length between the memory cell and the driver, so that the memory cells in the same drive area have a similar threshold voltage, and then the read voltage of the memory cell is adjusted by the voltage adjustment device corresponding to the drive area, and the threshold voltage difference is offset by the compensation voltage difference of different drive areas, so as to ensure the accuracy of data reading of the entire memory array, thereby avoiding memory read errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of a structure of a first storage array divided into drive areas provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a structure of a second storage array divided into drive areas provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a structure of a third storage array divided into drive areas provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of the principle of providing a compensation voltage for a driving capacitor provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the connection structure of the driving capacitor provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the turn-on resistance corresponding to the memory array provided in the embodiment of the present application;

[0024] Figure 7 A turn-on resistance curve diagram corresponding to different memory array positions in the memory array provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of the structure of a storage system provided in an embodiment of the present application.

[0026] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] Based on the background technology, it is known that during the data reading process, the memory usually reads data from all memory cells based on a fixed read voltage. Since the threshold voltages of different memory cells are different, read errors may occur during the data reading process based on the fixed read voltage.

[0028] Due to the limitation of the chip peripheral circuit area, different read voltages cannot be provided by multiple voltage sources in memory circuit design.

[0029] An embodiment of the present application provides a memory, which is suitable for adjusting the read voltage of different memory cells, thereby avoiding read errors of the memory.

[0030] Specifically, the memory provided in this embodiment includes: a storage array, including a plurality of storage cells arranged in an array along a first direction and a second direction, the first direction and the second direction are different; a driver, connected to a plurality of control lines extending along the first direction, or connected to a plurality of control lines extending along the second direction, each control line connects a plurality of storage cells in a row or a plurality of storage cells in a column to the driver; the storage array includes at least two driving areas, the control line between each storage cell in each driving area and the driver has a control line length, and the control line lengths of different driving areas are different; a voltage regulating device corresponding to the driving area, the voltage regulating device is electrically connected to at least one storage cell in the corresponding driving area, and is used to adjust the driving voltage transmitted to the storage cell.

[0031] The memory provided in the embodiment of the present application divides the memory array into different drive areas based on the difference in control line length between the memory cell and the driver, so that the memory cells in the same drive area have a similar threshold voltage, and then the read voltage of the memory cell is adjusted by the voltage adjustment device corresponding to the drive area, and the threshold voltage difference is offset by the compensation voltage difference of different drive areas, so as to ensure the accuracy of data reading of the entire memory array, thereby avoiding memory read errors.

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0034] In some embodiments, reference Figure 1 , Figure 1 The first embodiment provides a schematic diagram of a structure of dividing a memory array into drive areas. The memory 100 includes a memory array 101, a driver and a voltage regulating device.

[0035] The memory array 101 includes a plurality of memory cells 200 arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y are different.

[0036] The driver is connected to a plurality of control lines extending along the first direction X, and each control line connects a plurality of memory cells 200 in a row to the driver.

[0037] exist Figure 1 In the example, the control line is a word line (WL) 301 , and the driver is a word line driver 310 ; the word line driver 310 is connected to a plurality of word lines 301 in a first direction X, and each word line 301 connects a plurality of memory cells 200 in the same row to the word line driver 310 .

[0038] The memory array 101 includes at least two drive regions, and the control line between each memory cell 200 and the driver in each drive region has a control line length, and the control line lengths of different drive regions are different. In this example, the control line length is the length of the word line 301 between the memory cell 200 and the word line driver 310.

[0039] For the effect of different control line lengths on threshold voltage, refer to Figure 6 and Figure 7 , Figure 6 A schematic diagram of the turn-on resistance corresponding to the memory array provided in this embodiment, Figure 7 This is a turn-on resistance curve diagram corresponding to different memory array positions in the memory array provided in this embodiment. Figure 6 and Figure 7The resistors Rs at different positions in the memory array 101 are illustrated. As the length of the word line WL increases, the value of the resistor Rs increases accordingly, which can be expressed as resistance Rs = line resistance × word line length. In other words, the farther the distance from the peripheral circuit, the greater the resistor Rs, that is, the greater the resistance of the peripheral circuit, and the greater the threshold voltage Vt of the corresponding memory cell.

[0040] exist Figure 1 In an example, the memory array 101 may be divided into a first driving region 110 and a second driving region 120 based on a bisection point of a word line length.

[0041] At this time, the threshold voltage Vt of the memory cells 200 in the first driving region 110 is considered to be V1 on average; the distance between the second driving region 120 and the word line driver 310 is greater than the distance between the first driving region 110 and the word line driver 310, and the threshold voltage Vt of the memory cells 200 in the second driving region 120 is considered to be V1+△V1 on average.

[0042] A plurality of voltage regulating devices are electrically connected to at least one storage unit in a corresponding driving region and are used to regulate a driving voltage transmitted to the storage unit.

[0043] Specifically, the compensation voltage provided by the voltage regulating device is used to compensate the read voltage of the storage unit; assuming that the first driving area 110 corresponds to the first voltage regulating device, the compensation voltage provided by the first voltage regulating device is V01; the second driving area 120 corresponds to the second voltage regulating device, and the compensation voltage provided by the second voltage regulating device is V02. At this time, the read voltage of the storage unit 200 in the first driving area 110 is Vread+V01 after compensation, and the threshold voltage is V1; the read voltage of the storage unit 200 in the second driving area 120 is Vread+V02 after compensation, and the threshold voltage is V1+△V1. When V02 approaches V01+△V1, the difference in the compensation voltage offsets the difference in the threshold voltage of the storage unit 200, avoiding the read error of the memory based on the same read voltage.

[0044] In some embodiments, reference Figure 2 , Figure 2 The second embodiment provides a schematic diagram of a structure of dividing a drive area into a storage array. The storage 100 includes a storage array 101, a driver and a voltage regulating device.

[0045] The memory array 101 includes a plurality of memory cells 200 arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y are different.

[0046] The driver is connected to a plurality of control lines extending along the second direction Y, and each control line connects a plurality of storage units in the same column to the driver.

[0047] exist Figure 2 In the example, the control line is a bit line (WL) 302 , and the driver is a bit line driver 320 ; the bit line driver 320 is connected to a plurality of bit lines 302 in the second direction Y, and each bit line 302 connects a plurality of memory cells 200 in the same column to the bit line driver 320 .

[0048] The memory array 101 includes at least two drive regions, and the control line between each memory cell 200 and the driver in each drive region has a control line length, and the control line lengths of different drive regions are different. In this example, the control line length is the length of the bit line 302 between the memory cell 200 and the bit line driver 320.

[0049] For the effect of different control line lengths on threshold voltage, refer to Figure 6 and Figure 7 . Figure 6 and Figure 7 The resistors Rs at different positions in the memory array 101 are illustrated. As the length of the bit line BL increases, the value of the resistor Rs increases accordingly, which can be expressed as resistance Rs = line resistance × bit line length. In other words, the farther the distance from the peripheral circuit, the greater the resistor Rs, that is, the greater the resistance of the peripheral circuit, and the greater the threshold voltage Vt of the corresponding memory cell.

[0050] exist Figure 2 In an example, the memory array 101 may be divided into a first driving region 110 and a second driving region 120 based on a bisection point of the bit line length.

[0051] At this time, the threshold voltage Vt of the storage unit 200 in the first driving area 110 is regarded as V2 on average; the distance between the second driving area 120 and the bit line driver 320 is greater than the distance between the first driving area 110 and the bit line driver 320, and the threshold voltage Vt of the storage unit 200 in the second driving area 120 is regarded as V2+△V2 on average.

[0052] A plurality of voltage regulating devices are electrically connected to at least one storage unit in a corresponding driving region and are used to regulate a driving voltage transmitted to the storage unit.

[0053] Specifically, the compensation voltage provided by the voltage regulating device is used to compensate the read voltage of the storage unit; assuming that the first driving area 110 corresponds to the first voltage regulating device, the compensation voltage provided by the first voltage regulating device is V03; the second driving area 120 corresponds to the second voltage regulating device, and the compensation voltage provided by the second voltage regulating device is V04. At this time, the read voltage of the storage unit 200 in the first driving area 110 is Vread+V03 after compensation, and the threshold voltage is V2; the read voltage of the storage unit 200 in the second driving area 120 is Vread+V04 after compensation, and the threshold voltage is V2+△V2. When V04 approaches V03+△V2, the difference in the compensation voltage offsets the difference in the threshold voltage of the storage unit 200, avoiding the read error of the memory based on the same read voltage.

[0054] In some embodiments, reference Figure 3 , Figure 3 The third embodiment provides a schematic diagram of a structure of dividing a drive area into a storage array. The storage 100 includes a storage array 101, a driver and a voltage regulating device.

[0055] The memory array 101 includes a plurality of memory cells 200 arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y are different.

[0056] The driver is connected to a plurality of control lines extending along the first direction X and the second direction Y. Each control line connects a plurality of storage units in a row to the driver, and each control line connects a plurality of storage units in a column to the driver.

[0057] exist Figure 3 In the example, the control lines include a word line 301 and a bit line 302, and the driver includes a word line driver 310 and a bit line driver 320; the word line driver 310 is connected to multiple word lines 301 in a first direction X, and each word line 301 connects multiple memory cells 200 in the same row to the word line driver 310; the bit line driver 320 is connected to multiple bit lines 302 in a second direction Y, and each bit line 302 connects multiple memory cells 200 in the same column to the bit line driver 320.

[0058] The memory array 101 includes at least two driving regions, and the control line between each memory cell 200 and the driver in each driving region has a control line length, and the control line lengths of different driving regions are different. In this example, the control line length is the sum of the length of the word line 301 between the memory cell 200 and the word line driver 310, and the length of the bit line 302 between the memory cell 200 and the bit line driver 320.

[0059] For the effect of different control line lengths on threshold voltage, refer to Figure 6 and Figure 7 . Figure 6 and Figure 7 The resistors Rs at different positions in the memory array 101 are illustrated. As the length of the word line WL increases, or as the length of the bit line BL increases, the value of the resistor Rs increases accordingly, which can be expressed as resistance Rs = line resistance × (word line length + bit line length). In other words, the farther the distance from the peripheral circuit, the greater the resistor Rs, that is, the greater the resistance of the peripheral circuit, and the greater the threshold voltage Vt of the corresponding memory cell.

[0060] exist Figure 3 In the example, the memory array 101 may be obliquely divided into a first driving region 110 , a second driving region 120 , and a third driving region 130 based on two trisection points of the sum of the word line length and the bit line length.

[0061] At this time, the threshold voltage Vt of the storage cell 200 in the first driving area 110 is considered to be V3 on average; the sum of the distances between the second driving area 120 and the word line driver 310 and the bit line driver 320 is greater than the sum of the distances between the first driving area 110 and the word line driver 310 and the bit line driver 320, and the threshold voltage Vt of the storage cell 200 in the second driving area 120 is considered to be V3+△V3 on average; the sum of the distances between the third driving area 130 and the word line driver 310 and the bit line driver 320 is greater than the sum of the distances between the second driving area 120 and the word line driver 310 and the bit line driver 320, and the threshold voltage Vt of the storage cell 200 in the third driving area 130 is considered to be V3+2△V3 on average.

[0062] In some embodiments, the control line length may also be the sum of K1 times the length of the word line 301 from each storage cell 200 to the word line driver 310 and K2 times the length of the bit line 302 from the storage cell 200 to the bit line driver 320, wherein K1 and K2 are not equal; it should be noted that this embodiment does not constitute a numerical limitation on K1 and K2, and can be flexibly set according to application scenarios, actual needs, resistance relationships between word lines and bit lines, etc.

[0063] A plurality of voltage regulating devices are electrically connected to at least one storage unit in a corresponding driving region and are used to regulate a driving voltage transmitted to the storage unit.

[0064] Specifically, the compensation voltage provided by the voltage regulating device is used to compensate the read voltage of the storage unit; assuming that the first driving area 110 corresponds to the first voltage regulating device, the compensation voltage provided by the first voltage regulating device is V05; the second driving area 120 corresponds to the second voltage regulating device, the compensation voltage provided by the second voltage regulating device is V06; the third driving area 130 corresponds to the third voltage regulating device, and the compensation voltage provided by the third voltage regulating device is V07. At this time, the read voltage of the storage unit 200 in the first driving area 110 is Vread+V05 after compensation, and the threshold voltage is V3; the read voltage of the storage unit 200 in the second driving area 120 is Vread+V06 after compensation, and the threshold voltage is V3+△V3; the read voltage of the storage unit 200 in the third driving area 130 is Vread+V07 after compensation, and the threshold voltage is V3+2△V3. When V06 approaches V05+ΔV3 and V07 approaches V06+ΔV3, the compensation voltage offsets the threshold voltage difference of the memory cell 200, thereby avoiding the read error of the memory based on the same read voltage.

[0065] It should be noted that in Figure 1 to Figure 3 In the example, the first direction X and the second direction Y are perpendicular to each other, which is only used to illustrate the first direction X and the second direction Y, and does not limit the present embodiment. In a specific application, the first direction X and the second direction Y may have a certain angle.

[0066] It should be noted that in Figure 1 to Figure 3 In the example, the number of driving areas obtained by dividing the storage array 101 is only for illustrative purposes and does not constitute a limitation on this embodiment. In specific applications, more driving areas may be divided into multiple control line length ranges according to compensation accuracy.

[0067] In some embodiments, the voltage regulating device includes a driving capacitor, and the driving capacitors electrically connected to different driving regions have different capacitances.

[0068] Specifically, as an energy storage device, the capacitor can provide an additional compensation voltage to increase the read voltage received by the storage unit 200. Based on the principle of capacitor energy storage, it can be seen that the larger the capacitance of the driving capacitor, the larger the compensation voltage provided; the smaller the capacitance of the driving capacitor, the smaller the compensation voltage provided. Based on the foregoing, it can be seen that the threshold voltage of the storage unit in the driving area with a larger control line length is larger, that is, the driving area with a larger control line length corresponds to a larger capacitance of the driving capacitor, and the driving area with a smaller control line length corresponds to a smaller capacitance of the driving capacitor.

[0069] In some embodiments, the voltage regulating device includes a driving resistor, and the driving resistors electrically connected to different driving regions have different resistance values.

[0070] Specifically, the resistor, as a voltage divider device, can reduce the read voltage received by the memory cell 200 by dividing the read voltage into a compensation voltage. Based on the voltage division principle of the resistor, it can be seen that the larger the resistance of the driving resistor, the larger the compensation voltage of the voltage division; the smaller the capacitance of the driving capacitor, the smaller the compensation voltage of the voltage division. Based on the foregoing, it can be seen that the threshold voltage of the memory cell in the driving area with a larger control line length is larger, that is, the driving area with a larger control line length corresponds to a smaller resistance value of the driving resistor, and the driving area with a smaller control line length corresponds to a larger resistance value of the driving resistor.

[0071] In some embodiments, the memory 100 further includes a plurality of switch devices, wherein a first end of the switch device receives a power supply voltage, a second end of the switch device is electrically connected to a corresponding storage unit, and a control end of the switch device is connected to a voltage regulating device.

[0072] In some embodiments, reference Figure 4 , Figure 4 The schematic diagram of the principle of providing a compensation voltage for the driving capacitor provided in this embodiment, the first electrode plate of the driving capacitor Cboost is connected to the control terminal of the switching device S1, and the second electrode plate of the driving capacitor Cboost is used to input the control voltage. Specifically, the driving capacitor Cboost adjusts the driving voltage transmitted to the storage unit based on the input control voltage and the compensation voltage.

[0073] In some embodiments, a first end of the driving resistor is connected to a control end of the switch device S1, and a second end of the driving resistor is used to input a control voltage. Specifically, the driving resistor adjusts the driving voltage transmitted to the memory cell based on the input control voltage and the compensation voltage.

[0074] Specifically, the first terminal of the switch device S1 receives the power supply voltage, that is, Figure 4 The input voltage Vin shown, the second end of the switch device S1 is connected to the corresponding storage unit; when the switch device S1 is turned on, the first end and the second end of the switch device S1 are connected, and the switch device S1 provides an output voltage Vout to the corresponding storage unit. The driving voltage received by the control end of the switch device S1 is the gate voltage VG of the switch device S1. The gate of the switch device S1 can be regarded as a capacitor Cgate. When the control end of the switch device S1 is connected to the driving capacitor Cboost, it can be regarded as the capacitor Cgate and the driving capacitor Cboost are connected in series. The capacitors are connected in series, and the overall capacitance is reduced. It can be regarded as the capacitance of the gate capacitance of the switch device S1 is reduced, thereby reducing the threshold voltage of the switch device, and realizing the compensation of the threshold voltage difference of different storage cells in the storage array 101.

[0075] In some embodiments, reference Figure 5 , Figure 5A schematic diagram of the connection structure of the driving capacitor provided in this embodiment, wherein a switch device is connected to one side of the driving capacitor (voltage regulating device), and a boost circuit connected to the other side of the driving capacitor (voltage regulating device) is a circuit to which the gate of the switching device is originally connected. The switching device is a transistor connecting the voltage word line (VWL) and the global word line (GWL) to change the voltage provided by the voltage source VPRH to the global word line GWL, thereby affecting the potential on the voltage word line VWL and the global word line GWL; the global word line GWL is connected to the main word line (MWL) through the switch tube to change the potential on the main word line MWL; the main word line MWL is connected to the word line WL through the switch tube to change the potential on the word line WL, thereby changing the potential difference between the word line WL and the bit line BL to adjust the data reading of the memory cell.

[0076] In some embodiments, the voltage regulator device is provided within the driver.

[0077] The driver is a peripheral circuit of the memory 100. The voltage regulating device is formed by existing capacitors or resistors in the peripheral circuit of the memory 100. Threshold voltage compensation is achieved based on the original peripheral devices of the memory 100 without introducing new devices and affecting the area of ​​the memory.

[0078] In some embodiments, each memory cell in the memory array 101 is electrically connected to a driving capacitor with a different capacitance.

[0079] By providing a corresponding driving capacitor for each memory cell 200 , it is possible to ensure that the threshold voltage difference of each memory cell 200 in the memory array 101 is accurately compensated, further ensuring the accuracy of data reading of the entire memory array, thereby avoiding memory read errors.

[0080] In some embodiments, the capacitance of the driving capacitor electrically connected to multiple memory cells in the same driving region is the same. For example, multiple memory cells 200 in each driving region are electrically connected to the same driving capacitor, thereby ensuring that the capacitance of the driving capacitor electrically connected to the memory cells 200 is the same.

[0081] In some embodiments, the capacitance of the driving capacitors electrically connected to the multiple storage cells in each driving region is different. Each driving region performs voltage adjustment through driving capacitors with different capacitances to further improve the accuracy of threshold voltage compensation during compensation. In addition, each driving region includes driving capacitors with different capacitances, which can also be regarded as including multiple sub-regions in the driving region, and the capacitance of the driving capacitors in each sub-region is the same. For multiple sub-regions, it can be regarded that the storage array 101 is divided into more driving regions.

[0082] In some embodiments, each memory cell in the memory array 101 is electrically connected to a driving resistor with a different resistance value.

[0083] By providing a corresponding driving resistor for each memory cell 200 , it is possible to ensure that the threshold voltage difference of each memory cell 200 in the memory array 101 is accurately compensated, further ensuring the accuracy of data reading of the entire memory array, thereby avoiding memory read errors.

[0084] In some embodiments, the driving resistors electrically connected to multiple memory cells in the same driving region have the same resistance value. For example, multiple memory cells 200 in each driving region are electrically connected to the same driving resistor, thereby ensuring that the driving resistors electrically connected to the memory cells 200 have the same resistance value.

[0085] In some embodiments, the resistance values ​​of the driving resistors electrically connected to the multiple storage cells in each driving region are different. Each driving region performs voltage adjustment through driving resistors with different resistance values ​​to further improve the accuracy of threshold voltage compensation during compensation. In addition, each driving region includes driving resistors with different resistance values, which can also be regarded as including multiple sub-regions in the driving region, and the resistance value of the driving resistor in each sub-region is the same. For multiple sub-regions, it can be regarded that the memory array 101 is divided into more driving regions.

[0086] In some embodiments, the storage array is multi-layered, and the multi-layer storage array is stacked and arranged along a third direction, the third direction is perpendicular to the first direction and the second direction, and when the drive area of ​​each layer of the storage array is projected onto the storage array of the adjacent layer along the third direction, the projection pattern of the drive area overlaps with the drive area of ​​the adjacent layer of the storage array.

[0087] Specifically, for a multi-layer storage array, the drive area division method of one layer of the storage array can refer to the above Figure 1 to Figure 3 For example, for storage arrays in other layers, area division is performed based on the area division boundary line of the storage array in which the drive area has been divided, that is, the area division method of the multi-layer storage array is the same.

[0088] In some embodiments, the parameters of the voltage regulating devices electrically connected to the corresponding driving regions in different layers of storage arrays are the same. In one example, if the capacitance of the driving capacitor connected to the first driving region of the first layer of storage array is c, then the capacitance of the driving capacitor connected to the first driving region of the second layer of storage array is also c.

[0089] In some embodiments, corresponding driving regions in different layers of memory arrays are electrically connected to the same voltage regulating device, that is, the same driving regions in different layers of memory arrays are connected to the same driving capacitor or driving resistor, so as to compensate for the difference in threshold voltages of memory cells in different layers of memory arrays based on limited peripheral devices.

[0090] In some embodiments, in different layers of storage arrays, the parameters of the voltage regulating devices electrically connected to the corresponding driving areas are different, so that the corresponding voltage regulating devices are adaptively set according to the threshold voltage differences of the storage cells in different layers of storage arrays, thereby further ensuring the accuracy of data reading of the entire storage array.

[0091] In some embodiments, for a multi-layer storage array, the drive area division method of each layer of the storage array can refer to the above Figure 1 to Figure 3 For example, for a multi-layer storage array, the driving area division method of each layer of the storage array is different, and the parameters of the corresponding electrically connected voltage regulating devices may also be different.

[0092] In some embodiments, a multi-layer storage array includes any layer storage array with a driving region division method, and also includes any layer storage array with a driving region division method that is different.

[0093] The memory provided in the present application divides the memory array into different drive areas based on the difference in control line length between the memory cell and the driver, so that the memory cells in the same drive area have a similar threshold voltage, and then the read voltage of the memory cell is adjusted by the voltage adjustment device corresponding to the drive area, and the threshold voltage difference is offset by the compensation voltage difference of different drive areas, so as to ensure the accuracy of data reading of the entire memory array, thereby avoiding memory read errors.

[0094] It should be noted that, in the absence of conflict, the features disclosed in the memory provided in the above embodiments can be randomly combined to obtain a new memory embodiment.

[0095] Another embodiment of the present application provides a storage system, which is suitable for adjusting the read voltage of different storage units, so as to avoid memory read errors.

[0096] refer to Figure 8 , Figure 8 The schematic diagram of the structure of the storage system provided in this embodiment. The storage system 800 includes a memory 801 and a controller 802. The memory 801 may be the memory 100 mentioned in any of the above embodiments. The controller 802 is connected to the memory 801 and is used to control the memory 801 to store data. The memory 801 may perform the operation of storing data based on the control of the controller 802.

[0097] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0098] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0099] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0100] The above is a detailed introduction to a memory and storage system provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, it can be seen that the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory, characterized in that: include: A storage array, comprising a plurality of storage units arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are different; A driver connected to a plurality of control lines extending along the first direction or connected to a plurality of control lines extending along the second direction, each control line connecting a plurality of storage units in a row or a plurality of storage units in a column to the driver; The storage array comprises at least two driving regions, the control line between each storage unit in each driving region and the driver has a control line length, and the control line lengths of different driving regions are different; A voltage regulating device corresponding to the driving region, wherein the voltage regulating device is electrically connected to at least one storage unit of the corresponding driving region and is used to regulate a driving voltage transmitted to the storage unit.

2. The memory according to claim 1, wherein: Also includes: A plurality of switch devices, wherein a first end of the switch device receives a power supply voltage, a second end of the switch device is electrically connected to the corresponding storage unit, and a control end of the switch device is connected to the voltage regulating device.

3. The memory according to claim 2, wherein: The voltage regulating device comprises: a driving capacitor, wherein the driving capacitors electrically connected to different driving regions have different capacitance values; The first electrode plate of the driving capacitor is connected to the control end of the switching device, and the second electrode plate of the driving capacitor is used for inputting a control voltage.

4. The memory according to claim 3, wherein: The driving capacitors electrically connected to a plurality of storage units in the same driving region have the same capacitance.

5. The memory according to claim 2, wherein: The voltage regulating device comprises: a driving resistor, wherein the driving resistor electrically connected to different driving regions has different resistance values; The first end of the driving resistor is connected to the control end of the switch device, and the second end of the driving resistor is used to input a control voltage.

6. The memory according to claim 5, characterized in that The driving resistors electrically connected to a plurality of storage units in the same driving region have the same resistance value.

7. The memory according to claim 1, wherein: The voltage regulating device is arranged in the driver.

8. The memory according to any one of claims 1 to 7, characterized in that: The driver includes a word line driver and a bit line driver; The control line length is the length of the word line between the storage unit and the word line driver; or, The control line length is the length of the bit line between the memory cell and the bit line driver; or, The control line length is the sum of the length of the word line between each memory cell and the word line driver and the length of the bit line between the memory cell and the bit line driver.

9. The memory according to claim 1, wherein: The storage array is multi-layered, and the multi-layer storage array is stacked and arranged along a third direction, the third direction is perpendicular to the first direction and the second direction, and when the drive area of ​​each layer of the storage array is projected onto the storage array of an adjacent layer along the third direction, the projection pattern of the drive area overlaps with the drive area of ​​the storage array of the adjacent layer; The parameters of the voltage regulating devices electrically connected to the corresponding driving regions are different.

10. A storage system, characterized in that: include: The memory according to any one of claims 1 to 9; A controller is connected to the memory and is used to control the memory to store data.

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