Nonvolatile memory, sensitive amplification circuit thereof and electronic equipment
By providing the second amplification module and the inverter unit within the sensitive amplification circuit of the nonvolatile memory, the precharge signal is provided with internal control, which solves the problem of limited memory read speed and achieves a faster data read speed.
Patent Information
- Application Number
- CN202311401394.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-25
- Publication Date
- 2025-04-25
Smart Images
Figure CN119889396A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to a non-volatile memory and a sensitive amplifier circuit and electronic equipment thereof. Background Art
[0002] During the memory read operation, the pre-charge operation generally has the greatest impact on the read speed. The reason is that the parasitic capacitance CL of the bit line (BL) path of the memory array is relatively large (hundreds or even thousands of CELL drain capacitance and BL line capacitance, the capacitance can reach several pF). It takes a lot of electricity to pre-charge the bit line (BL) to the preset voltage; however, simply increasing the voltage VCLAMP during the pre-charge stage cannot guarantee fast pre-charge, because the reference current providing module can only provide limited current (its current value is between the erase and programming current of the CELL), and cannot provide sufficient drive for the amplifier. To solve this problem, a pre-charge signal is introduced, which controls the pre-charge current providing module, and the external controller divides the read cycle into two parts:
[0003] 1) Precharge phase, during which PREC is at a low level, and the precharge current supply module is controlled to provide sufficient drive current for the precharge phase to precharge the bit line (BL) to the required voltage. During this phase, regardless of the current of the CELL, the voltage of the VSPA node is always at a higher level (close to VCC);
[0004] 2) Amplification stage. In this stage, PREC becomes high, controlling the pre-charge current providing module to stop providing driving current. The reference current provided by the reference current providing module and the CELL current flowing through the amplifier tube will determine the voltage of the VSPA node, thereby determining the output.
[0005] The shortcoming is that, in order to prevent read data errors caused by incomplete pre-charging, the control logic generally gives a pre-charging signal as wide as possible to ensure that any individual sensitive amplifier circuit operates on any bit line (BL), and the bit line (BL) can be fully pre-charged in the entire operating voltage, temperature range and possible process drift. As a result, in many cases, the width of the pre-charging signal is greater than that required by the sensitive amplifier circuit, which limits the further reduction of the read cycle and thus limits the improvement of the read speed. Summary of the invention
[0006] The present application provides a non-volatile memory and a sensitive amplifier circuit and an electronic device thereof, which do not require an external controller to provide a pre-charge signal, thereby reducing the requirements for the controller and also reducing the interface signal scale between the controller and the sensitive amplifier circuit.
[0007] In a first aspect, the present application provides a sensitive amplifier circuit suitable for a non-volatile memory, the sensitive amplifier circuit comprising: a reference current providing module, used to provide a reference current; a pre-charge current providing module, used to provide a charging current for a bit line in a pre-charge stage, the bit line being used to couple a storage unit; an amplifier tube, a first end of the amplifier tube being coupled to the bit line, a second end of the amplifier tube being used to couple an output end of the pre-charge current providing module and an output end of the reference current providing module; a first amplifier module, a first end of the first amplifier module being coupled to a control end of the amplifier tube, a second end of the first amplifier module being coupled to a first end of the amplifier tube; A second amplifying module, wherein the first end of the second amplifying module is coupled to the first end of the amplifying tube; an inverting unit, wherein the input end of the inverting unit is coupled to the second end of the second amplifying module, and the output end of the inverting unit is coupled to the control end of the pre-charge current providing module; a comparing module, wherein the input end of the comparing module is coupled to the second end of the amplifying tube; wherein the second amplifying module is used to output a first voltage to the inverting unit when the bit line voltage is lower than a preset voltage, and the inverting unit is used to invert the first voltage to obtain a second voltage, and output it to the control end of the pre-charge current providing module, and the pre-charge current providing module enters the pre-charge stage to provide a charging current for the bit line.
[0008] Among them, the first amplification module includes: a first transistor, a first end of the first transistor is coupled to the power supply voltage end; a second transistor, a first end of the second transistor is coupled to the second end of the first switch tube, and the second end of the second transistor is grounded; the coupling point between the second transistor and the first transistor is coupled to the control end of the amplifier tube; wherein, in response to a read command, the first transistor tube is turned on, and a third voltage is provided to the control end of the amplifier tube to turn on the amplifier tube, and the pre-charge current providing module enters the pre-charge stage to perform a pre-charge operation on the bit line.
[0009] The first transistor is a Pmos transistor, and the second transistor is a Nmos transistor.
[0010] Wherein, the second amplification module includes: a third transistor, a first end of the third transistor is coupled to the power supply voltage end; a fourth transistor, a first end of the fourth transistor is coupled to the second end of the third transistor, and the second end of the fourth transistor is grounded; the control end of the fourth transistor is coupled to the bit line, and the coupling point between the third transistor and the fourth transistor is coupled to the input end of the inverting unit; wherein, in response to a read command, the fourth transistor is turned off, the third transistor is turned on, and the first voltage is provided to the inverting unit.
[0011] The third transistor is a Pmos transistor, and the fourth transistor is a Nmos transistor.
[0012] In which, in response to the bit line voltage being pre-charged to the target voltage, the fourth transistor MN3 is turned on, providing a third voltage to the inverting unit, the inverting unit is used to invert the third voltage to obtain a fourth voltage, and output it to the control end of the pre-charge current providing module, and the pre-charge current providing module stops providing charging current to the bit line.
[0013] The bias current of the fourth transistor is smaller than the bias current of the second transistor.
[0014] Wherein, the first amplification module is a first amplifier, the output end of the first amplifier is coupled to the control end of the amplifier tube, the inverting input end of the first amplifier is coupled to the first end of the amplifier tube, and the non-inverting input end of the first amplifier is coupled to the reference voltage end; the second amplification module is a second amplifier, the output end of the second amplifier is coupled to the inverting unit, the inverting input end of the second amplifier is coupled to the first end of the amplifier tube, and the non-inverting input end of the second amplifier is coupled to the reference voltage end; wherein, the reference voltage corresponding to the second amplifier is less than the reference voltage corresponding to the first amplifier.
[0015] In a second aspect, the present application provides a non-volatile memory, which includes the sensitive amplifier circuit provided in the first aspect.
[0016] In a third aspect, the present application provides an electronic device, comprising the non-volatile memory provided in the second aspect.
[0017] The beneficial effect of the present application is as follows: Different from the prior art, the non-volatile memory and its sensitive amplifier circuit and electronic device provided by the present application are provided with a second amplifier module and an inverting unit inside the sensitive amplifier circuit, and the second amplifier module and the inverting unit are used to provide a precharge signal for controlling the precharge current providing module, so that the precharge current providing module enters the precharge stage to provide a charging current for the bit line, and no external controller is required to provide a precharge signal, which reduces the requirements for the controller and also reduces the interface signal scale between the controller and the sensitive amplifier circuit. Furthermore, since no external controller is required to provide a precharge signal, it is not necessary to strictly read data according to the signal width of the precharge signal provided by the external controller, and the precharge signal can be turned on and off according to the actual situation inside the sensitive amplifier circuit, which can shorten the data reading cycle and thus improve the data reading speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:
[0019] Figure 1 It is a structural schematic diagram of an embodiment of a sensitive amplifier circuit provided by the present application;
[0020] Figure 2 is a structural schematic diagram of another embodiment of the sensitive amplifier circuit provided by the present application;
[0021] Figure 3 is a structural schematic diagram of another embodiment of the sensitive amplifier circuit provided by the present application;
[0022] Figure 4 This application provides Figure 2 or Figure 3 Schematic diagram of simulation effect of sensitive amplifier circuit;
[0023] Figure 5 This application provides Figure 1 Schematic diagram of simulation effect of sensitive amplifier circuit;
[0024] Figure 6 is a structural schematic diagram of an embodiment of a non-volatile memory provided by the present application;
[0025] Figure 7 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.
[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0028] See also Figure 1 , Figure 1 The sensitive amplifier circuit 100 of the present application is a schematic diagram of a structure of an embodiment of a sensitive amplifier circuit applicable to a non-volatile memory. The sensitive amplifier circuit 100 comprises: a reference current providing module 10, a pre-charge current providing module 20, an amplifier tube MN1, a first amplifier module 30 and a comparison module 40.
[0029] Specifically, the sense amplifier is a common module in non-volatile memory (NVM) for reading data stored in a memory cell (CELL), and is mainly composed of the following parts:
[0030] The amplifier tube MN1 is an NMOS tube with a common gate structure, and its source end is connected to the bit line (BL) of the storage array as the input end of the amplifier MN1.
[0031] The reference current providing module 10 provides a reference current. After the bit line (BL) is precharged and the voltage is stable, the reference current is compared with the bit line current (CELL current) on the bit line (BL) to determine the voltage input to the comparison module 40. That is, the voltage of the VSPA node. The magnitude of the reference current is generally set between the erase current and the programming current of the memory cell. If the memory cell is in the erase state, its current is greater than the reference current, and the VSPA node is a lower voltage (close to the BL voltage). If the memory cell is in the programming state, its current is less than the reference current, and the VSPA node is a higher voltage (close to the power supply voltage VCC). The reference current providing module 10 can be composed of a transistor MP1, wherein the first end of the transistor MP1 is coupled to the power supply voltage end VCC, and the second end of the transistor MP1 is coupled to the drain end of the amplifier MN1. The control end of the transistor MP1 is turned on under the control of the control signal PREC_BIAS to provide a reference current.
[0032] The pre-charge current providing module 20 provides a current for charging the bit line (BL) in the pre-charge phase. The pre-charge current providing module 20 can be composed of a pre-charge tube MP4, wherein the first end of the pre-charge tube MP4 is coupled to the power supply voltage terminal VCC, and the second end of the pre-charge tube MP4 is coupled to the drain terminal of the amplifier tube MN1. The control end of the pre-charge tube MP4 is turned on under the control of the pre-charge signal PREC to provide a pre-charge current. The pre-charge signal PREC is provided by an external controller.
[0033] The first amplifier module 30 is a single-stage amplifier with inverting amplification, comprising a first transistor MP2 and a second transistor MN2. The first transistor MP2 is used as a current mirror to provide a bias current. The first amplifier module 30 has two functions. The first is to form a negative feedback structure with the amplifier tube MN1 to reduce the input impedance of the sensitive amplifier circuit 100, thereby reducing the change of the bit line voltage (BL voltage) under different CELL (memory cell) currents. The second is that compared with the solution of fixing the gate bias voltage of the amplifier tube MN1, the inverting amplification characteristics of the first amplifier module 30 can be used in the pre-charging stage to provide a higher gate voltage for the amplifier tube MN1, thereby accelerating the pre-charging.
[0034] The comparison module 40 is used to compare the voltage of the VSPA node with the reference voltage VREF and output the final signal SA_OUT. The reference voltage VREF is set between the voltages corresponding to the erase state and the programming state of the CELL to ensure that the data stored in the CELL can be correctly distinguished.
[0035] The working process of the sensitive amplifier circuit 100 is as follows:
[0036] 1) The bit line (BL) to be read is discharged to the ground level, the word line (WL) of the CELL is applied with a suitable bias voltage to obtain a suitable CELL current, the column selection signal YSEL is valid, and the column selection switch MSW is turned on, so that the input end of the sensitive amplifier circuit 100 is connected to the CELL to be read.
[0037] 2) Enable the sensitive amplifier circuit 100. Since there is generally a large parasitic capacitance on the bit line (BL) path, the capacitance is discharged in the above step 1), so the initial level of the input terminal of the sensitive amplifier circuit 100 is 0.
[0038] 3) Due to the inverting amplification characteristic of the first amplifying module 30, the voltage VCLAMP increases, the amplifying tube MN1 is turned on to charge the bit line (BL), and the voltage of the bit line (BL) increases. This process is the pre-charging operation.
[0039] 4) When the voltage of the bit line (BL) reaches the threshold voltage of the second transistor MN2, the second transistor MN2 is turned on, and the voltage VCLAMP begins to drop. The voltage VCLAMP and the stable voltage of the bit line (BL) are determined by the characteristics of the first amplifier module 30, the amplifier MN1, and the current of the CELL;
[0040] 5) After the bit line (BL) is charged, the current flowing through the amplifier MN1 is determined by the CELL current and compared with the reference current provided by the reference current providing module 10, thereby determining the voltage of the VSPA node, and then outputting the final signal SA_OUT through the comparison module 40, which reflects the data stored in the CELL.
[0041] In the above process, the pre-charge operation generally has the greatest impact on the readout speed. The reason is that the parasitic capacitance CL of the bit line (BL) path of the memory array is relatively large (hundreds or even thousands of CELL drain capacitance and BL line capacitance, the capacitance can reach several pF), and it is necessary to provide a large amount of electricity to pre-charge the bit line (BL) to the preset voltage; however, simply increasing the voltage VCLAMP in the pre-charge stage cannot guarantee fast pre-charge, because the reference current providing module 10 can only provide a limited current (its current value is between the erase and programming currents of the CELL), and cannot provide sufficient drive for the amplifier MN1. To solve this problem, a pre-charge signal PREC is introduced, which controls the pre-charge current providing module 20, and the external controller divides the readout cycle into two parts:
[0042] 1) Precharge stage. In this stage, the precharge signal PREC is at a low level, and the precharge current providing module 20 is controlled to provide sufficient driving current for the precharge stage to precharge the bit line (BL) to the required voltage. In this stage, regardless of the current size of the CELL, the voltage of the VSPA node is always at a higher level (close to VCC).
[0043] 2) Amplification stage, in this stage the pre-charge signal PREC becomes high, controlling the pre-charge current providing module 20 to stop providing the driving current, and the reference current provided by the reference current providing module 10 and the CELL current flowing through the amplifier MN1 will determine the voltage of the VSPA node, thereby determining the output.
[0044] The disadvantage is that the pre-charging time of the sensitive amplifier circuit 100 for the bit line (BL) is related to multiple factors, such as power supply voltage, ambient temperature, parasitic capacitance of the bit line (BL), and process parameters of the MOS tube, and the external control logic is often unable to obtain this information, especially factors related to process parameters, which will cause different sensitive amplifier circuits 100 in the same chip to operate on different bit lines (BL), and the pre-charging time will also be different, so the optimal pre-charging time is difficult to determine. In order to prevent read data errors caused by incomplete pre-charging, the control logic generally gives a pre-charging signal PREC as wide as possible to ensure that any sensitive amplifier circuit 100 operates on any bit line (BL), and the bit line (BL) can be fully pre-charged in the entire operating voltage, temperature range, and possible process drift. As a result, in many cases, the width of the pre-charging signal is greater than that required by the sensitive amplifier circuit, which limits the further reduction of the read cycle, thereby limiting the increase in the read speed.
[0045] In addition, the pre-charge signal PREC increases the interface signal between the external controller and the sensitive amplifier circuit 100, and the timing of the interface signal needs to be precisely controlled. Especially for high-speed applications, the existence of the pre-charge signal PREC increases the requirements for the controller.
[0046] Based on this, the present application proposes to add an auxiliary amplifier module, whose output signal is inverted by an inverting unit and then transmitted to the pre-charge current providing module 20, which is used as a pre-charge signal to control the pre-charge current providing module 20 to perform a pre-charge operation, without the need for an external controller to control. This auxiliary amplifier module can ensure that the level signal output in the initial stage of pre-charge is high, and outputs a low level after the inverting unit to control the pre-charge current providing module 20 to output the pre-charge current, without the need for an external controller to provide a pre-charge signal, thereby reducing the requirements for the controller and the scale of the interface signal between the controller and the sensitive amplifier circuit. Please refer to any of the following embodiments for details.
[0047] See also Figure 2 , Figure 2The sensitive amplifier circuit 100 is a schematic diagram of an embodiment of a sensitive amplifier circuit for non-volatile memory provided by the present application. The sensitive amplifier circuit 100 includes: a reference current providing module 10, a pre-charge current providing module 20, an amplifier tube MN1, a first amplifier module 30, a second amplifier module 50, a comparison module 40 and an inverting unit 60.
[0048] The reference current providing module 10 is used to provide a reference current.
[0049] The pre-charge current providing module 20 is used to provide a charging current for a bit line in a pre-charge phase, and the bit line is used to couple a memory cell.
[0050] A first end of the amplifier MN1 is coupled to the bit line (BL), and a second end of the amplifier MN1 is used to couple an output end of the pre-charge current providing module 20 and an output end of the reference current providing module 10 .
[0051] A first end of the first amplifying module 30 is coupled to the control end of the amplifying tube MN1 , and a second end of the first amplifying module 30 is coupled to the first end of the amplifying tube MN1 .
[0052] A first end of the second amplifying module 50 is coupled to a first end of the amplifying tube MN1 .
[0053] An input terminal of the inverting unit 60 is coupled to the second terminal of the second amplifying module 50 , and an output terminal of the inverting unit 60 is coupled to the control terminal of the pre-charge current providing module 20 .
[0054] The input terminal of the comparison module 40 is coupled to the second terminal of the amplifier MN1 .
[0055] The second amplifier module 50 is used to output a first voltage to the inverting unit 60 when the bit line voltage is lower than a preset voltage. The inverting unit 60 is used to invert the first voltage to obtain a second voltage and output it to the control end of the pre-charge current providing module 20. The pre-charge current providing module 20 enters the pre-charge stage to provide a charging current for the bit line (BL). The preset voltage is greater than 0V.
[0056] Based on this, the second amplifier module 50 can ensure that the level signal output in the initial stage of pre-charging is high, and output a low-level inverted signal PREC_CTRL after the inverting unit 60 to control the pre-charging current providing module 20 to output the pre-charging current, without the need for an external controller to provide a pre-charging signal, which reduces the requirements for the controller and also reduces the interface signal scale between the controller and the sensitive amplifier circuit. In addition, there is no need for an external controller to provide a pre-charging signal, and the internal architecture of the sensitive amplifier circuit 100 can be used to provide an inverted signal PREC_CTRL to control the pre-charging current providing module 20, which can reduce the read cycle and thus improve the read speed.
[0057] Further, the first amplifying module 30 includes a first transistor MP2 and a second transistor MN2.
[0058] The first terminal of the first transistor MP2 is coupled to the power voltage terminal VCC.
[0059] The first end of the second transistor MN2 is coupled to the second end of the first transistor MP2 , and the second end of the second transistor MN2 is grounded; the coupling point between the second transistor MN2 and the first transistor MP2 is coupled to the control end of the amplifier MN1 .
[0060] In response to the read command, the first transistor MP2 is turned on under the control signal VBP, providing a third voltage to the control terminal of the amplifier MN1, turning on the amplifier MN1, and the pre-charge current providing module 20 enters the pre-charge phase to perform a pre-charge operation on the bit line.
[0061] Specifically, the bit line (BL) to be read is discharged to the ground level, the word line (WL) of the CELL is applied with a suitable bias voltage to obtain a suitable CELL current, the column selection signal YSEL is valid, and the column selection switch MSW is turned on, so that the input end of the sensitive amplifier circuit 100 is connected to the CELL to be read. The first transistor MP2 is turned on under the control signal VBP, and the third voltage is provided to the control end of the amplifier MN1, so that the amplifier MN1 is turned on, and the pre-charge current providing module 20 enters the pre-charge stage according to the control signal provided by the inverting unit 60 to perform a pre-charge operation for the bit line through the amplifier MN1.
[0062] The first transistor MP2 is a Pmos transistor, and the second transistor MN2 is a Nmos transistor.
[0063] Further, the second amplifying module 50 includes a third transistor MP3 and a fourth transistor MN3.
[0064] The first terminal of the third transistor MP3 is coupled to the power voltage terminal VCC.
[0065] A first terminal of the fourth transistor MN3 is coupled to the second terminal of the third transistor MP3 , and a second terminal of the fourth transistor MN3 is grounded.
[0066] A control terminal of the fourth transistor MN3 is coupled to the bit line, and a coupling point between the third transistor MP3 and the fourth transistor MN3 is coupled to an input terminal of the inverting unit 60 .
[0067] In response to the read command, the fourth transistor MN3 is turned off, the third transistor MP3 is turned on, and the first voltage is provided to the inverting unit 60. At this time, the first voltage is at a high level, and the first voltage is inverted by the inverting unit 60 to obtain a second voltage. The second voltage is at a low level. The second voltage is output to the pre-charge current providing module 20, so that the pre-charge current providing module 20 enters the pre-charge stage and performs a pre-charge operation for the bit line through the amplifier MN1.
[0068] The third transistor MP3 is a Pmos transistor, and the fourth transistor MN3 is a Nmos transistor.
[0069] In some embodiments, in response to the bit line voltage being precharged to the target voltage, the fourth transistor MN3 is turned on to provide a third voltage to the inverting unit 60. The third voltage is a low level. The inverting unit 60 is used to invert the third voltage to obtain a fourth voltage. The fourth voltage is a high level. The inverting unit 60 outputs the fourth voltage to the control terminal of the precharge current providing module 20, so that the precharge current providing module 20 stops providing a charging current to the bit line.
[0070] In some embodiments, the bias current of the fourth transistor MN3 is less than the bias current of the second transistor MN2, thereby ensuring that the output voltage of the second amplification module can be reduced before the output voltage of the first amplification module. Since the bias current of the fourth switch tube MN3 is less than the bias current of the second transistor MN2, the fourth transistor MN3 will be turned on earlier than the second transistor MN2, and the pre-charge current providing module 20 will stop providing charging current to the bit line more quickly, thereby not affecting the normal amplification operation.
[0071] In an application scenario, the bias current per unit size of the fourth transistor MN3 is smaller than the bias current per unit size of the second transistor MN2. For example, the size of the fourth transistor MN3 is the same as that of the second transistor MN2, but the current of the fourth transistor MN3 is smaller than that of the second transistor MN2; or the current of the fourth transistor MN3 is equal to the current of the second transistor MN2, but the size of the fourth transistor MN3 is larger than that of the second transistor MN2.
[0072] The inverting unit 60 detects the output signal VCLAMP2 of the second amplifying module 50 , and outputs an inverted signal PREC_CTRL thereof for controlling the pre-charge current providing module 20 .
[0073] In the read operation, the workflow is as follows:
[0074] In the initial stage, the voltage of the bit line BL is very low. At this time, VCLAMP2 is at a high level like VCLAMP, so that the inverting signal PREC_CTRL output by the inverting unit 60 is at a low level, and the pre-charge current providing module 20 is turned on to provide a drive for the amplifier MN1 to pre-charge the bit line (BL). The working state of other devices is the same as Figure 1 The sensitive amplifier circuit shown in the figure is the same as that in the figure, so it will not be repeated here.
[0075] After the bit line (BL) reaches the threshold voltage of the NMOS tube, both VCLAMP2 and VCLAMP voltages begin to drop. Since the bias current per unit size of the fourth transistor MN3 is smaller than the bias current per unit size of the second transistor MN2, VCLAMP2 drops faster. Before BL is fully pre-charged, VCLAMP2 has dropped to a lower level, driving the output PREC_CTRL signal of INV1 to be pulled high, turning off the pre-charge current providing module 20. At this time, further pre-charging of the bit line (BL) to the target voltage will only rely on the reference current provided by the reference current providing module 10, and the speed will be reduced. However, by reasonably setting the device sizes in the first amplification module 30 and the second amplification module 50, it can be ensured that the bit line (BL) voltage is very close to the stable value of full pre-charging when the pre-charge current providing module 20 is turned off, and the impact on the pre-charging time will be very small.
[0076] The stable voltage of the bit line (BL) is determined by the characteristics of the first amplifier module 30, the amplifier tube MN1, and the current of the CELL. Due to the negative feedback characteristics, in this stable state, the second transistor MN2 and the first transistor MP2 are both in the saturation region, and the first amplifier module 30 is in the high gain amplifier region. The BL voltage at this time is the threshold voltage of the second switch tube MN2 plus the over-drive voltage (the over-drive voltage is determined by the size of MN2 and the bias current of MP2); similarly, the BL voltage when the pre-charge is closed makes the fourth transistor MN3 and the third transistor MP3 both in the saturation region, and the second amplifier module 50 is in the high gain amplifier region. The BL voltage at this time is the threshold voltage of the fourth transistor MN3 plus the over-drive voltage (the over-drive voltage is determined by the size of the fourth transistor MN3 and the bias current of the third transistor MP3). As previously described, the fourth transistor MN3 and the second transistor MN2 use the same device with the same threshold voltage. Therefore, the difference between the BL voltage and the BL stable value when the pre-charging is turned off, that is, the over-drive difference between the fourth transistor MN3 and the second transistor MN2, as long as this over-drive difference is made very small, it can be ensured that the slowdown of pre-charging after the pre-charging current providing module 20 is turned off has little effect on the overall pre-charging time.
[0077] In fact, the factors that limit the two overdrive differences are mainly the possible process mismatch. For example, the threshold of the fourth transistor MN3 may be greater than the threshold of the second transistor MN2 due to mismatch. If the overdrive difference is not enough, the precharge signal will not be turned off after the precharge is completed, resulting in data reading errors. Therefore, the overdrive difference only needs to be greater than the mismatch caused by the possible process deviation. In general integrated circuit manufacturing, the mismatch of a single MOS tube is equivalent to a threshold deviation that generally does not exceed a few mV. Therefore, the difference between the two overdrives, that is, the difference between the BL voltage when the precharge is turned off and the stable value can be controlled at around 10 to 20 mV. This value is much smaller than the total BL precharge voltage (generally around 0.7 to 1 V), that is, the BL voltage when the precharge is turned off is already very close to the stable value, and the reduction in precharge speed after it is turned off has little effect on the total precharge speed. Therefore, this solution has a similar effect on the precharge speed of BL. Figure 1 The sensitive amplifier circuit is basically the same as that of the external pre-charge signal, and will not be slowed down due to the cancellation of the external pre-charge signal. Furthermore, since the solution of the present application does not divide the read cycle into two stages of pre-charge and amplification in the control timing, there is no need to use a typical sensitive amplifier circuit (such as Figure 1 ), the amplifier automatically enters the amplification state after the pre-charge is completed, and the reading speed of the typical sensitive amplifier will not be reduced due to the pre-charge cycle being greater than the actual demand. This ensures that in all cases, the output data can appear at the output end of the sensitive amplifier circuit at the fastest speed in the current state, thereby speeding up the reading speed.
[0078] The pre-charge current providing module 20 of the present solution is controlled by an internal circuit to achieve automatic opening and closing, and does not require a controller to provide a pre-charge signal, thereby reducing the requirements for the controller and also reducing the interface signal scale between the controller and the sensitive amplifier.
[0079] See also Figure 3 , Figure 3 The sensitive amplifier circuit for non-volatile memory provided by the present application is a schematic diagram of another embodiment of the structure. The sensitive amplifier circuit includes: a reference current providing module 10, a pre-charge current providing module 20, an amplifier tube MN1, a first amplifier module 30, a second amplifier module 50, a comparison module 40 and an inverting unit 60.
[0080] The reference current providing module 10 is used to provide a reference current.
[0081] The pre-charge current providing module 20 is used to provide a charging current for a bit line in a pre-charge phase, and the bit line is used to couple a memory cell.
[0082] A first end of the amplifier MN1 is coupled to the bit line, and a second end of the amplifier MN1 is used to couple an output end of the pre-charge current providing module 20 and an output end of the reference current providing module 10 .
[0083] The first amplifier module 30 is a first amplifier, the output end of the first amplifier is coupled to the control end of the amplifier tube MN1, the inverting input end of the first amplifier is coupled to the first end of the amplifier tube MN1, and the non-inverting input end of the first amplifier is coupled to the reference voltage end; the second amplifier module 50 is a second amplifier, the output end of the second amplifier is coupled to the inverting unit 60, the inverting input end of the second amplifier is coupled to the first end of the amplifier tube MN1, and the non-inverting input end of the second amplifier is coupled to the reference voltage end; wherein the reference voltage corresponding to the second amplifier is less than the reference voltage corresponding to the first amplifier. Figure 5 As shown, the reference voltage corresponding to the in-phase input terminal of the first amplifier is VREF_A1, and the reference voltage corresponding to the in-phase input terminal of the second amplifier is VREF_A2. That is, VREF_A2 is smaller than VREF_A1.
[0084] An input terminal of the inverting unit 60 is coupled to the second terminal of the second amplifying module 50 , and an output terminal of the inverting unit 60 is coupled to the control terminal of the pre-charge current providing module 20 .
[0085] The input terminal of the comparison module 40 is coupled to the second terminal of the amplifier MN1 .
[0086] Among them, the second amplification module 50 is used to output a first voltage to the inverting unit 60 when the bit line voltage is lower than a preset voltage. The inverting unit 60 is used to invert the first voltage to obtain a second voltage and output it to the control end of the pre-charge current providing module 20. The pre-charge current providing module 20 enters the pre-charge stage to provide a charging current for the bit line.
[0087] In the read operation, the workflow is as follows:
[0088] In the initial stage, the voltage of the bit line BL is very low. At this time, VCLAMP2 is at a high level like VCLAMP, so that the output signal PREC_CTRL of the inverting unit 60 is at a low level, and the pre-charge current providing module 20 is turned on to provide a drive for the amplifier MN1 to pre-charge the bit line (BL). The working state of other devices is the same as Figure 1 The sensitive amplifier circuit shown in the figure is the same as that in the figure, so it will not be repeated here.
[0089] After the voltage of the bit line (BL) reaches the reference voltage of the first amplifier and the second amplifier, both the VCLAMP2 and VCLAMP voltages begin to decrease. Since the reference voltage corresponding to the second amplifier is lower than the reference voltage corresponding to the first amplifier, VCLAMP2 decreases earlier and faster. Before BL is fully pre-charged, VCLAMP2 has dropped to a lower level, driving the output inversion signal PREC_CTRL signal of INV1 in the inverting unit 60 to be pulled high, turning off the pre-charge current providing module 20. At this time, the further pre-charging of the bit line (BL) to the target voltage will only rely on the reference current provided by the reference current providing module 10, and the speed will be reduced. However, by reasonably setting the device sizes in the first amplification module 30 and the second amplification module 50, it can be ensured that the bit line (BL) voltage is very close to the stable value of full pre-charging when the pre-charge current providing module 20 is turned off, and the impact on the pre-charging time will be very small.
[0090] The pre-charge current providing module 20 of the present solution is controlled by an internal circuit to achieve automatic opening and closing, and does not require a controller to provide a pre-charge signal, thereby reducing the requirements for the controller and also reducing the interface signal scale between the controller and the sensitive amplifier.
[0091] In an application scenario, the 50nm NOR FLASH process is used to simulate the read operation of a storage cell in the storage array with a current difference of 2uA from the reference current and a load of 2pF. Figure 4 As shown; as a comparison, the simulation results of the typical sensitive amplifier circuit realized with the same process for the same storage unit read are as follows Figure 5 shown.
[0092] like Figure 4 As shown, Figure 2 or Figure 3 The sensitive amplifier circuit 100 has a low inversion signal PREC_CTRL at the beginning of the read cycle, and the precharge tube MP4 in the precharge current providing module 20 is turned on to charge the bit line BL. The charging speed is basically the same as that of a typical sensitive amplifier circuit, and the charging of the bit line BL is completed within about 10ns. After that, the inversion signal PREC_CTRL is controlled by the second amplifier module 50 to become a high level, and the precharge tube MP4 in the precharge current providing module 20 is automatically turned off. The amplifier MN1 enters the amplification operation, and the VSPA voltage is determined according to the difference between the reference current and the CELL current, and then the final read data SA_OUT is output through the comparison module 40. The total read cycle is about 20ns; Figure 5 As shown, Figure 1 The pre-charge signal PREC of the sensitive amplifier circuit 100 needs to be set longer to 20ns due to the need to consider the influence of various factors. The amplification operation can only be entered after the pre-charge signal PREC is turned off. The total readout cycle is about 30ns.
[0093] It should be noted that the power supply voltage, temperature, and process deviation have a great influence on the driving capability of the transistor. In addition, considering the deviation of the BL parasitic capacitance, it is reasonable in many cases to reserve a margin of twice the optimal value of the pre-charge signal width under typical conditions. Therefore Figure 4 and Figure 5 The contrast between Figure 2 or Figure 3 The sensitive amplifier circuit 100 is compared Figure 1 The advantage of the sensitive amplifier circuit 100 in readout speed.
[0094] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of a non-volatile memory provided by the present application. The non-volatile memory 1000 includes the sensitive amplifier circuit 100 as described above.
[0095] See also Figure 7 , Figure 7 2 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The electronic device 2000 includes the non-volatile memory 1000 as described above.
[0096] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
[0097] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.
[0098] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A sensitive amplifier circuit suitable for non-volatile memory, characterized in that: The sensitive amplifier circuit comprises: A reference current providing module, used for providing a reference current; A pre-charge current providing module, used for providing a charging current to a bit line in a pre-charge phase, wherein the bit line is used for coupling a storage unit; an amplifier tube, wherein a first end of the amplifier tube is coupled to the bit line, and a second end of the amplifier tube is used to couple an output end of the pre-charge current providing module and an output end of the reference current providing module; A first amplifying module, wherein a first end of the first amplifying module is coupled to the control end of the amplifying tube, and a second end of the first amplifying module is coupled to the first end of the amplifying tube; A second amplifying module, wherein a first end of the second amplifying module is coupled to a first end of the amplifying tube; an inverting unit, wherein an input end of the inverting unit is coupled to the second end of the second amplifying module, and an output end of the inverting unit is coupled to the control end of the pre-charge current providing module; A comparison module, wherein an input end of the comparison module is coupled to the second end of the amplifier tube; Among them, the second amplification module is used to output a first voltage to the inverting unit when the bit line voltage is lower than a preset voltage. The inverting unit is used to invert the first voltage to obtain a second voltage and output it to the control end of the pre-charge current providing module. The pre-charge current providing module enters the pre-charge stage to provide a charging current for the bit line.
2. The sensitive amplifier circuit according to claim 1, characterized in that: The first amplification module comprises: A first transistor, wherein a first terminal of the first transistor is coupled to a power supply voltage terminal; a second transistor, wherein a first end of the second transistor is coupled to a second end of the first transistor, and a second end of the second transistor is grounded; and a coupling point between the second transistor and the first transistor is coupled to a control end of the amplifier tube; Among them, in response to the read command, the first transistor is turned on, and a third voltage is provided to the control terminal of the amplifier tube to turn on the amplifier tube, and the pre-charge current providing module enters the pre-charge stage to perform a pre-charge operation for the bit line.
3. The sensitive amplifier circuit according to claim 2, characterized in that: The first transistor is a Pmos transistor, and the second transistor is a Nmos transistor.
4. The sensitive amplifier circuit according to claim 1 or 2, characterized in that: The second amplification module comprises: a third transistor, a first terminal of the third transistor being coupled to a power supply voltage terminal; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to a second terminal of the third transistor, and a second terminal of the fourth transistor is grounded; a control terminal of the fourth transistor is coupled to the bit line, and a coupling point between the third transistor and the fourth transistor is coupled to an input terminal of the inverting unit; In response to a read command, the fourth transistor is turned off, and the third transistor is turned on to provide the first voltage to the inverting unit.
5. The sensitive amplifier circuit according to claim 4, characterized in that: The third transistor is a Pmos transistor, and the fourth transistor is a Nmos transistor.
6. The sensitive amplifier circuit according to claim 4, characterized in that: In response to the bit line voltage being precharged to the target voltage, the fourth switch tube is turned on to provide a third voltage to the inverting unit. The inverting unit is used to invert the third voltage to obtain a fourth voltage and output it to the control end of the precharge current providing module. The precharge current providing module stops providing charging current to the bit line.
7. The sensitive amplifier circuit according to claim 4, characterized in that: A bias current of the fourth transistor is smaller than a bias current of the second transistor.
8. The sensitive amplifier circuit according to claim 1, characterized in that: The first amplification module is a first amplifier, the output end of the first amplifier is coupled to the control end of the amplifier tube, the inverting input end of the first amplifier is coupled to the first end of the amplifier tube, and the non-inverting input end of the first amplifier is coupled to the reference voltage end; The second amplifying module is a second amplifier, the output end of the second amplifier is coupled to the inverting unit, the inverting input end of the second amplifier is coupled to the first end of the amplifier tube, and the non-inverting input end of the second amplifier is coupled to the reference voltage end.
9. A non-volatile memory, characterized in that: The non-volatile memory comprises the sensitive amplifier circuit as described in any one of claims 1-8.
10. An electronic device, characterized in that: The electronic device comprises the nonvolatile memory as claimed in claim 9.