Method of repairing a storage array and memory

Abstract

The application relates to the field of semiconductor technology, in particular to a storage array repair method and a memory. The storage array repair method comprises the following steps: performing a leakage test on a plurality of control lines in a storage array to obtain a first test result, the first test result comprising a leakage characteristic value of each control line, the leakage characteristic value being used for indicating whether a leakage current value of the corresponding control line is greater than a leakage threshold value; performing a cell opening test on a plurality of storage units in the storage array to obtain a second test result, the second test result comprising the number of leakage units on each control line; obtaining a replacement address based on the first test result and the second test result; and repairing the replacement address by using a redundant address, the redundant address being a control line address corresponding to a redundant array. The storage array repair method provided by the application aims to improve the utilization rate of redundant resources in the memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a repair method of a storage array and a memory. BACKGROUND

[0002] Memory is used to store information in various electronic devices (such as computers, wireless communication devices, cameras, etc.), and the information is stored by regulating different states of the memory.

[0003] Generally, there are redundant signal lines and cells in the memory, and when a problem cell is found in the storage array, the defective cell is replaced with a redundant cell, wherein row repair and column repair are two common repair methods for the memory.

[0004] The way to detect the failure of the storage array is to perform a leakage test on the word line (WL) and the bit line (BL), and to determine whether the storage cell needs to be repaired according to the leakage of the word line (WL) and the bit line (BL); wherein a threshold is set when testing the leakage, and if the threshold is exceeded, it is determined that there is leakage.

[0005] The number and degree of leakage of the storage cells in wafers of different processes are different, but the number of redundant cells in the memory is limited. In the conventional leakage test, a single threshold setting cannot maximize the use of redundant resources. SUMMARY

[0006] The main purpose of the present application is to provide a repair method of a storage array and a memory, which aims to improve the utilization rate of redundant resources in the memory.

[0007] To achieve the above purpose, the present application provides a repair method of a storage array, comprising: performing a leakage test on a plurality of control lines in the storage array to obtain a first test result, the first test result comprising a leakage characterization value of each control line, the leakage characterization value being used to characterize whether the leakage current value corresponding to the control line is greater than a leakage threshold; performing a cell opening test on a plurality of storage cells in the storage array to obtain a second test result, the second test result comprising the number of leakage cells on each control line; obtaining a replacement address based on the first test result and the second test result; repairing the replacement address using a redundant address, the redundant address being a control line address corresponding to a redundant array.

[0008] In some embodiments, the replacement address includes a first address, or the replacement address includes a first address and a second address; the first address is an address of a control line in which a number of leakage units in the second test result is greater than a first preset value; and the second address is an address of a control line in which a leakage characteristic value in the first test result is a second preset value.

[0009] In some embodiments, the method of obtaining a replacement address based on the first test result and the second test result includes: comparing the second test result with the first preset value, and obtaining a control line in which a number of leakage units is greater than the first preset value in a plurality of control lines to obtain the first address; and obtaining a control line in which a leakage characteristic value in the first test result is a second preset value in the plurality of control lines to obtain the second address.

[0010] In some embodiments, the method of repairing the replacement address based on redundant addresses includes: after repairing the first address using the redundant addresses, repairing the second address using the remaining redundant addresses.

[0011] In some embodiments, the method of repairing the replacement address using redundant addresses includes: sorting the first address based on the number of leakage units in size order, and repairing the first address in size order of the number of leakage units; and sorting the second address based on the size order of the leakage characteristic value, and repairing the second address in size order of the leakage characteristic value.

[0012] In some embodiments, the method of performing the unit-on test includes: configuring a to-be-tested storage unit in a storage array to an on state; reading a state of the to-be-tested storage unit based on a high-level read voltage; if the to-be-tested storage unit read is in an off state, the to-be-tested storage unit is the leakage unit; and obtaining a number of leakage units on each to-be-tested control line in the storage array.

[0013] In some embodiments, the leakage test and the unit-on test are performed sequentially.

[0014] In some embodiments, the redundant addresses are provided by a redundant array, and the method of obtaining a replacement address based on the first test result and the second test result comprises: obtaining a quantity correspondence between the redundant address and the replacement address in a repair strategy of the redundant array; obtaining a third test result based on the correspondence and the first test result; the third test result comprises a quantity of the plurality of control lines whose leakage characterization values are second preset values in the correspondence; obtaining a fourth test result based on the correspondence and the second test result; the fourth test result comprises a total of the leakage units on the plurality of control lines in the correspondence; and obtaining the replacement address based on the third test result and the fourth test result.

[0015] In some embodiments, before repairing the replacement address by using the redundant address, the repair method further comprises: performing the leakage test on a plurality of the redundant addresses to obtain a fifth test result; the fifth test result comprises a leakage characterization value of each of the redundant addresses; obtaining a redundant address with a leakage characterization value being a third preset value from the plurality of the redundant addresses to obtain a repair address; and the method of repairing the replacement address by using the redundant address comprises: repairing the replacement address by using the repair address.

[0016] Embodiments of the present application also provide a memory repaired by the repair method of the storage array, comprising: a storage array and a redundant array; a detection module connected to the storage array, the detection module being configured to perform a leakage test on a plurality of control lines in the storage array to obtain a first test result, the first test result comprising a leakage characterization value of each of the control lines; perform a unit opening test on a plurality of storage units in the storage array to obtain a second test result, the second test result comprising a quantity of leakage units on each of the control lines; a control module connected to the detection module and the redundant array, the control module being configured to obtain a replacement address based on the first test result and the second test result; and repair the replacement address by using a redundant address, the redundant address being a control line address corresponding to the redundant array.

[0017] The repair method of the storage array provided by the present application obtains a replacement address by combining a unit opening test and a leakage test; wherein, the storage unit with a larger quantity of leakage units on the control line obtained based on the unit opening test, and the control line with a leakage current value greater than a leakage threshold value obtained based on the leakage test. On this basis, the replacement address is repaired based on a redundant address, and the storage unit with relatively serious leakage is repaired preferentially, thereby improving the utilization rate of redundant resources and the repair efficiency in the memory.

[0018] In some embodiments, the repair address is obtained by leakage test on the redundant address, so as to ensure that the repair address is a leakage normal repair unit, thereby ensuring that the memory unit works normally after the memory is repaired by redundancy. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0020] Figure 1 The flowchart corresponding to each step in the repair method of the storage array provided by the embodiments of the present application is shown.

[0021] Figure 2 The structure diagram of the storage array provided by the embodiments of the present application is shown.

[0022] Figure 3 The step diagram corresponding to the first repair method of repairing the storage array based on the repair address provided by the embodiments of the present application is shown.

[0023] Figure 4 The step diagram corresponding to the second repair method of repairing the storage array based on the repair address provided by the embodiments of the present application is shown.

[0024] Figure 5 The step diagram corresponding to the third repair method of repairing the storage array based on the repair address provided by the embodiments of the present application is shown.

[0025] Figure 6 The structure diagram of the memory provided by the embodiments of the present application is shown.

[0026] The implementation of the present application, functional characteristics and advantages will be further described with reference to the drawings. DETAILED DESCRIPTION

[0027] Based on the background art, the number and leakage degree of leakage memory cells in wafers of different processes are different, but the number of redundant units in the memory is limited. In the conventional leakage test, a single threshold setting cannot maximize the use of redundant resources.

[0028] The leakage test of the memory includes an analog test and a digital test. The analog test measures the actual leakage current value by externally applying a voltage. The digital test compares the leakage threshold value and the leakage current by a comparator in the chip, and outputs 1 if the leakage current exceeds the leakage threshold value, and outputs 0 otherwise.

[0029] The digital test is generally used because the analog test is relatively slow and the number of word lines / bit lines to be tested in the memory chip is large. In this case, the leakage threshold value in the leakage test is the leakage threshold value set by the chip in the digital test. The output result of "1" indicates that the leakage of the test line is large, and the output result of "0" indicates that the leakage of the test line is small.

[0030] The leakage test is performed based on the digital test in this embodiment, which is used as an example and does not constitute a limitation on this embodiment. In other embodiments, the leakage test can be performed based on the analog test.

[0031] In one example, when the leakage threshold value is set too large, the number of results of "1" decreases, the number of results of "0" increases, and some test lines with leakage currents close to the leakage threshold value cannot be repaired. When the leakage threshold value is set too small, the number of results of "1" increases, the number of results of "0" decreases, and some test lines with large leakage currents and output of "1" can not be repaired preferentially. Setting multiple leakage threshold values for leakage testing will increase the test time by several times, and reduce the efficiency of redundant repair.

[0032] The embodiment provides a repair method of a memory array, including: performing a leakage test on a plurality of control lines in the memory array to obtain a first test result, the first test result including a leakage representation value of each control line, the leakage representation value being used to represent whether a leakage current value of the corresponding control line is greater than a leakage threshold value; performing a cell-on test on a plurality of memory cells in the memory array to obtain a second test result, the second test result including a number of leakage cells on each control line; obtaining a replacement address based on the first test result and the second test result; and repairing the replacement address by using a redundant address, the redundant address being a control line address in a redundant array.

[0033] The repair method of the memory array provided in the embodiment combines the cell-on test and the leakage test to obtain the replacement address, which includes the memory cell with a large number of leakage cells on the control line obtained based on the cell-on test, and the control line with a leakage current value greater than the leakage threshold value obtained based on the leakage test. On this basis, the replacement address is repaired based on the redundant address, the memory cell with relatively serious leakage is preferentially repaired, and the utilization rate and the repair efficiency of the redundant resources in the memory are improved.

[0034] It should be noted that the present embodiment is exemplified based on the leakage test performed based on the digital test, and does not constitute a limitation on the present embodiment. In other embodiments, the leakage test can be performed based on the analog test. At this time, the leakage characterization value is obtained by comparing the leakage current value obtained based on the analog test with the externally preset leakage threshold value.

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0036] In addition, the descriptions such as "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions appears to be contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection claimed by the present application.

[0037] Reference Figure 1 , Figure 1 The flowchart corresponding to each step in the repair method of the storage array provided in the present embodiment includes:

[0038] Step 101, performing a leakage test on the storage array.

[0039] Step 102, performing a unit opening test on the storage array.

[0040] Step 103, obtaining a replacement address.

[0041] Step 104, repairing the replacement address using a redundant address.

[0042] The following will be described in detail with reference to the drawings.

[0043] Step 101, performing a leakage test on the storage array.

[0044] Performing a leakage test on a plurality of control lines in the storage array obtains a first test result, and the first test result includes a leakage characterization value of each control line. The leakage characterization value is used to characterize whether the leakage current value of the corresponding control line is greater than the leakage threshold value.

[0045] In one example, if the leakage current value of the corresponding control line is greater than or equal to the leakage threshold, the leakage current characterization value is "1"; if the leakage current value of the corresponding control line is less than the leakage threshold, the leakage current characterization value is "0".

[0046] For storage arrays, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the storage array provided in this embodiment. The storage array includes storage cells 300 arranged in an array, wherein storage cells 300 in the same row are connected to the same word line WL, and storage cells in the same column are connected to the same bit line BL; in the extension direction of the word line WL, the storage array includes bit lines BL1 to BL8, and in the extension direction of the bit line BL, the storage array includes word lines WL1 to WL8.

[0047] It should be noted that the "control line" mentioned above can be at least one of word line WL or bit line BL. In this case, the leakage current characterization value indicates whether the leakage current value of the corresponding word line or bit line is greater than the leakage current threshold. This embodiment will be described in detail with word line WL as the control line, which does not constitute a limitation on this embodiment.

[0048] It should also be noted that for multi-layer stacked memory arrays, multiple word lines (WL) or bit lines (BL) share a single control line. In this case, the leakage current characteristic value of the control line indicates the number of word lines or bit lines whose leakage current on the control line exceeds the leakage current threshold.

[0049] In one example, multiple control lines include word lines WL1, WL2, WL3...WLn. A leakage current test is performed on word line WL1, and the leakage current characteristic value on word line WL1 is obtained. Then, the leakage current test is performed on word line WL2, and so on, until the leakage current test is completed on word line WLn, and the leakage current characteristic value on word line WLn is obtained. The leakage current characteristic value of each word line WL1, WL2, WL3...WLn constitutes the first test result.

[0050] For leakage current testing, all memory cells on the control line under test are set to the "SET" state, and then the leakage current characterization value on the control line under test is obtained. After that, all memory cells on the control line are set to the "RESET" state.

[0051] It should be noted that for the "SET" and "RESET" states of a storage unit, the "SET" state means that the storage unit stores data "1", and the "RESET" state means that the storage unit stores data "0".

[0052] Step 102: Start the test for the storage array execution unit.

[0053] performing a cell open test on a plurality of memory cells in the memory array to obtain a second test result, the second test result comprising a number of leaky cells on each control line.

[0054] For the cell open test, in some embodiments, the method of performing the cell open test comprises: configuring a to-be-tested memory cell in the memory array to an open state; reading a state of the to-be-tested memory cell based on a high-level read voltage; if the read to-be-tested memory cell is in a closed state, the to-be-tested memory cell is a leaky cell; and obtaining a number of leaky cells on each to-be-tested control line in the memory array.

[0055] In one example, the to-be-tested memory cell is initialized to a "SET" state, at which time the to-be-tested memory cell stores data "1", and the untested memory cell is initialized to a "RESET" state, at which time the untested memory cell stores data "0"; a state of the to-be-tested memory cell is read based on a high-level read voltage, at which time if the to-be-tested memory cell is normal, the read to-be-tested memory cell is in a "SET" state, and if the to-be-tested memory cell is seriously leaky, the read to-be-tested memory cell is in a "RESET" state; after the cell open test of the to-be-tested memory cell is completed, the to-be-tested memory cell is reset to a "RESET" state, and the next to-be-tested memory cell is initialized to a "SET" state, until the number of leaky cells on the to-be-tested control line is obtained.

[0056] It should be noted that the execution object of the cell open test is the memory cell, and the number of leaky cells on the to-be-tested control line needs to be obtained by sequentially performing the cell open test on all memory cells connected to the to-be-tested control line.

[0057] In one example, the plurality of control lines comprises word lines WL1, WL2, WL3, …, WLn, the cell open test is performed on all memory cells on the word line WL1, after the number of leaky cells on the word line WL1 is obtained, the cell open test is performed on all memory cells on the word line WL2, and so on, until the cell open test on all memory cells on the word line WLn is completed, and the number of leaky cells on the word line WLn is obtained. Wherein, the number of leaky cells on each word line WL1, WL2, WL3, …, WLn constitutes the second test result.

[0058] It should also be noted that for a multi-layer stacked memory array, a plurality of word lines WL or bit lines BL share a control line, at which time the second test result comprises a number of leaky cells on each control line corresponding to the word line or the bit line.

[0059] In some embodiments, the leak test and the cell open test can be performed in steps.

[0060] In some embodiments, the leakage test and the cell open test are performed in sequence, specifically, one of the leakage test or the cell open test is performed preferentially, and then the other of the leakage test or the cell open test is performed.

[0061] At step 103, the replacement address is obtained.

[0062] The replacement address is obtained based on the first test result and the second test result. Specifically, the replacement address is obtained based on the test results of steps 101 and 102.

[0063] In some embodiments, the replacement address includes a first address and a second address. The first address is obtained based on the second test result, and the first address is the address of the control line in which the number of leakage cells is greater than a first preset value in the second test result. The second address is obtained based on the first test result, and the second address is the address of the control line in which the leakage characteristic value is the second preset value in the first test result.

[0064] In one example, the leakage characteristic value is the second preset value, i.e., the leakage characteristic value is "1", so as to obtain the address of the control line in which the leakage current is greater than the leakage threshold.

[0065] It should be noted that for a multi-layer stacked memory array, a plurality of word lines WL or bit lines BL share one control line, and in this case, the leakage characteristic value of the control line represents the number of word lines or bit lines in which the leakage current exceeds the leakage threshold. In this case, the first address is the address of the control line in which the sum of the number of leakage cells corresponding to each word line WL or bit line BL is greater than the first preset value. The second address is the address of the control line in which the leakage characteristic value is greater than the fourth preset value in the first test result.

[0066] In some embodiments, the method of obtaining the replacement address based on the first test result and the second test result includes: comparing the second test result with the first preset value, obtaining the control line in which the number of leakage cells is greater than the first preset value among the plurality of control lines, to obtain the first address; the first address is the address of the control line in which the number of leakage cells is greater than the first preset value. Comparing the first test result with the second preset value, obtaining the control line in which the leakage characteristic value is the second preset value in the first test result among the plurality of control lines, to obtain the second address; the second address is the address of the control line in which the leakage characteristic value is the second preset value.

[0067] It should be noted that in the leakage test, the leakage characteristic value of the control line represents whether the corresponding test line leaks. The number of leakage cells on each control line is counted through the cell open test. The number of leakage cells is positively correlated with the size of the leakage current of the control line, and can reflect the degree of leakage on the control line to a certain extent. By reasonably setting the first preset value, the first address obtained based on the cell open test can be repaired preferentially, so as to preferentially repair the control line with the most serious leakage.

[0068] For the multi-layer stacked memory cells, the leakage current characterization value of the leakage current test on the control line characterizes the leakage current degree of the corresponding control line, and the number of leakage cells on each control line is counted through the cell opening test, which can also reflect the leakage current degree of the control line to a certain extent. By reasonably setting the first preset value and the fourth preset value, the repair of the control line with the most serious leakage current can be preferentially realized by preferentially repairing the first address obtained based on the cell opening test.

[0069] In some application scenarios, due to the limitation of redundant resources, the redundant resources are insufficient to complete the complete repair of the first address, and at this time the replacement address only includes the first address.

[0070] Based on the foregoing description, it can be known that the redundant address is provided by the redundant array, and the replacement of the redundant resources of part of the memory on the market appears in pairs or in blocks. A value written in the content-addressable memory (CAM) by mapping the faulty cell to the redundant cell can include multiple control lines, and the objects of the first test result and the second test result are single control lines.

[0071] Based on this scenario, in some embodiments, the method of obtaining the replacement address based on the first test result and the second test result includes (i.e., step 103 includes): obtaining a correspondence relationship between the redundant address and the number of replacement addresses in the repair strategy of the redundant array; obtaining a third test result based on the correspondence relationship and the first test result, the third test result including the number of multiple control lines with the leakage current characterization value being the second preset value under the correspondence relationship; obtaining a fourth test result based on the correspondence relationship and the second test result, the fourth test result including the sum of the number of leakage memory cells on multiple control lines under the correspondence relationship; and obtaining the replacement address based on the third test result and the fourth test result.

[0072] Step 104, repairing the replacement address by using the redundant address.

[0073] Repairing the replacement address by using the redundant address, the redundant address being the control line address corresponding to the redundant array.

[0074] Based on the foregoing description, preferentially repairing the first address obtained based on the cell opening test can preferentially realize the repair of the control line with the most serious leakage current, i.e., in some embodiments, the method of repairing the replacement address based on the redundant address includes: after repairing the first address by using the redundant address, repairing the second address by using the remaining redundant address.

[0075] It should be noted that the redundant address mentioned in the embodiment refers to the address of the control line in the redundant array in the memory; the replacement of the redundant unit in the redundant array to the storage unit in the storage array is actually the replacement of the read and write operation of the defective storage unit to the read and write operation of the redundant unit in the process of storage and addressing of the storage array, that is, the replacement of the redundant unit and the storage unit is realized by address replacement.

[0076] In some embodiments, the method of repairing the replacement address by using the redundant address comprises: sorting the first addresses based on the number of leakage units in size order, and sequentially repairing the first addresses according to the number of leakage units in size order; sorting the second addresses based on the number of leakage characteristic values being the second preset value in size order, and sequentially repairing the second addresses according to the number of leakage characteristic values being the second preset value in size order.

[0077] Figure 3 is a flowchart corresponding to each step in the repair method of the storage array provided by another embodiment of the present application. Figure 3 The embodiment shown in Figure 1 The difference between the embodiment shown in and the embodiment shown in is that after step 103 is performed and before step 104 is performed, step 105 of obtaining a repair address in the redundant address is further included. At this time, step 104 repairs the replacement address by using the redundant address, that is, repairs the replacement address by using the repair address.

[0078] Specifically, before the replacement address is repaired by using the redundant address, the repair method further includes: performing a leakage test on the plurality of redundant addresses to obtain a fifth test result; the fifth test result includes a leakage characteristic value of each redundant address; obtaining a redundant address with a leakage characteristic value being a third preset value from the plurality of redundant addresses to obtain the repair address; the method of repairing the replacement address by using the redundant address includes: repairing the replacement address by using the repair address.

[0079] In one example, the leakage characteristic value is the third preset value, that is, the leakage characteristic value is "0", so as to obtain the redundant address with the leakage current less than the leakage threshold.

[0080] It should be noted that the redundant address refers to the address of the redundant control line in the redundant unit.

[0081] In one example, the plurality of redundant control lines include redundant word lines WLx1, WLx2, WLx3, …, WLxn, the leakage test is performed on the redundant word line WLx1, the leakage characteristic value on the redundant word line WLx1 is obtained, the leakage test is performed on the redundant word line WLx2, and the leakage test on the redundant word line WLxn is completed until the leakage characteristic value on the redundant word line WxLn is obtained. The leakage characteristic value of each redundant word line WLx1, WLx2, WLx3, …, WLxn constitutes the fifth test result.

[0082] In the plurality of redundant control lines, the redundant control line with the leakage characterization value being the third preset value is obtained to obtain the repair address. The repair address is obtained through the leakage test on the redundant address, so as to ensure that the repair address is the repair unit with normal leakage, thereby ensuring that the storage unit of the memory works normally after the redundancy repair.

[0083] Figure 4 is a flowchart corresponding to each step in the storage array repair method provided by another embodiment of the present application. Figure 4 The embodiment shown in Figure 3 The difference between the embodiment shown in Figure 3 In the example, step 105 is located after the execution of step 103 and before the execution of step 104; and Figure 4 In the example, step 105 is executed simultaneously with step 103, so as to reduce the overall running time of the storage array repair method.

[0084] Figure 5 is a flowchart corresponding to each step in the storage array repair method provided by another embodiment of the present application. Figure 5 The embodiment shown in Figure 3 The difference between the embodiment shown in Figure 3 In the example, step 105 is located after the execution of step 103 and before the execution of step 104; and Figure 5 In the example, step 105 is executed simultaneously with step 101 and step 102, so as to reduce the overall running time of the storage array repair method.

[0085] It should be noted that the storage array provided by the present embodiment can include a static random access memory array, a dynamic random access memory array, a ferroelectric random access memory array, or a phase change random access memory array.

[0086] The storage array repair method provided by the present embodiment combines the cell opening test and the leakage test to obtain the replacement address; wherein, the storage unit with a larger number of leakage cells on the control line obtained based on the cell opening test, and the control line with a leakage current value greater than the leakage threshold value obtained through the leakage test. On this basis, the replacement address is repaired based on the redundant address, and the relatively serious leakage storage unit is preferentially repaired, thereby improving the utilization rate of the redundant resources in the memory and the repair efficiency.

[0087] It should be noted that the features of the memory provided by the above embodiments can be randomly combined to obtain a new memory embodiment without conflict.

[0088] The present embodiment further provides a memory, which aims to improve the utilization rate of the redundant resources in the memory.

[0089] Specifically, the memory is repaired by using the repair method of the memory provided in the above embodiment, including: a storage array and a redundancy array, a detection module connected to the storage array, the detection module being configured to: perform a leakage test on a plurality of control lines in the storage array to obtain a first test result, the first test result including a leakage characterization value of each control line; perform a cell-on test on a plurality of storage cells in the storage array to obtain a second test result, the second test result including a number of leakage cells on each control line; a control module connected to the detection module and the redundancy array, the control module being configured to obtain a replacement address based on the first test result and the second test result; and repair the replacement address by using a redundancy address, the redundancy address being a control line address corresponding to the redundancy array.

[0090] Reference Figure 6 , Figure 6 A structural schematic diagram of the memory provided in the embodiment is shown in FIG. 1.

[0091] The memory 20 includes a storage array 201, a redundancy array 202, a detection module 301, and a control module 302, wherein the detection module 301 is connected to the storage array 201, and the control module 302 is connected to the detection module 301 and the redundancy array 202.

[0092] The detection module 301 is configured to perform a leakage test and a cell-on test on a plurality of control lines in the storage array 201 to obtain a first test result and a second test result. The detection logic of the control module 302 can refer to the description of steps 101 and 102 in the above embodiment, and the description of the present embodiment will not be repeated.

[0093] The control module 302 is configured to obtain a replacement address according to the first test result and the second test result, and repair the replacement address by using a redundancy address, the redundancy address being a control line address corresponding to the storage array.

[0094] The control logic of the control module 302 can refer to the description of steps 103 and 104 in the above embodiment, and the description of the present embodiment will not be repeated.

[0095] In some embodiments, the detection module 301 is further configured to obtain a third test result based on the first test result, and obtain a fourth test result based on the second test result. At this time, the control module 302 obtains a replacement address according to the third test result and the fourth result, and repairs the replacement address by using a redundancy address.

[0096] In some embodiments, the detection module 301 is further configured to perform a leakage test on the plurality of control lines in the redundancy array 202 to obtain a repair address from the redundancy address, and to repair the replacement address based on the repair address, that is, the detection module 301 is further configured to perform a leakage test on the plurality of control lines in the redundancy array 202 to obtain a fifth test result, and the control module 302 is configured to obtain a repair address in the redundancy address based on the fifth test result, and to repair the replacement address based on the repair address.

[0097] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the detailed description of other embodiments above, which will not be repeated here.

[0098] The above has described the basic concept, and it is obvious that the above detailed disclosure is only used as an example and does not limit the present application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are suggested in the present application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0099] The above has described the basic concept, and it is obvious that the above detailed disclosure is only used as an example and does not limit the present application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are suggested in the present application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0099] The above has described the basic concept, and it is obvious that the above detailed disclosure is only used as an example and does not limit the present application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are suggested in the present application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.​

Claims

1. A method of repairing a memory array, comprising: The method comprises the following steps: performing a leakage test on a plurality of control lines in the storage array to obtain a first test result, the first test result comprising a leakage characterization value of each control line, the leakage characterization value being used to characterize whether a leakage current value of the corresponding control line is greater than a leakage threshold value; performing a cell opening test on a plurality of storage cells in the storage array to obtain a second test result, the second test result comprising a number of leakage cells on each control line; based on the first test result and the second test result, obtaining a replacement address; the replacement address comprises a first address, or the replacement address comprises a first address and a second address; repairing the replacement address using redundant addresses, the redundant addresses being control line addresses corresponding to a redundant array; the method of repairing the replacement address using redundant addresses comprises: after repairing the first address using the redundant addresses, repairing the second address using the remaining redundant addresses.

2. The method of repairing a storage array of claim 1, wherein, The first address is the address of the control line in the second test result whose number of leakage cells is greater than a first preset value; The second address is the address of the control line in the first test result whose leakage characterization value is a second preset value.

3. The method of repairing a memory array of claim 2, wherein, The method of obtaining a replacement address based on the first test result and the second test result comprises: comparing the second test result with the first preset value to obtain the control line whose number of leakage cells is greater than the first preset value in the plurality of control lines, thereby obtaining the first address; obtaining the control line whose leakage characterization value in the first test result is a second preset value in the plurality of control lines, thereby obtaining the second address.

4. The method of repairing a memory array of claim 3, wherein, The method of repairing the replacement address using redundant addresses comprises: sorting the first address based on the number of leakage cells in descending order, and repairing the first address in descending order of the number of leakage cells; sorting the second address based on the leakage characterization value in descending order, and repairing the second address in descending order of the leakage characterization value.

5. The method of repairing a memory array of claim 1, wherein, The method of performing the cell opening test comprises: configuring a to-be-tested storage cell in the storage array to an open state; reading the state of the to-be-tested storage cell based on a high-level read voltage; if the to-be-tested storage cell is read as a closed state, the to-be-tested storage cell is the leakage cell; obtaining the number of leakage cells on each to-be-tested control line in the storage array.

6. The method of repairing a memory array of any of claims 1-5, wherein, The leakage test and the cell opening test are performed sequentially.

7. The method of repairing a memory array of any of claims 1-5, wherein, The redundant addresses are provided by a redundant array, and the method of obtaining a replacement address based on the first test result and the second test result comprises: obtaining a correspondence between the redundant addresses and the number of replacement addresses in a repair strategy of the redundant array; based on the correspondence and the first test result, obtaining a third test result; the third test result comprising the number of control lines whose leakage characterization value is a second preset value under the correspondence; Based on the correspondence and the second test result, a fourth test result is obtained; the fourth test result includes the sum of the leakage units on the plurality of control lines under the correspondence; Based on the third test result and the fourth test result, the replacement address is obtained.

8. The method of repairing a memory array of any of claims 1-5, wherein, Before the replacement address is repaired by using the redundant address, the repair method of the storage array further includes: Performing the leakage test on the plurality of redundant addresses to obtain a fifth test result; the fifth test result includes the leakage characterization value of each redundant address; Obtaining a redundant address with a third preset leakage characterization value from the plurality of redundant addresses to obtain a repair address; The method for repairing the replacement address by using the redundant address includes: repairing the replacement address by using the repair address.

9. A memory repaired using the repair method of any one of claims 1 to 8 for a memory array, characterized by, It includes: A storage array and a redundant array; A detection module connected to the storage array, the detection module is configured to: Performing a leakage test on the plurality of control lines in the storage array to obtain a first test result, the first test result includes the leakage characterization value of each control line; Performing a unit opening test on the plurality of storage units in the storage array to obtain a second test result, the second test result includes the number of leakage units on each control line; A control module connected to the detection module and the redundant array, the control module is configured to obtain a replacement address based on the first test result and the second test result; Repairing the replacement address by using a redundant address, the redundant address is a control line address corresponding to the redundant array.

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