Semiconductor chip and semiconductor package including same

Abstract

A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes: a substrate; a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; a third interlayer insulating layer and a fourth interlayer insulating layer stacked on the lower pad and the second interlayer insulating layer; an upper pad on the fourth interlayer insulating layer and having a second thickness greater than the first thickness in the vertical direction; and a via structure in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pad and the upper pad. Each via structure includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor chip and a semiconductor package including the semiconductor chip. Background Art

[0002] Semiconductor packages are configured to easily use integrated circuit chips as part of electronic products. Traditionally, semiconductor packages include a printed circuit board (PCB) and a semiconductor chip die, which is mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, many studies are being conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0003] An object of the inventive concept is to provide a semiconductor chip with improved reliability.

[0004] An object of the inventive concept is to provide a semiconductor package with improved reliability.

[0005] A semiconductor chip according to some embodiments of the inventive concept includes: a substrate; a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer, which are stacked in sequence on the substrate; a lower pad, which is on the second interlayer insulating layer and has a first thickness in a vertical direction; a third interlayer insulating layer and a fourth interlayer insulating layer, which are stacked in sequence on the lower pad and the second interlayer insulating layer; an upper pad, which is on the fourth interlayer insulating layer and has a second thickness greater than the first thickness in the vertical direction; and a via structure, which is in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connects the lower pad and the upper pad, wherein each via structure includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping with the first via in the vertical direction.

[0006] A semiconductor chip according to some embodiments of the inventive concept includes: a substrate; a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer, which are sequentially stacked on the substrate; a through via in the first interlayer insulating layer and the substrate; a via insulating layer interposed between the through via and the substrate; a wiring in the porous insulating layer; a contact plug in the first interlayer insulating layer and in contact with one of the wirings; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; a third interlayer insulating layer and a fourth interlayer insulating layer, which are sequentially stacked on the lower pad and the second interlayer insulating layer ; an upper pad, which is on the fourth interlayer insulating layer and has a second thickness greater than the first thickness in the vertical direction; and a via structure, which is in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connects the lower pad and the upper pad, wherein the third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer stacked in sequence, each via structure includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping with the first via in the vertical direction, and each via structure has a height of 1.0μm to 10μm in the vertical direction.

[0007] A semiconductor package according to some embodiments of the inventive concept includes: a packaging substrate; a first semiconductor chip on the packaging substrate; and a second semiconductor chip and a third semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip and the third semiconductor chip are spaced apart from each other in a lateral direction, wherein the third semiconductor chip includes a buffer die and a memory die stacked in sequence, and the first semiconductor chip and the memory die each include: a substrate; a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer, stacked in sequence on the substrate; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; a third interlayer insulating layer on the lower pad and the second interlayer insulating layer; an upper pad on the third interlayer insulating layer and having a second thickness greater than the first thickness in the vertical direction; and a via structure, electrically connecting the lower pad and the upper pad through the third interlayer insulating layer, each via structure of the first semiconductor chip having a first height in the vertical direction, and each via structure in the memory die having a second height less than the first height in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0009] Figure 1 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0010] FIG. 2A to FIG. 2C A plan view of a landing pad and an upper pad according to an embodiment of the inventive concept is shown.

[0011] Figure 3 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0012] Figure 4 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0013] Figure 5 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0014] Figure 6 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0015] Figure 7 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0016] Figure 8 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0017] Fig. 9A is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0018] Fig. 9B yes Fig. 9A An enlarged view of portion “P2”.

[0019] FIG. 10A to FIG. 10G It is shown in sequence that the manufacturing Figure 1 A view of a method of manufacturing a semiconductor chip. DETAILED DESCRIPTION

[0020] Hereinafter, in order to explain the inventive concept in detail, embodiments according to the inventive concept will be described with reference to the accompanying drawings. Herein, terms indicating order such as first, second, etc. are used to distinguish components performing the same / similar functions, and their numbers may change depending on the order in which they are mentioned.

[0021] Figure 1 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0022] Reference Figure 1 , the semiconductor chip 100 according to this example may include a substrate 1. In this specification, a "semiconductor chip" may also be referred to as a "semiconductor die". The substrate 1 may include, for example, a semiconductor material. The substrate 1 may be a silicon single crystal substrate. The substrate 1 may include a first region DR and a second region ER. For example, the first region DR may be a device region in which an integrated circuit and a through-via are disposed. The second region ER may be a dummy region or an edge region.

[0023] The transistor TR may be disposed in the first region DR on the front surface of the substrate 1. Although not shown, a shallow device isolation pattern, a memory cell, a capacitor, etc. may be disposed in the first region DR on the front surface of the substrate 1. The memory cell may include a word line and a bit line.

[0024] The front surface of the substrate 1 may be covered by a first interlayer insulating layer 3. The first interlayer insulating layer 3 may cover a transistor TR, a memory cell, a capacitor, and the like. For example, the first interlayer insulating layer 3 may have a single-layer or multilayer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A first contact (e.g., a contact plug) 5c electrically connected to the transistor TR may be provided in the first interlayer insulating layer 3 on the first region DR. For example, the first contact 5c may be in contact with the first wiring 11. The second contact 5g may be provided in the first interlayer insulating layer 3 on the second region ER. According to one example, each second contact 5g may be a dummy pattern, a guard ring pattern, a chipping dam pattern, or a test pattern. The guard ring pattern or the chipping dam pattern may be used to protect the first region DR from moisture or physical cracks. When viewed in a plan view, the guard ring pattern or the chipping dam pattern may have a closed curve shape surrounding the first region DR.

[0025] A plurality of porous insulating layers 10 are stacked on the first interlayer insulating layer 3. Each porous insulating layer 10 may be formed of a low-k material having a dielectric constant smaller than that of silicon oxide. Each porous insulating layer 10 may have a density smaller than that of the first interlayer insulating layer 3. The mechanical strength of each porous insulating layer 10 may be smaller than that of the first interlayer insulating layer 3. Each porous insulating layer 10 may include carbon. Each porous insulating layer 10 may include SiOCH. Although not shown, a silicon nitride layer or a SiCN layer may be interposed between the porous insulating layers 10.

[0026] The first via 9 and the first wiring 11 are provided in the porous insulating layer 10 in the first region DR. The second via 9g and the second wiring 11g are provided in the porous insulating layer 10 in the second region ER. Each of the first via 9, the first wiring 11, the second via 9g and the second wiring 11g may include copper. The side surface and the lower surface of each of the first via 9, the first wiring 11, the second via 9g and the second wiring 11g may be covered with a diffusion barrier layer. The diffusion barrier layer may include at least one of titanium, tantalum, titanium nitride and tantalum nitride. At least one of the first via 9, the first wiring 11, the second via 9g and the second wiring 11g may have a dual damascene pattern structure.

[0027] Each of the second via 9g and the second wiring 11g may be a dummy pattern, a guard ring pattern, a broken dam pattern, or a test pattern. The guard ring pattern or the broken dam pattern may be used to protect the first region DR from moisture or physical cracks. When viewed in a plan view, the guard ring pattern or the broken dam pattern may have a closed curve shape surrounding the first region DR.

[0028] The rear surface of the substrate 1 is covered by a lower passivation layer 40. The lower passivation layer 40 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, SiCN, and polyimide.

[0029] In the first region DR, the through via TV may penetrate the substrate 1, the lower passivation layer 40, and the first interlayer insulating layer 3 and may contact one of the first wirings 11. As used herein, the term "contact" refers to direct physical contact. The through via TV may be electrically connected to at least one of the transistors TR through some of the first wirings 11.

[0030] The through via TV may include copper or tungsten. The side surface of the through via TV may be covered by a diffusion barrier layer. The diffusion barrier layer may include at least one of titanium, tantalum, titanium nitride, and tantalum nitride. The through via insulating layer TL may be interposed between the through via TV and the substrate 1. The through via insulating layer TL may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The through via insulating layer TL may include an air gap region therein.

[0031] The lower conductive bump 46 is disposed under the lower passivation layer 40 and contacts the through via TV. The lower conductive bump 46 may include at least one of copper, aluminum, nickel, and gold.

[0032] The uppermost one of the porous insulating layers 10 may be covered by a second interlayer insulating layer 13. The second interlayer insulating layer 13 may be formed of silicon oxide. The third via 12 may be provided in the second interlayer insulating layer 13. The third via 12 may include copper or tungsten.

[0033] The lower pads BP are disposed on the second interlayer insulating layer 13. The lower pads BP may include a first lower pad BP (R) and a second lower pad BP (D). Each lower pad BP may also be referred to as a "lower wiring". Each lower pad BP may have a first thickness TH1 in a vertical direction (e.g., a direction perpendicular to the uppermost surface of the substrate 1). The first thickness TH1 may be, for example, 0.1 micrometers (μm) to 1 μm. As the lower pads BP are downward in the vertical direction, each lower pad BP may have a wider width in a lateral direction (e.g., a direction parallel to the uppermost surface of the substrate 1). The lower surface of each lower pad BP may have a first width WT1 in the lateral direction. The distances between the lower pads BP in the lateral direction may be the same. In another example, the distance between the first lower pads BP (R) may be different from the distance between the second lower pads BP (D). The width of the first lower pad BP (R) may be different from the width of the second lower pad BP (D).

[0034] The actual electrical signal may be applied to the first lower pad BP (R). The dummy pattern of the second lower pad BP (D) may be electrically floating. Each second lower pad BP (D) may be a dummy pattern, a guard ring pattern, a broken dam pattern, or a test pattern. Each lower pad BP may include a first metal portion MP1 and a first anti-reflection layer AR1 stacked in sequence. The first metal portion MP1 may be formed of, for example, aluminum. The first anti-reflection layer AR1 may be formed as, for example, a single layer or multiple layers of at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

[0035] The lower pad BP and the second interlayer insulating layer 13 may be covered by a third interlayer insulating layer 20. The third interlayer insulating layer 20 may include a first silicon oxide layer 15, a hydrogen barrier layer 17, and a second silicon oxide layer 19 stacked in sequence. The hydrogen barrier layer 17 may be formed of, for example, silicon nitride. The first silicon oxide layer 15 may fill the space between the lower pads BP. The upper surface of the first silicon oxide layer 15 may have a concave-convex structure. The hydrogen barrier layer 17 may have a conformal thickness. The upper surface of the hydrogen barrier layer 17 may also have a concave-convex structure. The upper surface of the second silicon oxide layer 19 may be flat. The hydrogen barrier layer 17 may hinder / prevent hydrogen from diffusing into a transistor or a memory cell, thereby improving the reliability of the semiconductor chip.

[0036] The fourth interlayer insulating layer 21 is disposed on the third interlayer insulating layer 20. The fourth interlayer insulating layer 21 may have a single-layer or multi-layer structure of at least one of silicon oxide and silicon nitride. The fourth interlayer insulating layer 21 may have a flat upper surface.

[0037] The upper pad UP is disposed on the fourth interlayer insulating layer 21. The upper pad UP may have a second thickness TH2 in a vertical direction. The second thickness TH2 is greater than the first thickness TH1. The second thickness TH2 may be 2 to 5 times the first thickness TH1. The second thickness TH2 may be, for example, 2 μm to 2.5 μm.

[0038] The upper pad UP may include a conductive material. The upper pad UP may include a third metal portion MP3 and a third anti-reflection layer AR3 stacked in sequence. The third metal portion MP3 may be formed of, for example, aluminum. The third anti-reflection layer AR3 may be formed as, for example, a single layer or multiple layers of at least one of titanium, titanium nitride, tantalum, or tantalum nitride. As the upper pad UP goes downward, the upper pad UP may have a wider width.

[0039] The first path structure VST1 extends in the third interlayer insulating layer 20 and the fourth interlayer insulating layer 21 (e.g., penetrates the third interlayer insulating layer 20 and the fourth interlayer insulating layer 21) to electrically connect the first lower pad BP (R) to the upper pad UP. The first path structure VST1 may have a first height HE1 in the vertical direction. The first height HE1 is a vertical distance from the lowermost surface of the first path structure VST1 to the uppermost surface of the first path structure VST1. The first height HE1 may be equal to or greater than the second thickness TH2. The first height HE1 may be, for example, 1.0 μm to 10 μm. Therefore, the upper pad UP may be spaced apart from the first lower pad BP (R) by a specific (e.g., predetermined) distance, thereby reducing the parasitic capacitance between the first wirings 11 and improving the resistance-capacitance (RC) delay characteristics by applying a voltage to the upper pad UP.

[0040] A plurality of first via structures VST1 may be provided. Each first via structure VST1 may include a first via VA1, a first landing pad LP(R), and a second via VA2 stacked in sequence. The first via VA1 extends in the third interlayer insulating layer 20 (e.g., penetrates the third interlayer insulating layer 20) and contacts the first lower pad BP(R). The second via VA2 extends in the fourth interlayer insulating layer 21 (e.g., penetrates the fourth interlayer insulating layer 21) to electrically connect the first landing pad LP(R) to the upper pad UP. The second via VA2 may overlap the first landing pad LP(R) and the first via VA1 in the vertical direction. Therefore, the vertical axis may pass through the second via VA2, the first landing pad LP(R), and the first via VA1. The first via VA1 and the second via VA2 may include tungsten. The side surface and the lower surface of each of the first via VA1 and the second via VA2 may be covered by a diffusion barrier layer.

[0041] The second landing pad LP(D) may be disposed on the third interlayer insulating layer 20 in the second region ER. The second landing pad LP(D) may also be referred to as a "dummy pad". The second landing pad LP(D) may be a dummy pattern that is not electrically connected to any first via VA1 or second via VA2 of any first via structure VST1. The second landing pad LP(D) may hinder / prevent a load effect to help the first landing pad LP(R) to be accurately formed.

[0042] The first landing pad LP(R) and the second landing pad LP(D) may constitute a pad LP. As the landing pad LP goes downward, each landing pad LP may have a wider width. Each landing pad LP may include a second metal portion MP2 and a second anti-reflection layer AR2 stacked in sequence. The second metal portion MP2 may be formed of, for example, aluminum. The second anti-reflection layer AR2 may be formed of, for example, a single layer or multiple layers of at least one of titanium, titanium nitride, tantalum, or tantalum nitride. Each landing pad LP may have the same first thickness TH1 as the lower pad BP. Optionally, the thickness of each landing pad LP may be greater than the first thickness TH1. The lower surface of each landing pad LP may have a first width WT1 in the lateral direction.

[0043] The landing pads LP may be spaced apart from each other by the same first distance DS1 in the lateral direction. That is, the first landing pads LP(R) may be spaced apart from each other by the same first distance DS1. The second landing pads LP(D) may be spaced apart from each other by the same first distance DS1. Among the first landing pads LP(R), the outermost first landing pad LP(R1) closest to the second landing pad LP(D) may be spaced apart from the outermost second landing pad LP(D1) adjacent thereto by the first distance DS1. Therefore, the second landing pads LP(D) may be formed to have the same size and spacing distance as the first landing pads LP(R), thereby hindering / preventing the load effect. In another example, the distance between the first landing pads LP(R) may be different from the distance between the second landing pads LP(D). The width of the first landing pad LP(R) may be different from the width of the second landing pad LP(D).

[0044] The fourth interlayer insulating layer 21 and the upper pad UP may overlap (eg, be covered by) the upper passivation layer 23. The upper passivation layer 23 may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, SiCN, and polyimide.

[0045] The upper conductive bump CB may penetrate the upper passivation layer 23 and may contact the upper pad UP. The upper conductive bump CB may include copper. The solder layer SB is bonded on the upper conductive bump CB. The solder layer SB may include, for example, SnAg.

[0046] FIG. 2A to FIG. 2C A plan view of a landing pad and an upper pad according to an embodiment of the inventive concept is shown.

[0047] Reference Figure 1 and Figure 2A , the first landing pads LP(R) may have island (eg, circular) shapes spaced apart from each other.

[0048] Reference Figure 1 and Figure 2B , the first landing pads LP(R) may be electrically connected to each other to collectively have a grid (eg, perforated, rectangular) shape.

[0049] Optionally, refer to Figure 1 and Figure 2C , the first landing pads LP(R) may be electrically connected to each other and commonly have a plate (eg, non-perforated, rectangular) shape.

[0050] Figure 3 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0051] Reference Figure 3 , the semiconductor chip 101 according to this example may exclude (ie, omit) Figure 1 The second landing pad LP (D) of the other structures can be Figure 1 The same as those in .

[0052] Figure 4 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0053] Reference Figure 4 In the semiconductor chip 102 according to this example, the third interlayer insulating layer 20 may be formed of a single layer of silicon oxide (and therefore, the hydrogen barrier layer 17 may not be provided between the first silicon oxide layer 15 and the second silicon oxide layer 19). The fourth interlayer insulating layer 21 may also be formed of a single layer of silicon oxide, and no hydrogen barrier layer 17 may be provided therein. Figure 1 The third interlayer insulating layer 20 and the fourth interlayer insulating layer 21 may be formed of the same silicon oxide layer, so the interface therebetween may not be distinguished. The silicon oxide layer may have a lower dielectric constant than that of silicon nitride, Figure 4 The structure can reduce the parasitic capacitance between the upper pad UP and the lower pad BP, thereby improving the RC delay characteristic. Figure 3 Those that are the same / similar.

[0054] Figure 5 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0055] Reference Figure 5, in the semiconductor chip 103 according to the present example, the first via structure VST1 may exclude (i.e., omit) the first landing pad LP(R). In the present example, the first via structure VST1 includes only the first via VA1 and the second via VA2. The first via VA1 and the second via VA2 are in contact with each other. There may be no interface between the first via VA1 and the second via VA2. The first via VA1 and the second via VA2 may be formed integrally with each other. The first via VA1 and the second via VA2 may have a width that narrows downward in the lateral direction. A portion of the upper surface of the first via VA1 may protrude in the lateral direction beyond the lower surface of the second via VA2 and may vertically overlap with the fourth interlayer insulating layer 21 (e.g., covered by and / or in contact with the fourth interlayer insulating layer 21). Other structures may be similar to Figure 3 Those that are the same / similar.

[0056] Figure 6 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0057] Reference Figure 6 , the semiconductor chip 104 according to this example may further include a fifth interlayer insulating layer 25 interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23. The fifth interlayer insulating layer 25 may be formed of silicon oxide. The first path structure VST1 extends in the third to fifth interlayer insulating layers 20, 21 and 25 (for example, penetrates the third to fifth interlayer insulating layers 20, 21 and 25). The first path structure VST1 may not include a first landing pad LP (R). In this example, the first path structure VST1 includes a first path VA1, a second path VA2 and a third path VA3 stacked in sequence. The third path VA3 extends in the fifth interlayer insulating layer 25 (for example, penetrates the fifth interlayer insulating layer 25). The first path VA1 and the second path VA2 are in contact with each other. The second path VA2 and the third path VA3 are in contact with each other. There may be no interface between the first path VA1 and the second path VA2. There may be no interface between the second path VA2 and the third path VA3. The first path VA1, the second path VA2 and the third path VA3 may be formed integrally with each other. The first via VA1, the second via VA2, and the third via VA3 may have widths that narrow downward. A portion of an upper surface of the first via VA1 may vertically overlap with (e.g., be covered by) the fourth interlayer insulating layer 21. A portion of an upper surface of the second via VA2 may vertically overlap with (e.g., be covered by) the fifth interlayer insulating layer 25. Other structures may be similar to Figure 3 Those that are the same / similar.

[0058] Figure 7is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0059] Reference Figure 7 , the semiconductor chip 105 according to this example may further include a fifth interlayer insulating layer 25 interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23. The fifth interlayer insulating layer 25 may be formed of silicon oxide. The first path structure VST1 extends in the third to fifth interlayer insulating layers 20, 21 and 25 (for example, penetrates the third to fifth interlayer insulating layers 20, 21 and 25). In this example, the first path structure VST1 includes a first path VA1, a first landing pad LP (R), a second path VA2 and a third path VA3 stacked in sequence. The third path VA3 penetrates the fifth interlayer insulating layer 25. The second path VA2 and the third path VA3 are in contact with each other. There may be no interface between the second path VA2 and the third path VA3. The second path VA2 and the third path VA3 may be formed integrally with each other. The first path VA1, the second path VA2 and the third path VA3 may have a width that narrows downward. A portion of the upper surface of the second path VA2 may overlap vertically with the fifth interlayer insulating layer 25 (for example, covered by the fifth interlayer insulating layer 25). Other structures can be used with Figure 6 In this example, the first path structure VST1 includes paths of a three-level structure, but is not limited thereto, and may include paths of four or more levels.

[0060] In another example, the first via structure VST1 may further include a first landing pad LP(R) interposed between the second via VA2 and the third via VA3. Therefore, the first via structure VST1 may include a first via VA1, a first landing pad LP(R), a second via VA2, a first landing pad LP(R), and a third via VA3 stacked in sequence. Alternatively, the first via structure VST1 may include a first via VA1, a second via VA2, a first landing pad LP(R), and a third via VA3 stacked in sequence.

[0061] Figure 8 is a cross-sectional view of a semiconductor chip according to an embodiment of the inventive concept.

[0062] Reference Figure 8, the semiconductor chip 106 according to the present example further includes a first residual test pattern 11t, a first residual test path 9t, and a second residual test pattern TP. The first residual test pattern 11t and the first residual test path 9t may be disposed in the porous insulating layer 10 in the second region ER. The first residual test pattern 11t may have the same thickness and the same material as the first wiring 11. The first residual test path 9t may have the same thickness and the same material as the first path 9. The second residual test pattern TP may have the same first thickness TH1 as the lower pad BP. The first thickness TH1 may be less than the second thickness TH2 of the upper pad UP. The lower surface of the second residual test pattern TP may have a width WT2 wider than the first width WT1 of the lower surface of the lower pad BP in the lateral direction.

[0063] The second residual test pattern TP may include a first metal portion MP1 and a first anti-reflection layer AR1 sequentially stacked. The first metal portion MP1 may be formed of, for example, aluminum. The first anti-reflection layer AR1 may be formed of, for example, titanium nitride.

[0064] A portion of the upper surface of the second residual test pattern TP may be vertically overlapped with the third interlayer insulating layer 20, the fourth interlayer insulating layer 21, the cap layer 22, and the upper passivation layer 23 stacked in sequence (e.g., covered by the third interlayer insulating layer 20, the fourth interlayer insulating layer 21, the cap layer 22, and the upper passivation layer 23 stacked in sequence). Another portion of the upper surface of the second residual test pattern TP may be exposed. The sidewalls of the third interlayer insulating layer 20, the fourth interlayer insulating layer 21, the cap layer 22, and the upper passivation layer 23 may be aligned with each other. A groove 24 is formed in the porous insulating layer 10, the third interlayer insulating layer 20, and the fourth interlayer insulating layer 21 between the second residual test pattern TP and the lower pad BP.

[0065] The capping layer 22 may extend to cover the inner wall and bottom surface of the groove 24. The capping layer 22 may extend to be interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23, and may cover a portion of the upper surface and the side surface of the upper pad UP. The capping layer 22 may be formed of silicon oxide having a relatively higher density than that of the porous insulating layer 10. The capping layer 22 may penetrate the porous insulating layer 10 to hinder / prevent physical cracks or moisture from propagating from the outside of the semiconductor chip 106. A portion of the upper passivation layer 23 may be inserted into the groove 24 to fill the groove 24. Other structures may be the same as those described with reference to FIG. Figure 3 Same / similar to those described.

[0066] Fig. 9A is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. Fig. 9B yes Fig. 9A An enlarged view of portion “P2”.

[0067] Reference Figure 1 , Fig. 9A and Fig. 9B , the semiconductor package 1000 according to the present example may include a packaging substrate PS, a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300. The second semiconductor chip 200 and the third semiconductor chip 300 may be spaced apart from each other in the lateral direction and may be on the first semiconductor chip 100. The packaging substrate PS may be a printed circuit board. The packaging substrate PS may include an upper substrate pad PUP, a lower substrate pad PBP, and an internal substrate wiring IT electrically connecting them. The external connection terminal OSB may be bonded to the lower substrate pad PBP.

[0068] The first semiconductor chip 100 may be mounted on the package substrate PS using the first internal connection member IB1. An underfill layer UF may be interposed between the package substrate PS and the first semiconductor chip 100. The first semiconductor chip 100 may also be referred to as an "intermediary substrate" or an "intermediary chip". The first semiconductor chip 100 may have a Figure 1 When a portion “P1” of the first semiconductor chip 100 is enlarged, the first semiconductor chip 100 may be Figure 1 The first semiconductor chip 100 may have a reference Figures 2A to 8 Describes the structure of a semiconductor chip rather than Figure 1 The first semiconductor chip 100 may include upper conductive bumps CB, lower conductive bumps 46, and through vias TV electrically connecting them. The first semiconductor chip 100 may further include upper connection wirings CBT electrically connecting some of the upper conductive bumps CB.

[0069] The second and third semiconductor chips 200 and 300 are mounted on the first semiconductor chip 100 through second internal connection members IB2. An underfill layer UF may be interposed between the first and second semiconductor chips 100 and 200 and between the first and third semiconductor chips 100 and 300.

[0070] The bottom filling layer UF may be formed of a non-conductive film (NCF). The bottom filling layer UF may also be referred to as a "non-conductive layer". The bottom filling layer UF may independently include a thermosetting resin or a photocurable resin. In addition, the bottom filling layer UF may further include an organic filler or an inorganic filler independently of each other. The organic filler may include, for example, a polymer material. The inorganic filler may include, for example, silicon oxide (SiO 2 ).

[0071] The second semiconductor chip 200 may be selected from a system large-scale integration (LSI) chip, a logic circuit chip, a micro-electromechanical system (MEMS) device chip, or an application-specific integrated circuit (ASIC) chip. The third semiconductor chip 300 may be a high bandwidth memory (HBM) chip or a hybrid memory cube (HMC) chip. The second semiconductor chip 200 and the third semiconductor chip 300 may be electrically connected to each other through an upper connection wiring CBT.

[0072] The third semiconductor chip 300 may include a buffer die BF and first to fourth memory dies ME1 to ME4 stacked in sequence. The third semiconductor chip 300 may further include a mold layer MD. For example, the mold layer MD may include an insulating resin such as an epoxy molding compound (EMC). The mold layer MD may further include a filler, which may be dispersed in the insulating resin.

[0073] Each of the first to fourth memory dies ME1 to ME4 may be, for example, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip. The buffer die BF and each of the first to fourth memory dies ME1 to ME4 may have Fig. 9B The structure shown.

[0074] Specifically, refer to Fig. 9B , the buffer die BF and the first to fourth memory dies ME1 to ME4 may each have Figure 1 In order to describe the structure similar to Figure 1 Different from the structure in FIG. 1 , each of the buffer die BF and the first to fourth memory dies ME1 to ME4 does not include (ie, omits) the fourth interlayer insulating layer 21 and includes a second via structure VST2 electrically connecting the first lower pad BP(R) and the upper pad UP.

[0075] The second via structure VST2 has a second height HE2 in the vertical direction. The second height HE2 is a vertical distance from the lowermost surface of the second via structure VST2 to the uppermost surface of the second via structure VST2. The second height HE2 may be equal to or less than the second thickness TH2 of the upper pad UP. The second height HE2 may be less than the thickness of the upper pad UP of the first semiconductor chip 100. Figure 1 The first height HE1 of the first via structure VST1 is 44. The lower conductive bump 46 may be disposed in the lower passivation layer 40, and the lower surface of the lower conductive bump 46 may be coplanar with the lower surface of the lower passivation layer 40. The upper surface of the upper conductive bump CB may be coplanar with the upper surface of the upper passivation layer 23. Other structures may be the same as those described in reference. Figure 1 Same / similar to those described.

[0076] The buffer die BF and the first to fourth memory dies ME1 to ME4 may each be bonded to each other using a Cu-to-Cu bonding manner. That is, the upper conductive bumps CB of the lower one of the first to fourth memory dies ME1 to ME4 and the buffer die BF may contact the lower conductive bumps 46 of the buffer die BF and the upper one of the first to fourth memory dies ME1 to ME4.

[0077] In the semiconductor package 1000 according to the inventive concept, the first height HE1 of the first via structure VST1 in the first semiconductor chip 100 corresponding to the interposer chip may be 1.0 μm to 10 μm. When the interposer chip is used to test the performance of the third semiconductor chip 300 as an HBM chip, the resistance capacitance (RC) delay characteristic may be improved.

[0078] The heat dissipation member HS may be disposed on the second semiconductor chip 200 and the third semiconductor chip 300. The heat dissipation member HS may be a material having excellent thermal conductivity and may include, for example, a metal. A thermal boundary material layer TM may be interposed between the heat dissipation member HS and the second semiconductor chip 200 and between the heat dissipation member HS and the third semiconductor chip 300. The thermal boundary material layer TM may include a thermosetting resin layer. The thermal boundary material layer TM may further include filler particles dispersed in the thermosetting resin layer. The filler particles may include at least one of disiloxane, aluminum oxide, zinc oxide, and boron nitrogen.

[0079] FIG. 10A to FIG. 10G It is shown in sequence that the manufacturing Figure 1 A view of a method of manufacturing a semiconductor chip.

[0080] Reference Fig. 10A , a transistor TR, a first interlayer insulating layer 3, a first contact 5c, a second contact 5g, a first wiring 11, a first via 9, a second wiring 11g, a second via 9g, a porous insulating layer 10, a through via TV, a via insulating layer TL, a third via 12, and a second interlayer insulating layer 13 are formed on a substrate 1 using a typical process. After a first metal layer and a preliminary first anti-reflective layer are sequentially deposited on the second interlayer insulating layer 13, an etching process is performed to form a lower pad BP.

[0081] Reference Fig. 10B A first silicon oxide layer 15, a hydrogen barrier layer 17, and a second silicon oxide layer 19 are sequentially deposited on the lower pad BP to form a third interlayer insulating layer 20. A chemical mechanical polishing (CMP) process is performed to planarize an upper surface of the second silicon oxide layer 19.

[0082] Reference Fig. 10C, a first via hole is formed in the third interlayer insulating layer 20 . A conductive layer is deposited on the third interlayer insulating layer 20 to fill the first via hole, and an etch-back or CMP process is performed to form a first via VA1 in the third interlayer insulating layer 20 .

[0083] Reference Fig. 10D , a second metal layer and a preliminary second anti-reflection layer are sequentially deposited on the third interlayer insulating layer 20, and the second metal layer and the second anti-reflection layer AR2 are etched to form a landing pad LP. In this case, the first landing pad LP(R) and the second landing pad LP(D) can be formed at the same time. By reducing / minimizing the load effect by using the second landing pad LP(D), the first landing pad LP(R) can be formed without defects.

[0084] Reference Fig. 10E , a fourth interlayer insulating layer 21 is formed on the third interlayer insulating layer 20. The upper surface of the fourth interlayer insulating layer 21 may be planarized by performing a CMP process. A second via VA2 is formed in the fourth interlayer insulating layer 21. As a result, a first via structure VST1 may be formed.

[0085] Reference Fig.10F , a third metal layer and a preliminary third anti-reflection layer are sequentially deposited on the fourth interlayer insulating layer 21 , and then the third metal layer and the third anti-reflection layer AR3 are etched to form an upper pad UP.

[0086] Reference Figure 10G An upper passivation layer 23 is formed to cover the fourth interlayer insulating layer 21 and the upper pad UP. The upper passivation layer 23 is etched to form a hole HL exposing the upper pad UP. A conductive bump CB is formed in the hole HL, and a solder layer SB is formed on the conductive bump CB.

[0087] Then, refer to Figure 1 , a back grinding process is performed on the rear surface of the substrate 1 to expose the through via TV. A lower passivation layer 40 and a lower conductive bump 46 are formed on the rear surface of the substrate 1. Thus, it is possible to manufacture Figure 1 A semiconductor chip 100 is provided.

[0088] In the semiconductor chip according to the embodiment of the inventive concept, the via structure electrically connecting the lower pad and the upper pad can have a height greater than the thickness of the upper pad, thereby improving the RC delay characteristics. In addition, when the interposer chip having the above structure is used to test the HBM chip, it can be very effective in improving the RC delay characteristics.

[0089] Although the exemplary embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept are to be considered in all respects as illustrative and not restrictive, and the scope of the inventive concept is indicated by the appended claims. Figures 1 to 9B The embodiments of the present invention may be combined with each other.

[0090] Citation of Related Applications

[0091] This application claims the priority of Korean Patent Application No. 10-2023-0143183 filed on October 24, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor chip, comprising: substrate; A first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer are sequentially stacked on the substrate; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; A third interlayer insulating layer and a fourth interlayer insulating layer are sequentially stacked on the lower pad and the second interlayer insulating layer; an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction that is greater than the first thickness; as well as a via structure in both the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pad and the upper pad, Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping with the first via in the vertical direction.

2. The semiconductor chip according to claim 1, wherein: Each of the via structures has a height in the vertical direction that is 1.0 μm to 10 μm greater than the second thickness.

3. The semiconductor chip according to claim 1, wherein: Each of the via structures further includes a landing pad interposed between the first via and the second via.

4. The semiconductor chip according to claim 3, in, The landing pads of the via structure are spaced apart from each other and have a circular shape, or The landing pads of the via structure are electrically connected to each other to have a perforated or non-perforated rectangular shape.

5. The semiconductor chip according to claim 3, further comprising a dummy pad on the third interlayer insulating layer and spaced apart from the landing pad, in, The dummy pad is not electrically connected to the first via and the second via of any of the via structures.

6. The semiconductor chip according to claim 5, wherein: A first distance between the landing pads in the lateral direction is equal to a second distance between the dummy pads in the lateral direction.

7. The semiconductor chip according to claim 6, in, The landing pad includes an outermost landing pad adjacent to the dummy pad, The dummy pads include outermost dummy pads adjacent to the outermost landing pads, and Wherein, a third distance between the outermost landing pad and the outermost dummy pad in the transverse direction is equal to the first distance.

8. The semiconductor chip according to claim 6, wherein: A first width of each of the landing pads in the lateral direction is equal to a second width of each of the dummy pads in the lateral direction.

9. The semiconductor chip according to claim 1, in, The third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer stacked in sequence, and The first via is in the first silicon oxide layer, the hydrogen barrier layer and the second silicon oxide layer.

10. The semiconductor chip according to claim 1, in, the second passage is in contact with the first passage, wherein a lower width of each of the first passage and the second passage in a lateral direction is narrower than an upper width of each of the first passage and the second passage in the lateral direction, wherein a portion of the upper surface of the first passage protrudes beyond the lower surface of the second passage in the lateral direction, and Wherein, the fourth interlayer insulating layer is on the portion of the upper surface of the first via.

11. The semiconductor chip according to claim 1, wherein: Each of the via structures further comprises a third via on the second via.

12. The semiconductor chip according to claim 11, in, Each of the via structures further includes a landing pad, and The landing pad is between the first via and the second via, or between the second via and the third via.

13. The semiconductor chip according to claim 1, further comprising: wiring in the porous insulating layer; a first residual test pattern in the porous insulating layer and spaced apart from the wiring in a lateral direction; as well as a second residual test pattern on the second interlayer insulating layer, electrically connected to the first residual test pattern, and spaced apart from the lower pad in the lateral direction, wherein the second residual test pattern has the first thickness, and Wherein, the width of the second residual test pattern in the lateral direction is greater than the width of each of the lower pads in the lateral direction.

14. The semiconductor chip according to claim 13, further comprising: a capping layer on the fourth interlayer insulating layer and on a side surface and an upper surface of the upper pad; as well as a passivation layer, on the cap layer, Part of the cap layer is in the fourth interlayer insulating layer, the third interlayer insulating layer, the second interlayer insulating layer, and the porous insulating layer, and is in contact with the first interlayer insulating layer. 15 . The semiconductor chip of claim 14 , further comprising a conductive bump in the passivation layer and the capping layer and in contact with the upper pad.

16. A semiconductor chip, comprising: substrate; A first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer are sequentially stacked on the substrate; a through via in the first interlayer insulating layer and the substrate; a via insulating layer interposed between the through via and the substrate; wiring in the porous insulating layer; a contact plug in the first interlayer insulating layer and in contact with one of the wirings; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; A third interlayer insulating layer and a fourth interlayer insulating layer are sequentially stacked on the lower pad and the second interlayer insulating layer; an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction that is greater than the first thickness; as well as a via structure in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pad and the upper pad, The third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer stacked in sequence. wherein each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping with the first via in the vertical direction, and Wherein, each of the via structures has a height in the vertical direction of 1.0 micrometer to 10 micrometers.

17. A semiconductor package, comprising: Package substrate; A first semiconductor chip, on the packaging substrate; as well as a second semiconductor chip and a third semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip and the third semiconductor chip are spaced apart from each other in a lateral direction, The third semiconductor chip includes a buffer die and a memory die stacked in sequence. Wherein, the first semiconductor chip and the memory die each include: substrate; A first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer are sequentially stacked on the substrate; a lower pad on the second interlayer insulating layer and having a first thickness in a vertical direction; a third interlayer insulating layer, on the lower pad and the second interlayer insulating layer; an upper pad on the third interlayer insulating layer and having a second thickness in the vertical direction that is greater than the first thickness; and a via structure, passing through the third interlayer insulating layer to electrically connect the lower pad and the upper pad, wherein each of the via structures of the first semiconductor chip has a first height in the vertical direction, and Each of the via structures of the memory die has a second height in the vertical direction that is smaller than the first height.

18. The semiconductor package according to claim 17, wherein: The first height is 1.0 micrometer to 10 micrometers.

19. The semiconductor package according to claim 17, wherein: Each of the via structures of the first semiconductor chip includes a first via and a second via stacked in sequence.

20. The semiconductor package according to claim 19, wherein Each of the via structures of the first semiconductor chip further includes a landing pad between the first via and the second via.

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