Semiconductor package

Abstract

A semiconductor package includes: a redistribution structure including a first surface and a second surface; and a semiconductor chip located on the first surface of the redistribution structure. The redistribution structure includes: a plurality of first conductive lines, the plurality of first conductive lines having first signal lines; and a plurality of second conductive lines at a vertical height different from that of the plurality of first conductive lines. The plurality of second conductive lines includes a ground line electrically insulated from the first signal line. The ground line includes: an opening extending through the ground line at a position vertically overlapping the first signal line; and the ventilation hole is communicated with the first end part of the opening. The first end portion of the opening has a first width in a first horizontal direction. The ventilation hole has a second width smaller than the first width in the first horizontal direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages. Background Art

[0002] With the rapid development of the electronics industry and the needs of users, electronic devices are becoming smaller and lighter, and therefore, semiconductor devices, which are core components of electronic devices, are required to be highly integrated. Semiconductor packages with connection terminals that ensure connection reliability have been designed for highly integrated semiconductor chips with an increased number of input / output (I / O) connection terminals. For example, fan-out semiconductor packages such as fan-out panel-level packages have been developed to increase the gap between the connection terminals in order to prevent interference between the connection terminals. Summary of the invention

[0003] The present disclosure relates to a semiconductor package, a semiconductor package including a redistribution structure with improved reliability, and a semiconductor package capable of simplifying a process of forming a redistribution structure. For example, the present disclosure relates to a fan-out panel level package (FOPLP).

[0004] In some implementations, a semiconductor package includes: a redistribution structure, the redistribution structure including a first surface and a second surface; and a semiconductor chip, the semiconductor chip being located on the first surface of the redistribution structure, wherein the redistribution structure includes: a plurality of first conductive lines, the plurality of first conductive lines including a first signal line; and a plurality of second conductive lines, the plurality of second conductive lines being arranged at a vertical height different from a vertical height of the plurality of first conductive lines and including a grounding line electrically insulated from the first signal line, wherein the grounding line includes: an opening, the opening extending through the grounding line at a position vertically overlapping the first signal line and including a first end having a first width in a first horizontal direction; and a ventilation hole, the ventilation hole being connected to the first end of the opening and having a second width in the first horizontal direction that is less than the first width.

[0005] In some implementations, a semiconductor package includes: a redistribution structure, the redistribution structure including a first surface and a second surface; a semiconductor chip, the semiconductor chip is located on the first surface of the redistribution structure; and an external connection terminal, the external connection terminal is located on the second surface of the redistribution structure, wherein the redistribution structure includes: a plurality of first conductive lines, the plurality of first conductive lines are located at a first vertical height lower than the vertical height of the first surface of the redistribution structure; a first redistribution insulating layer, the first redistribution insulating layer covering a plurality of bottom surfaces of the plurality of first conductive lines; a plurality of second conductive lines, the plurality of second conductive lines are located on the bottom surface of the first redistribution insulating layer and are at a second vertical height lower than the first vertical height; and a second redistribution insulating layer, the second redistribution insulating layer is located on the bottom surface of the first redistribution insulating layer and covers a plurality of bottom surfaces of the plurality of second conductive lines, wherein at least one second conductive line among the plurality of second conductive lines includes: an opening, the opening extending through the at least one second conductive line and including a first end having a first width in a first horizontal direction; and a ventilation hole, the ventilation hole being connected to the first end of the opening and having a second width less than the first width of the opening.

[0006] In some implementations, a semiconductor package includes: a first redistribution structure; a semiconductor chip, the semiconductor chip is located on a top surface of the first redistribution structure; a connection structure, the connection structure is located on the top surface of the first redistribution structure and is located on at least one side of the semiconductor chip; a second redistribution structure, the second redistribution structure is located on the semiconductor chip and the connection structure; and a solder ball, the solder ball is arranged on a bottom surface of the first redistribution structure, wherein the first redistribution structure includes: a plurality of first conductive lines, the plurality of first conductive lines including a first signal line; a first redistribution insulating layer, the first redistribution insulating layer covers the plurality of first conductive lines and includes a first photosensitive polymer; a plurality of second conductive lines , the plurality of second conductive lines are at a lower vertical height than the plurality of first conductive lines and include a ground line electrically insulated from the first signal line; and a second redistribution insulating layer, the second redistribution insulating layer covers the plurality of second conductive lines and includes a second photosensitive polymer, wherein the ground line includes: an opening, the opening extending through the ground line at a position vertically overlapping with the first signal line and including a first end having a first width in a first horizontal direction; and a ventilation hole, the ventilation hole being connected to the first end of the opening and having a second width less than the first width in the first horizontal direction, wherein the ground line includes a paired signal line pattern, and the opening vertically overlaps with the paired signal line pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The implementation of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1 is a cross-sectional view illustrating an example of a semiconductor package.

[0009] Figure 2 yes Figure 1 An example enlarged view of portion A of FIG.

[0010] Figures 3 to 11 1 and 2 are plan views illustrating examples of various plan shapes of a second ground line included in a semiconductor package.

[0011] Fig. 12A and Fig. 12B is an example graph illustrating the frequency of defects occurring in semiconductor packages.

[0012] Fig.13 is a cross-sectional view illustrating an example of a semiconductor package.

[0013] Figures 14 to 18 , FIG. 19A to FIG. 19E and Fig. 20 is a schematic cross-sectional view illustrating an example of a method of manufacturing a semiconductor package.

[0014] Specific implementation method

[0015] Hereinafter, implementations of the present disclosure will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 is a cross-sectional view illustrating an example of the semiconductor package 1 . Figure 2 yes Figure 1 An example enlarged view of portion A of FIG. Figures 3 to 11 1 is a plan view illustrating examples of various planar shapes of the second ground line GL2_G included in the semiconductor package 1 .

[0017] refer to Figures 1 to 11 , the semiconductor package 1 may include a semiconductor chip 100, a first redistribution structure 200, a connection structure 300, and a second redistribution structure 400. The semiconductor chip 100 may be arranged on the first redistribution structure 200, the connection structure 300 may be arranged on the first redistribution structure 200 to surround the semiconductor chip 100, and the second redistribution structure 400 may be arranged on the semiconductor chip 100 and the connection structure 300. The connection structure 300 may electrically connect the first redistribution structure 200 and the second redistribution structure 400 to each other. The semiconductor package 1 may be a fan-out panel level package (FOPLP).

[0018] In some implementations, the first redistribution structure 200 and the second redistribution structure 400 may be formed by a redistribution process. In some implementations, the semiconductor package 1 may be formed in a chip-first manner by first forming the connection structure 300 and the semiconductor chip 100 and then forming the first redistribution structure 200 and the second redistribution structure 400.

[0019] The first redistribution structure 200 may include a first redistribution insulation layer 210 and a plurality of first redistribution patterns 220. The first redistribution insulation layer 210 may be arranged to surround the plurality of first redistribution patterns 220. In some implementations, the first redistribution structure 200 may include a plurality of first redistribution insulation layers 210 stacked.

[0020] In some implementations, the first redistribution insulating layer 210 may include a photosensitive polymer. For example, the first redistribution insulating layer 210 may be formed of a photoimageable dielectric (PID) or a photosensitive polyimide (PSPI), or may be formed of a buildup film such as an Ajinomoto buildup film (ABF).

[0021] The plurality of first redistribution patterns 220 may include a plurality of first redistribution line patterns 222, a plurality of first redistribution paths 224, and a plurality of first redistribution seed layers 226. The plurality of first redistribution patterns 220 may be, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc., or a metal alloy thereof, but is not limited thereto. In some implementations, the first redistribution line patterns 222 and the first redistribution paths 224 may be made of the same material, and the first redistribution seed layer 226 may be made of a material different from both the first redistribution line patterns 222 and the first redistribution paths 224. In some implementations, the first redistribution line patterns 222 and the first redistribution paths 224 may include copper or a copper alloy, and the first redistribution seed layer 226 may include titanium or titanium nitride.

[0022] The plurality of first redistribution vias 224 may pass through at least one first redistribution insulating layer 210 to be respectively connected to some of the plurality of first redistribution line patterns 222. In some implementations, each of the plurality of first redistribution vias 224 may have a tapered shape extending from the lower side to the upper side with a narrower horizontal width. For example, the plurality of first redistribution vias 224 may have a wider horizontal width in a direction away from at least one semiconductor chip 100.

[0023] In some implementations, at least some of the plurality of first redistribution line patterns 222 may be integrally formed with some of the plurality of first redistribution vias 224. For example, the first redistribution line patterns 222 and the first redistribution vias 224 contacting the top surface of the first redistribution line pattern 222 (i.e., the first redistribution vias 224 extending from the top surface of the first redistribution line pattern 222) may be formed together to be integrated with each other. For example, each of the plurality of first redistribution vias 224 may have a narrower horizontal width while being away from the integrated first redistribution line pattern 222. The first redistribution seed layer 226 may cover the first redistribution line patterns 222 and the first redistribution vias 224 that are integrated with each other.

[0024] In some implementations, the plurality of first redistribution line patterns 220 may include a plurality of first conductive lines CL1 arranged at a first vertical height LV1, a plurality of second conductive lines CL2 arranged at a second vertical height LV2 lower than the plurality of first conductive lines CL1, and a plurality of third conductive lines CL3 arranged at a third vertical height LV3 lower than the plurality of second conductive lines CL2.

[0025] Here, the first vertical height LV1 may indicate a height lower than the top surface of the first redistribution structure 200. In addition, the second vertical height LV2 may indicate a height lower than the top surface of the first redistribution structure 200, and a vertical distance from the semiconductor chip 100 to the second vertical height LV2 may be greater than a vertical distance from the semiconductor chip 100 to the first vertical height LV1. In addition, the third vertical height LV3 may indicate a height lower than the top surface of the first redistribution structure 200, and a vertical distance from the semiconductor chip 100 to the third vertical height LV3 may be greater than a vertical distance from the semiconductor chip 100 to the second vertical height LV2.

[0026] The plurality of first conductive lines CL1 may include first signal lines CL1_S. The first signal lines CL1_S may include line patterns for supplying signals to the semiconductor chip 100. In some implementations, the first signal lines CL1_S may be composed of lines of various widths and shapes designed for supplying high-speed signals to the semiconductor chip 100.

[0027] In some implementations, such as Figure 3As shown, the first signal line CL1_S may include a pair of signal line patterns SP1 and SP2. The pair of signal line patterns SP1 and SP2 may be arranged to be spaced apart from each other along a first horizontal direction at a first vertical height, and may extend parallel to each other. In some implementations, the pair of signal line patterns SP1 and SP2 may include a differential signal pair for transmitting high-speed signals to the semiconductor chip 100. For example, the pair of signal line patterns SP1 and SP2 may include a power line pair for all signals (including clock pairs, data, commands, addresses, etc.) sent to the semiconductor chip 100 as differential signal pairs. In some implementations, as Figure 4 As shown, the first signal line CL1_S may include a single signal line pattern instead of the pair of signal line patterns SP1 and SP2. In some implementations, the first signal line CL1_S may include a single signal line pattern in addition to the pair of signal line patterns SP1 and SP2.

[0028] The plurality of first conductive lines CL1 may further include a first ground line CL1_G and a first redistribution line CL1_R. The first ground line CL1_G and the first redistribution line CL1_R may be arranged to be spaced apart from the first signal line CL1_S along the first horizontal direction at a first vertical height LV1. For example, the first ground line CL1_G may be configured such that a ground voltage is applied thereto, and the first redistribution line CL1_R may be configured such that a power supply voltage or other signal voltage is applied thereto.

[0029] The plurality of second conductive lines CL2 may include a second ground line CL2_G. The second ground line CL2_G may be arranged at a second vertical height LV2. The second ground line CL2_G may include an opening Op penetrating the inside of the second ground line CL2_G, and the opening Op may be arranged at a position vertically overlapping with the first signal line CL1_S. For example, the opening Op may be arranged at a position vertically overlapping with the paired signal line patterns SP1 and SP2 of the first signal line CL1_S. Figure 3 As shown, the opening Op may have a circular or elliptical planar shape, and the opening Op may be arranged at a position corresponding to the pair of signal line patterns SP1 and SP2 (represented by Figure 3 The dotted lines in the figure indicate where the vertical overlap occurs.

[0030] A ventilation hole Vh may be arranged in the first end E1 of the opening Op. The ventilation hole Vh may penetrate the inside of the second ground line CL2_G and may be connected to the first end E1 of the opening Op. A portion of the first redistribution insulating layer 210 may be filled in the opening Op and the ventilation hole Vh. In the operation of filling the first redistribution insulating layer 210 inside the opening Op through a coating process, the ventilation hole Vh may serve as a degassing path of the opening Op, and therefore, air stagnation in the opening Op may be minimized or prevented.

[0031] In some implementations, the first redistribution insulating layer 210 may be formed by applying or coating a viscous photopolymer material on the first redistribution line pattern 220 and curing the photopolymer material through a subsequent curing process. On the sidewall of the opening Op, a step may appear due to the relatively large height of the first redistribution line pattern 220, and the inside of the opening Op is not completely filled with the photopolymer material, and air may be trapped, so that the air may remain in the photopolymer material. In this case, defects may occur when forming the subsequent first redistribution line pattern 220. However, a ventilation hole Vh is provided at the first end E1 of the opening Op, and therefore, air can be minimized or prevented from being trapped inside the opening Op.

[0032] In some implementations, the width of the ventilation hole Vh may be narrower than the first end E1 of the opening Op. The first end E1 of the opening Op may have a first width w11 in the first horizontal direction X, and the ventilation hole Vh may have a second width w21 in the first horizontal direction X, and the second width w21 may be smaller than the first width w11.

[0033] For example, when the opening Op has Figure 3 In the circular horizontal cross-section shown, the first width w11 may correspond to the maximum width of the opening Op, such as the diameter of the opening Op. The second width w21 of the ventilation hole Vh may indicate the width of a portion of the ventilation hole Vh that communicates with the first end E1 of the opening Op and is arranged adjacent to the first end E1 of the opening Op.

[0034] In some implementations, the first width w11 may range from about 50 micrometers to about 1000 micrometers, but is not limited thereto. In some implementations, the second width w21 may range from about 15% to about 30% of the first width w11. For example, when the second width w21 is less than about 15% of the first width w11, there is no degassing effect from the opening Op, and when the second width w21 is greater than about 30% of the first width w11, the amount of residual air trapped in the vent hole Vh increases, so that the total amount of bubbles reduced may not be large.

[0035] In some implementations, the ventilation hole Vh may have a third width w22 in the second horizontal direction Y intersecting the first horizontal direction X, and the third width w22 may be about 50% or more of the second width w21. For example, when the third width w22 of the ventilation hole Vh in the second horizontal direction Y is less than about 50% of the second width w21 in the first horizontal direction X, it may be difficult to fully discharge the air in the opening Op through the ventilation hole Vh.

[0036] In some implementations, the plane cross-sectional area of ​​the ventilation hole Vh may be in the range of about 5% to about 30% of the plane cross-sectional area of ​​the opening Op. When the plane cross-sectional area of ​​the ventilation hole Vh is less than about 5% of the plane cross-sectional area of ​​the opening Op, the degassing effect of the opening Op may not be fully achieved. When the plane cross-sectional area of ​​the ventilation hole Vh is greater than about 30% of the plane cross-sectional area of ​​the opening Op, the amount of residual air retained in the ventilation hole Vh increases instead, so that the total amount of bubbles reduced may not be large.

[0037] In some implementations, the vent hole Vh may be arranged to communicate with the first end E1 of the opening Op, and the first end E1 of the opening Op may indicate a portion of the opening Op that is last filled with the photosensitive polymer material in a process of applying or coating the photosensitive polymer material. Figure 3 As shown, the opening Op may include a first end E1 and a second end E2 opposite to the first end E1 , and the photosensitive polymer material may be coated or applied along a coating direction D_coat from the second end E2 of the opening Op toward the first end E1 thereof.

[0038] The ventilation hole Vh is connected to the first end E1 of the opening Op where the photosensitive polymer material finally fills the opening Op along the coating direction D_coat, so that the photosensitive polymer material completely fills the interior of the opening Op without leaving any air, all the air is discharged through the ventilation hole Vh, and the interior of the ventilation hole Vh can also be completely filled with the photosensitive polymer material, or only a small amount of air can remain inside the ventilation hole Vh.

[0039] In some implementations, such as Figure 3 As shown, the opening Op may be circular or elliptical in plan, and the vent hole Vh may be elliptical or semicircular in plan. Figure 5 As shown, the ventilation hole Vh can be in a square or rectangular planar shape. In some implementations, such as Figure 6 As shown, the ventilation hole Vh may be in a triangular planar shape.

[0040] In some implementations, such as Figure 7As shown, the opening Op may be rectangular or rounded rectangular in plan, and the vent hole Vh may be square or rectangular in plan. Figure 8 As shown, the opening Op may have a rectangular or rounded rectangular plan shape, and the ventilation hole Vh may have a triangular plan shape. In some implementations, the ventilation hole Vh may have a polygonal or rounded polygonal plan shape.

[0041] In some implementations, the opening Op may be as follows: Fig. 9 The irregular plane shape shown.

[0042] The first signal line CL1_S may include a pair of signal line patterns SP1 and SP2, and each of the pair of signal line patterns SP1 and SP2 may have a planar shape including a first line portion extending in a first direction, a second line portion extending in a second direction and connected to the first line portion, and an inflection point portion located between the first line portion and the second line portion.

[0043] In some implementations, such as Fig. 9 As shown, the opening Op may be arranged to surround the first signal line CL1_S when viewed in a plan view. For example, the sidewall of the opening Op may surround the first signal line CL1_S and may be arranged to be spaced apart from the first signal line CL1_S along the first horizontal direction. The opening Op may have a planar shape including a first portion Op_1 extending in a first direction and a second portion Op_2 extending in a second direction and communicating with the first portion Op_1. A bent portion Op_b may be formed between the first portion Op_1 and the second portion Op_2.

[0044] In such Fig. 9 In some implementations shown, the ventilation hole Vh may have an elliptical or semicircular plan shape, but in some implementations, the ventilation hole Vh may have a square, rectangular, or triangular plan shape.

[0045] In some implementations, a plurality of ventilation holes Vh may be formed to communicate with one opening Op. Fig.10 As shown, the opening Op may have a circular or elliptical planar shape, and the first ventilation hole Vh1 and the second ventilation hole Vh2 each having an elliptical or semicircular planar shape may be arranged to be spaced apart from each other so as to communicate with the first end E1 of the opening Op. Fig.11 As shown, the opening Op may have a rectangular or rounded rectangular plan shape, and the first, second, and third ventilation holes Vh1, Vh2, and Vh3, each having a rectangular or rounded rectangular plan shape, may be arranged to be spaced apart from each other so as to communicate with the first end E1 of the opening Op.

[0046] Despite Figures 3 to 11 , the opening Op and the vent hole Vh having various planar shapes are illustrated, but the shapes of the opening Op and the vent hole Vh according to the present disclosure are not limited thereto. It should be understood that the opening Op may have various structures and irregular planar shapes in a closed loop shape, and the vent hole Vh may have various structures and irregular planar shapes connected to one end of the opening Op and having a narrower width than the opening Op.

[0047] Return to reference Figure 1 The plurality of second conductive lines CL2 may further include second redistribution lines CL2_R. The second redistribution lines CL2_R may be electrically connected to the first redistribution lines CL1_R.

[0048] The plurality of third conductive lines CL3 may further include a third signal line CL3_S and a third redistribution line CL3_R. The third redistribution line CL3_R may be electrically connected to the second redistribution line CL2_R. In some implementations, the third signal line CL3_S may be arranged to vertically overlap with the opening Op of the second ground line CL2_G. In this case, the third signal line CL3_S may vertically overlap with a portion of the first redistribution insulating layer 210 that fills the inside of the opening Op of the second ground line CL2_G. In some implementations, the third signal line CL3_S may be arranged at a position that does not vertically overlap with the opening Op of the second ground line CL2_G.

[0049] exist Figure 1 In the embodiment, a three-layer wiring layer structure has been illustrated, in which the first redistribution structure 200 includes a plurality of first conductive lines CL1, a plurality of second conductive lines CL2, and a plurality of third conductive lines CL3, but in some implementations, the first redistribution structure 200 may have a four-layer wiring layer structure or a five-layer wiring layer structure, and, for example, a plurality of fourth conductive lines or a plurality of fifth conductive lines may be further formed at a vertical height lower than the third vertical height LV3. When the first redistribution structure 200 has a four-layer wiring layer structure or a five-layer wiring layer structure, at least one of the plurality of fourth conductive lines or the plurality of fifth conductive lines may include an additional ground line having an opening. The additional ground line may include a plurality of ground lines having an opening such as Figures 3 to 11 Various planar shapes of openings Op and vent holes Vh are shown.

[0050] The first redistribution structure 200 may further include a plurality of bottom surface connection pads 230 arranged on the bottom surface of the first redistribution structure 200. Each of the plurality of bottom surface connection pads 230 may be connected to the bottom surface of the first redistribution line pattern 222. The plurality of bottom surface connection pads 230 may include nickel (Ni) or gold (Au). A plurality of external connection terminals 500 may be attached to the plurality of bottom surface connection pads 230. The plurality of external connection terminals 500 may connect the semiconductor package 1 to the outside. The plurality of external connection terminals 500 may include solder balls or solder bumps.

[0051] The semiconductor chip 100 may be attached on the first redistribution structure 200. The semiconductor chip 100 may be mounted on the first redistribution structure 200 in a flip-chip manner. The semiconductor chip 100 may be electrically connected to the redistribution line pattern 220 of the first redistribution structure 200 through the lower chip pad 110.

[0052] In some implementations, the semiconductor chip 100 may be a memory chip or a logic chip. For example, the memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a NAND flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In addition, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.

[0053] The connection structure 300 may have a mounting space 300G in which the semiconductor chip 100 is arranged, and may include a base layer 310 and a plurality of connection paths 320. The plurality of connection paths 320 may penetrate the base layer 310. The connection structure 300 may be a printed circuit board (PCB), a ceramic substrate, a wafer for manufacturing a package, or a built-in layer. The connection structure 300 may include two or more stacked base layers 310, but may include a single base layer 310 in some implementations. For example, the connection structure 300 may be a multilayer printed circuit board.

[0054] The base layer 310 may be formed of at least one material selected from phenolic resin, epoxy resin, and polyimide. The base layer 310 may include at least one material selected from frame flame retardant 4 (FR-4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene ether, bismaleimide triazine (BT), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0055] In some implementations, the plurality of connection vias 320 may include an electrolytically deposited (ED) copper foil, a rolled annealed (RA) copper foil, a stainless steel foil, an aluminum foil, an ultra-thin copper foil, sputtered copper, a copper alloy, etc. Each of the plurality of connection vias 320 may include a via portion 322 penetrating the base layer 310 and a connection pattern portion 324 disposed on the top surface of the base layer 310 and integrally connected to the via portion 322.

[0056] The semiconductor package 1 may further include a filling insulating layer 330 that fills the mounting space 300G. The filling insulating layer 330 may fill the space between the semiconductor chip 100 and the base layer 310 arranged in the mounting space 300G. For example, the filling insulating layer 330 may be formed of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler (particularly Ajinomoto stacked film (ABF), FR-4, BT, etc.). Alternatively, the filling insulating layer 330 may be formed of a molding material such as EMC or a photosensitive material such as a photosensitive encapsulant (PIE). In some implementations, a portion of the filling insulating layer 330 may be formed of an insulating material such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0057] The second redistribution structure 400 may include a second redistribution insulation layer 410 and a plurality of second redistribution patterns 420. The plurality of second redistribution patterns 420 may include a plurality of second redistribution line patterns, a plurality of second redistribution vias, and a plurality of second redistribution seed layers. The second redistribution insulation layer 410 and the plurality of second redistribution patterns 420 included in the second redistribution structure 400 are substantially similar to the first redistribution insulation layer 210 and the plurality of first redistribution patterns 220 included in the first redistribution structure 200, and redundant description may be omitted.

[0058] The second redistribution structure 400 may further include a plurality of top surface connection pads 430 arranged on a top surface of the second redistribution structure 400. The plurality of top surface connection pads 430 may include nickel (Ni) or gold (Au). The second redistribution insulating layer 410 includes an opening 410H in an upper portion of the second redistribution insulating layer 410, and a top surface of each of the plurality of top surface connection pads 430 may be exposed through the opening 410H.

[0059] Generally speaking, in the process of forming a redistribution structure, a photosensitive polymer material is applied or coated on the top surface of a redistribution line pattern including copper, and a redistribution insulating layer is formed by a subsequent curing process. When the photosensitive polymer material is applied to a redistribution line pattern having a relatively large opening, a step may appear due to the relatively high height of the redistribution line pattern. Due to the presence of the step, a difference in coating speed may occur, and the interior of the opening may not be completely filled with the photosensitive polymer material, and air may be trapped, so that the air may remain in the photosensitive polymer material. The trapped air may cause voids or cracks in the redistribution insulating layer, or may cause defects in the subsequent redistribution line pattern.

[0060] However, since the opening Op is formed in the second ground line CL2_G at a portion vertically overlapping the first signal line CL1_S, the parasitic capacitance of the signal line may be reduced. In addition, the ventilation hole Vh is formed in the first end E1 of the opening Op, and therefore, air may be minimized or prevented from being trapped in the opening Op. Therefore, the semiconductor package 1 may have excellent reliability.

[0061] Fig. 12A and Fig. 12B is an example graph illustrating the frequency of defects occurring in semiconductor packages.

[0062] refer to Fig. 12A , Comparative Examples 1 to 4CO11, CO12, CO13, and CO14 may be semiconductor packages in which the large conductive lines in the first redistribution structure include openings having a relatively wide width. Examples 1 to 4EX11, EX12, EX13, and EX14 may be semiconductor packages that each further include a vent hole connected to the opening in each structure corresponding to Comparative Examples 1 to 4CO11, CO12, CO13, and CO14. In Example 1EX11, the width of the vent hole is approximately 8% of the opening width, in Example 2EX12, the width of the vent hole is approximately 9% of the opening width, in Example 3EX13, the width of the vent hole is approximately 11% of the opening width, and in Example 4EX14, the width of the vent hole is approximately 15% of the opening width. The number of defective products corresponds to the number of semiconductor packages in which bubbles having a reference size or larger are left in the opening.

[0063] like Fig. 12AAs shown, Example 1EX11 and Example 2EX12 indicate a slight increase in the number of defective products compared to Comparative Example 1CO11 and Comparative Example 2CO12, whereas Example 3EX13 indicates a slight decrease in the number of defective products compared to Comparative Example 3CO13, and Example 4EX14 indicates a significant decrease in the number of defective products compared to Comparative Example 4CO14, for example, the number of defective products is reduced by about 25%. Therefore, it can be confirmed that when the width of the vent is about 15% or more of the opening width, air can be prevented from being trapped in the opening. When the width of the vent is less than about 10% of the opening width, it can be assumed that the effect of preventing air stagnation by the vent is hardly exhibited, or the amount of air trapped in the relatively small vent increases instead.

[0064] See also Fig. 12B , Comparative Examples 5 to 8 CO21, CO22, CO23, and CO24 may be semiconductor packages in which the large conductive lines in the first redistribution structure include openings with relatively wide widths. In addition to the signal line design, Comparative Examples 5 to 8 CO21, CO22, CO23, and CO24 may have structures similar to Comparative Examples 1 to 4 CO11, CO12, CO13, and CO14, respectively. Examples 5 to 8 EX21, EX22, EX23, and EX24 may be semiconductor packages that each further include ventilation holes that communicate with the openings in each structure corresponding to Comparative Examples 5 to 8 CO21, CO22, CO23, and CO24. In Example 5EX21, the width of the vent hole is approximately 8% of the opening width, in Example 6EX22, the width of the vent hole is approximately 9% of the opening width, in Example 7EX23, the width of the vent hole is approximately 11% of the opening width, and in Example 8EX24, the width of the vent hole is approximately 15% of the opening width.

[0065] like Fig. 12B As shown, Example 5EX21, Example 6EX22, and Example 7EX23 indicate an increase in the number of defective products compared to Comparative Example 5CO21, Comparative Example 6CO22, and Comparative Example 7CO23, whereas Example 4EX14 indicates a decrease in the number of defective products compared to Comparative Example 4CO14. Therefore, it can be confirmed that when the width of the vent is about 15% or more of the opening width, air can be prevented from being trapped in the opening. When the width of the vent is less than about 10% of the opening width, it can be assumed that the effect of preventing air stagnation by the vent is hardly manifested, or the amount of air trapped in the relatively small vent increases instead.

[0066] Fig.13 is a cross-sectional view illustrating an example of the semiconductor package 2 .

[0067] refer to Fig.13 , the semiconductor package 2 may be a package on package (PoP) including a lower package LP and an upper package UP attached to the lower package LP.

[0068] The lower package LP may include a first redistribution structure 200, a second redistribution structure 400 located on the first redistribution structure 200, a semiconductor chip 100 disposed between the first redistribution structure 200 and the second redistribution structure 400, and a connection structure 300 disposed between the first redistribution structure 200 and the second redistribution structure 400 and surrounding the semiconductor chip 100. The lower package LP may include a reference Figures 1 to 11 A semiconductor package 1 is described.

[0069] The upper package UP may be attached to the second redistribution structure 400. The upper package UP may be electrically connected to the plurality of second redistribution patterns 420 of the second redistribution structure 400. For example, the upper package UP may be connected to the plurality of top surface connection pads 430. For example, a plurality of package connection terminals 950 may be arranged between the upper package UP and the plurality of top surface connection pads 430. For example, a plurality of package connection terminals 950 may be attached to the plurality of top surface connection pads 430. The plurality of package connection terminals 950 may electrically connect the lower package LP and the upper package UP to each other. In some implementations, each of the plurality of package connection terminals 950 may be a bump, a solder ball, or the like.

[0070] The upper package UP includes a package board 700 and an auxiliary semiconductor chip 800 mounted on the package board 700. The auxiliary semiconductor chip 800 may be mounted on the package board 700 through a plurality of auxiliary chip pads 820 disposed on a top surface of the auxiliary semiconductor chip 800.

[0071] The auxiliary semiconductor chip 800 may be a memory semiconductor chip, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip.

[0072] In some implementations, the auxiliary semiconductor chip 800 is electrically connected to the package board 700 through a plurality of bonding wires 830 connected to a plurality of auxiliary chip pads 820, and may be mounted on the package board 700 using a die attach film (DAF) 840. In some implementations, the upper package UP may include a plurality of auxiliary semiconductor chips 800 spaced apart from each other in the horizontal direction, or may also include a plurality of auxiliary semiconductor chips 800 stacked in the vertical direction. Alternatively, the upper package UP may include a plurality of auxiliary semiconductor chips 800 electrically connected by through electrodes and stacked in the vertical direction. Alternatively, the auxiliary semiconductor chip 800 may be mounted on the package board 700 in a flip chip manner.

[0073] The package board 700 may be a printed circuit board. For example, the package board 700 may be a double-sided printed circuit board or a multi-layer printed circuit board. The package board 700 may include at least one base insulating layer 710 and a plurality of wiring patterns 720. The plurality of wiring patterns 720 may include a portion arranged on the bottom surface of the base insulating layer 710, a portion arranged on the top surface of the base insulating layer 710, and a portion penetrating the base insulating layer 710. In some implementations, the package board 700 may include a solder resist layer 730 arranged on each top surface and each bottom surface of the base insulating layer 710. A plurality of package connection terminals 950 may be attached to portions arranged on the bottom surface of the base insulating layer 710 among the plurality of wiring patterns 720, and a plurality of bonding wires 830 may be connected to portions arranged on the top surface of the base insulating layer 710 among the plurality of wiring patterns 720.

[0074] In some implementations, the upper package UP may further include an encapsulation molding layer 890 surrounding the auxiliary semiconductor chip 800 and a plurality of bonding wires 830 on the package board 700. For example, the encapsulation molding layer 890 may be a molding member including epoxy molding compound (EMC).

[0075] Figures 14 to 18 , FIG. 19A to FIG. 19E and Fig. 20 is a schematic cross-sectional view illustrating an example of a method of manufacturing a semiconductor package.

[0076] refer to Fig.14 , a connection structure 300 including a base layer 310 and a plurality of connection paths 320 is prepared.

[0077] Each of the plurality of connection vias 320 may include a via portion 322 penetrating the base layer 310 , and a connection pattern portion 324 disposed on the top surface of the base layer 310 and integrally connected to the via portion 322 .

[0078] refer to Fig.15, forming a mounting space 300G penetrating from the top surface to the bottom surface of the connection structure 300. To form the mounting space 300G, dry etching, wet etching, screen printing, drill or laser drilling processes may be used. In some implementations, the mounting space 300G may be formed in a central area of ​​the connection structure 300 in a plan view.

[0079] refer to Fig.16 , after attaching the connection structure 300 to the support film 20, the semiconductor chip 100 is placed in the installation space 300G. The semiconductor chip 100 can be attached to the support film 20 in the installation space 300G. The support film 20 can be an adhesive film, but is not limited thereto. For example, the support film 20 can be a dicing film. The semiconductor chip 100 has a face-down arrangement, in which a first surface on which a plurality of lower chip pads 120 are arranged faces the support film 20 and can be attached to the support film 20.

[0080] refer to Fig.17 , a filling insulating layer 330 may be formed to fill the mounting space 300G. The filling insulating layer 330 may fill the space between the semiconductor chip 100 and the base layer 310 arranged in the mounting space 300G. In some implementations, the filling insulating layer 330 may be formed on the supporting film 20 to cover the side surface and the top surface of the semiconductor chip 100 and fill all the mounting space 300G.

[0081] After forming the filling insulation layer 330 , the support film 20 may be removed.

[0082] refer to Fig.18 , FIG. 19A to FIG. 19E , a first redistribution structure 200 is formed on the bottom surface of the semiconductor chip 100, the connection structure 300 and the filling insulation layer 330. Fig.17 After forming the resulting structure such that the bottom surfaces of the semiconductor chip 100 , the connection structure 300 , and the filling insulation layer 330 face upward, a first redistribution structure 200 may be formed on the semiconductor chip 100 , the connection structure 300 , and the filling insulation layer 330 .

[0083] The first redistribution insulating layers 210 may be formed by coating or applying a photopolymer material and curing the coated photopolymer material. Each of the first redistribution insulating layers 210 may include first to fourth insulating layers IL1, IL2, IL3, and IL4 formed by such photopolymer material coating, exposure, development, and curing processes.

[0084] For example, an exposure process may be performed on a portion of the first insulating layer IL1 , the portion of the first insulating layer IL1 may be removed by a developing process, and then the first insulating layer IL1 may be cured by a curing process.

[0085] Thereafter, a plurality of first conductive lines CL1 may be formed on the first insulating layer IL1. The plurality of first conductive lines CL1 may be formed using sputtering, physical vapor deposition, electron beam evaporation, an electroplating process, or an electroless plating process.

[0086] By repeating these processes, a second insulating layer IL2 is formed on the first insulating layer IL1 to cover the plurality of first conductive lines CL1 , a plurality of second conductive lines CL2 are formed on the second insulating layer IL2 , and a third insulating layer IL3 is formed on the second insulating layer IL2 to cover the plurality of second conductive lines CL2 .

[0087] FIG. 19A to FIG. 19E The coating process of the photosensitive polymer material for forming the third insulating layer IL3 covering the plurality of second conductive lines CL2 is schematically illustrated in time sequence.

[0088] like Fig.19A As shown, each of the plurality of second conductive lines CL2 may include a second ground line CL2_G, and the second ground line CL2_G may include an opening Op and a vent hole Vh. The opening Op may have a relatively wide first width w11, and the vent hole Vh may be arranged to communicate with the first end E1 of the opening Op and may have a second width w21 that is smaller than the first width w11. Due to the presence of the opening Op, a step may appear between the top surface of the second ground line CL2_G and the bottom surface of the opening Op.

[0089] refer to Fig.19B , the photosensitive polymer material PSM may be applied or coated in a coating direction D_coat. In some implementations, the coating process of the photosensitive polymer material PSM may include slit coating. In the coating process, the photosensitive polymer material PSM may be coated or applied along the coating direction D_coat from the second end E2 of the opening Op toward the first end E1 of the opening Op.

[0090] Fig.19C The example diagram shows a state where the photosensitive polymer material PSM fills the remaining portion of the opening Op, leaving only a portion adjacent to the first end E1 of the opening Op. Due to the presence of a step between the top surface of the second ground line CL2_G and the bottom surface of the opening Op, a difference may occur in the coating speed of the photosensitive polymer material PSM, and accordingly, the surface of the photosensitive polymer material PSM disposed inside the opening Op may move later than the surface of the photosensitive polymer material PSM on the top surface of the second ground line CL2_G. Fig.19C As shown, a portion of the opening Op adjacent to the first end E1 and the interior of the ventilation hole Vh may be in a state of not being filled with the photosensitive polymer material PSM.

[0091] Fig.19D The diagram illustrates a state in which the photosensitive polymer material PSM completely fills a portion of the opening Op adjacent to the first end E1 and is not filled in the ventilation hole Vh. All air inside the opening Op may be exhausted through the ventilation hole Vh.

[0092] Fig.19E The example diagram shows a state where the photosensitive polymer material PSM completely fills the inside of the ventilation hole Vh and covers the entire top surface of the second ground line CL2_G. Fig.19E As shown, the photopolymer material PSM may completely fill the interior of the opening Op with all air being exhausted through the vent hole Vh, and the interior of the vent hole Vh may also be completely filled with the photopolymer material PSM, or only a small amount of air may remain inside the vent hole Vh.

[0093] Return to reference Fig.18 , a plurality of third conductive wires CL3 may be formed on the third insulating layer IL3 , and a fourth insulating layer IL4 may be formed on the third insulating layer IL3 to cover the plurality of third conductive wires CL3 .

[0094] refer to Fig. 20 , a second redistribution structure 400 is formed on the top surface of the connection structure 300 and the filling insulation layer 330. After forming the first redistribution structure 200, the second redistribution structure 400 may be formed by vertically inverting the Fig.18 The resulting structure is such that the top surfaces of the connection structure 300 and the filling insulation layer 330 face upward and the first redistribution structure 200 faces downward, and the second redistribution structure 400 is formed on the connection structure 300 and the filling insulation layer 330 .

[0095] Afterwards, if Figure 1 As shown, the semiconductor package 1 may be formed by attaching a plurality of external connection terminals 500 to a plurality of bottom surface connection pads 230 .

[0096] Generally speaking, when a photosensitive polymer material is applied to a redistribution line pattern having a relatively large opening, a step may occur due to the relatively high height of the redistribution line pattern. Due to the presence of the step, a coating speed may vary, and the inside of the opening may not be completely filled with the photosensitive polymer material, and air may be trapped, so that the air may remain in the photosensitive polymer material. The trapped air may cause voids or cracks in the redistribution insulating layer, or may cause defects in the subsequent redistribution line pattern.

[0097] However, according to the above-described method of manufacturing the semiconductor package 1, the interior of the opening Op can be completely filled with the photosensitive polymer material through the ventilation hole Vh communicating with the first end E1 of the opening Op, and air stagnation inside the opening Op can be minimized or prevented. Therefore, the semiconductor package 1 can have excellent reliability.

[0098] The semiconductor package according to the present disclosure includes a signal line and a ground line arranged in a redistribution structure, and the ground line may include an opening vertically overlapping the signal line and a vent hole connected to an end of the opening. In the process of forming a redistribution insulating layer by coating a photosensitive polymer material to fill the opening, the vent hole can prevent bubbles from remaining in the opening and improve the reliability of the redistribution structure.

[0099] Although this specification contains many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope that may be claimed, but should be interpreted as a description of the features of a specific implementation that may be dedicated to a specific invention. Some features described in this specification in separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although the above-mentioned features may be described as working in certain combinations, one or more features from the combination can be removed from the combination in some cases, and the combination can be for sub-combinations or variations of sub-combinations.

[0100] While the present disclosure has been particularly shown and described with reference to implementations thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a redistribution structure, the redistribution structure comprising a first surface and a second surface; as well as a semiconductor chip, wherein the semiconductor chip is located on the first surface of the redistribution structure, The redistribution structure includes: a plurality of first conductive lines, the plurality of first conductive lines are at a first vertical height and include first signal lines; and a plurality of second conductive lines, the plurality of second conductive lines are at a second vertical height different from the first vertical height of the plurality of first conductive lines, the plurality of second conductive lines include ground lines electrically isolated from the first signal lines, Wherein, the grounding line includes: an opening, which extends through the grounding line at a position vertically overlapping with the first signal line, and the opening includes a first end having a first width in a first horizontal direction; and a ventilation hole, which is connected to the first end of the opening, and the ventilation hole has a second width in the first horizontal direction that is smaller than the first width.

2. The semiconductor package according to claim 1, wherein: The second width is 15% to 30% of the first width.

3. The semiconductor package according to claim 1, wherein: The ventilation hole has a third width in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, and The third width is 50% or more of the second width.

4. The semiconductor package according to claim 1, wherein: The ventilation hole has a planar shape of at least one of a circle, a triangle, a rectangle or a rounded rectangle.

5. The semiconductor package according to claim 1, wherein: The opening has a first area in plan view, The ventilation hole has a second area in the plan view, and The second area is in a range of 5% to 30% of the first area.

6. The semiconductor package according to claim 1, wherein: The first signal line includes a pair of signal line patterns, and The paired signal line patterns are spaced apart from each other in the first horizontal direction.

7. The semiconductor package according to claim 6, wherein: The opening vertically overlaps the pair of signal line patterns.

8. The semiconductor package according to claim 1, wherein: The plurality of first conductive lines include a first redistribution line spaced apart from the first signal line, and The plurality of second conductive lines include a second redistribution line spaced apart from the ground line.

9. The semiconductor package according to claim 1, wherein: The redistribution structure further includes: a redistribution insulating layer covering the plurality of first conductive lines and the plurality of second conductive lines, and A portion of the redistribution insulation layer is disposed inside the opening and the ventilation hole.

10. The semiconductor package according to claim 1, wherein The ventilation hole comprises: a first ventilation hole communicating with the first end of the opening; and A second ventilation hole is communicated with the first end of the opening, and the second ventilation hole is spaced apart from the first ventilation hole in the first horizontal direction.

11. The semiconductor package according to claim 1, further comprising: a connection structure, the connection structure being located on the first surface of the redistribution structure, the connection structure comprising a mounting space in which the semiconductor chip is mounted; as well as An external connection terminal is attached to the second surface of the redistribution structure, the external connection terminal being electrically connected to the redistribution structure.

12. A semiconductor package, comprising: a redistribution structure, the redistribution structure comprising a first surface and a second surface; a semiconductor chip, wherein the semiconductor chip is located on the first surface of the redistribution structure; as well as an external connection terminal, the external connection terminal being located on the second surface of the redistribution structure, The redistribution structure comprises: a plurality of first conductive lines, the plurality of first conductive lines are at a first vertical height lower than a vertical height of the first surface of the redistribution structure; a first redistribution insulating layer, the first redistribution insulating layer covering a plurality of bottom surfaces of the plurality of first conductive lines; a plurality of second conductive lines, the plurality of second conductive lines are located on the bottom surface of the first redistribution insulating layer, the plurality of second conductive lines are at a second vertical height lower than the first vertical height; and a second redistribution insulating layer, the second redistribution insulating layer is located on the bottom surface of the first redistribution insulating layer, the second redistribution insulating layer covers a plurality of bottom surfaces of the plurality of second conductive lines. Wherein, at least one of the plurality of second conductive lines comprises: an opening, the opening extending through the at least one second conductive line, the opening comprising a first end having a first width in a first horizontal direction; and a ventilation hole, the ventilation hole being connected to the first end of the opening, the ventilation hole having a second width smaller than the first width of the opening.

13. The semiconductor package according to claim 12, wherein: A portion of the second redistribution insulation layer is disposed inside the opening and inside the ventilation hole.

14. The semiconductor package according to claim 12, wherein: The plurality of first conductive lines include paired signal line patterns; and The opening vertically overlaps the pair of signal line patterns.

15. The semiconductor package according to claim 14, wherein: The second width is 15% to 30% of the first width.

16. The semiconductor package according to claim 15, wherein: The ventilation hole has a third width in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, and The third width is 50% or more of the second width.

17. The semiconductor package according to claim 12, wherein: The opening has a first area in plan view, The ventilation hole has a second area in the plan view, and The second area is in a range of 5% to 30% of the first area.

18. A semiconductor package, comprising: First redistribution structure; a semiconductor chip, the semiconductor chip being located on a top surface of the first redistribution structure; a connection structure located on a top surface of the first redistribution structure and located on at least one side of the semiconductor chip; a second redistribution structure, the second redistribution structure being located on the semiconductor chip and the connection structure; as well as a solder ball located on a bottom surface of the first redistribution structure, The first redistribution structure comprises: a plurality of first conductive lines, the plurality of first conductive lines comprising first signal lines; a first redistribution insulating layer, the first redistribution insulating layer covering the plurality of first conductive lines, the first redistribution insulating layer comprising a first photosensitive polymer; a plurality of second conductive lines, the plurality of second conductive lines being at a lower vertical height than the plurality of first conductive lines, the plurality of second conductive lines comprising a ground line electrically insulated from the first signal lines; and a second redistribution insulating layer, the second redistribution insulating layer covering the plurality of second conductive lines, the second redistribution insulating layer comprising a second photosensitive polymer. Wherein, the grounding line includes: an opening, which extends through the grounding line at a position vertically overlapping with the first signal line, and the opening includes a first end having a first width in a first horizontal direction; a ventilation hole, which is connected to the first end of the opening, and the ventilation hole has a second width smaller than the first width in the first horizontal direction; and a paired signal line pattern, wherein the opening vertically overlaps with the paired signal line pattern.

19. The semiconductor package according to claim 18, wherein: the second width is 15% to 30% of the first width, The ventilation hole has a third width in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, and The third width is 50% or more of the second width.

20. The semiconductor package according to claim 18, wherein The opening has a first area in plan view, The ventilation hole has a second area in the plan view, and The second area is in a range of 5% to 30% of the first area.

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