Semiconductor structure and method of testing the same

Abstract

The embodiment of the present application discloses a kind of semiconductor structure and its testing method, it is related to semiconductor technical field, can reduce the size of semiconductor structure, improve test efficiency, realize semiconductor structure can be suitable for different performance test.Semiconductor structure includes semiconductor substrate, stacked structure, at least one first test pad, at least one second test pad, at least one third test pad and at least one fourth test pad.Stacked structure includes multiple test chips and one conductive layer that are stacked and coupled with each other.The conductive layer is arranged between two adjacent test chips and is coupled with the test chips.The conductive layer includes multiple conductive structures arranged along the vertical direction of the semiconductor substrate and the stacked structure;one first test pad is coupled with one second test pad through one conductive structure;one third test pad is coupled with one fourth test pad through one conductive structure.

Description

Technical Field

[0001] This application relates to computer information technology, and to, but is not limited to, a semiconductor structure and its testing method. Background Technology

[0002] To achieve high-performance and small-size semiconductor memory devices, high integration is achieved by stacking multiple chips in a single package. The stacked chips can be interconnected using through-silicon via (TSV) type conductive structures.

[0003] In related technologies, semiconductor structures for testing the performance of multiple stacked chips occupy a large amount of space, and the testing efficiency of testing multiple semiconductor structures separately is low. Summary of the Invention

[0004] In view of the above, this application provides a semiconductor structure and its testing method to solve at least one problem existing in the prior art. It relates to the field of semiconductor technology, and can reduce the size of the semiconductor structure, improve testing efficiency, and enable the semiconductor structure to be suitable for testing different performance characteristics.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a semiconductor structure. The semiconductor structure includes: a semiconductor substrate, a stacked structure, at least one first test pad, at least one second test pad, at least one third test pad, and at least one fourth test pad.

[0007] A stacked structure is disposed on one side of the semiconductor substrate, including a plurality of test chips stacked and coupled to each other and a conductive layer; the conductive layer is disposed between two adjacent test chips and coupled to the test chips.

[0008] At least one first test pad is disposed on the side of the stacked structure away from the semiconductor substrate and is coupled to the stacked structure. At least one second test pad is disposed on the side of the stacked structure away from the semiconductor substrate and is spaced apart from the at least one first test pad; the at least one second test pad is coupled to the stacked structure. At least one third test pad is disposed on the side of the stacked structure close to the semiconductor substrate and is coupled to the stacked structure. At least one fourth test pad is disposed on the side of the stacked structure close to the semiconductor substrate and is spaced apart from the at least one third test pad; the at least one fourth test pad is coupled to the stacked structure.

[0009] The conductive layer includes a plurality of conductive structures spaced apart along a stacking direction perpendicular to the semiconductor substrate and the stacked structure; a first test pad is coupled to a second test pad through one of the conductive structures; and a third test pad is coupled to a fourth test pad through one of the conductive structures.

[0010] In some examples, one of the conductive structures is coupled to a first test pad and a second test pad, and to a third test pad and a fourth test pad.

[0011] In some examples, the number of test chips on the side of the conductive layer away from the semiconductor substrate may differ from the number of test chips on the side of the conductive layer closer to the semiconductor substrate.

[0012] In some examples, the semiconductor structure includes interconnect structures and transition structures. Multiple interconnect structures are disposed within the test chip. The opposite ends of each interconnect structure, extending along the stacking direction of the semiconductor substrate and the stacked structure, are exposed from the surface of the test chip. Transition structures are disposed between two adjacent test chips; one transition structure is coupled to two interconnect structures of each of the two adjacent test chips.

[0013] In some examples, the conductive layer is located between the first test chip and the second test chip along a stacking direction parallel to the semiconductor substrate and the stacked structure. Along a stacking direction parallel to the semiconductor substrate and the stacked structure, one of the conductive structures covers two interconnect structures of the first test chip and two interconnect structures of the second test chip.

[0014] In some examples, the test chip includes a first redistribution layer and a second redistribution layer located on opposite sides of the test chip along the stacking direction of the semiconductor substrate and the stacked structure.

[0015] A conductive signal line in the first redistribution layer serves as a first heating layer, and the first heating layer is coupled to the first test pad and the second test pad; and / or, a conductive signal line in the second redistribution layer serves as a second heating layer, and the second heating layer is coupled to the third test pad and the fourth test pad. The conductive layer serves as a sensing layer.

[0016] In some examples, the interconnect structures within different test chips are made of the same material and / or have the same dimensions.

[0017] In some examples, the material of the interconnect structure is the same as the material of the transition structure; and / or, the material of the conductive layer is the same as the material of the interconnect structure.

[0018] In the aforementioned semiconductor structure, the stacked structure can be divided into upper and lower test structures based on the connection relationship and placement of the conductive layers. With a first test pad coupled to a second test pad via a conductive structure, and a third test pad coupled to a fourth test pad via a conductive structure, the upper and lower test structures reduce the space occupied by the semiconductor structure compared to two test structures arranged horizontally.

[0019] Furthermore, considering the application of semiconductor structures in testing the performance of multilayer chips, a portion of the test structure can be tested using a conductive structure and a first test pad and a second test pad; another portion of the test structure can be tested using a conductive structure and a third test pad and a fourth test pad. This can improve testing efficiency, and in particular, broaden the applicability of semiconductor structures for testing different properties.

[0020] Secondly, embodiments of this application provide a method for testing semiconductor structures, used to perform radio frequency parameter testing on semiconductor structures as described in any of the above examples. The semiconductor structure includes a first test structure and a second test structure; the first test structure includes multiple test chips stacked between a first test pad and a conductive layer; the second test structure includes multiple test chips stacked between a third test pad and a conductive layer.

[0021] The testing method includes: measuring the return loss of the reflected signals from the first test pad and the second test pad respectively, and measuring the power of the transmitted signal between the first test pad and the second test pad to determine the power of the transmitted signal of the first test structure. The method also includes measuring the return loss of the reflected signals from the third test pad and the fourth test pad respectively, and measuring the power of the transmitted signal between the third test pad and the fourth test pad to determine the power of the transmitted signal of the second test structure.

[0022] In the aforementioned process of performing RF parameter testing on semiconductor structures, the first test structure can be tested using a conductive structure and a first test pad and a second test pad; the second test structure can be tested using a conductive structure and a third test pad and a fourth test pad. The first and second test structures can be tested separately. Within a single testing machine, only the test pads coupled to the semiconductor structure need to be changed to achieve testing of different test structures, which is beneficial for improving testing efficiency.

[0023] Thirdly, embodiments of this application provide a method for testing a semiconductor structure, characterized in that it is used to perform thermal testing on a semiconductor structure as described in any of the above examples; the semiconductor structure includes a first test structure and a second test structure; the first test structure includes a plurality of test chips stacked between a first heating layer and a conductive layer in a first redistribution layer coupled to a first test pad; the second test structure includes a plurality of test chips stacked between a second heating layer and a conductive layer in a second redistribution layer coupled to a third test pad.

[0024] The testing method includes: inputting current through the first test pad to the first test structure to reach a thermal equilibrium state, determining the current and voltage between the first test pad and the second test pad; and determining the temperature of the conductive structure and the thermal resistance of the first test structure.

[0025] In addition, by inputting current through the third test pad to the second test structure to reach a thermal equilibrium state, the current and voltage between the third test pad and the fourth test pad are determined; the temperature of the conductive structure and the thermal resistance of the second test structure are determined.

[0026] In the aforementioned thermal testing of the semiconductor structure, the first test structure can be tested using a conductive structure and a first test pad and a second test pad; the second test structure can be tested using a conductive structure and a third test pad and a fourth test pad. The first and second test structures can be tested separately, or thermal test data can be collected simultaneously while fulfilling the operational steps for RF signal testing. Specifically, interference factors involved in the actual testing operation can be eliminated before implementation to improve testing efficiency. Attached Figure Description

[0027] In the accompanying drawings, similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0028] Figure 1 Schematic diagram of the semiconductor structure provided for implementation of this application Figure 1 ;

[0029] Figure 2 Schematic diagram of the semiconductor structure provided for implementation of this application Figure 2 ;

[0030] Figure 3 Schematic diagram of the semiconductor structure provided for implementation of this application Figure 3 ;

[0031] Figure 4A schematic flowchart of a testing method for a semiconductor structure provided for the implementation of this application;

[0032] Figure 5 A flowchart illustrating another testing method for the semiconductor structure provided for the implementation of this application. Detailed Implementation

[0033] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0035] In the embodiments of this application, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0036] It should be understood that the phrases "some embodiments" or "some examples" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "some examples" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0037] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0038] It is understood that the meanings of “on”, “above” and “above” in this application should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intermediary feature or layer (i.e., directly on something), but also that it is “on” something with an intermediary feature or layer.

[0039] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0040] To meet the demand for reliable, small-size packaging of semiconductor integrated circuits, stacked packaging technologies have been developed to enable miniaturization and high performance of electrical / electronic devices.

[0041] In the field of semiconductor technology, "stacked packaging" refers to a device having two or more chips or packages stacked vertically. By implementing stacked packaging, semiconductor memory devices with a capacity more than twice the permissible storage capacity achieved through typical semiconductor processes can be formed.

[0042] Stacked packaging technology offers advantages such as large storage capacity, high packaging density, and small package size. Stacked packaging is formed by stacking multiple semiconductor chips and then encapsulating these stacked semiconductor chips together. Alternatively, stacked packaging can be formed by first encapsulating semiconductor chips and then stacking the encapsulated semiconductor chips. In this stacked package, the individual semiconductor chips can be electrically connected to each other via metal wires or through-silicon vias (TSVs), allowing multiple semiconductor chips to be physically and electrically connected in the vertical direction through the TSV-type conductive structures formed within them. This enables testing based on the TSV-type conductive structures within the stacked package semiconductor structure and the test pads of peripherals.

[0043] For example, the signal transmission quality of the entire semiconductor structure can be tested. However, multiple semiconductor structures need to be tested separately, and these structures occupy a significant amount of horizontal space.

[0044] Alternatively, a heating layer and a sensing layer can be added between the stacked semiconductor chips, and then the thermal resistance of the multiple semiconductor chips between the heating layer and the sensing layer can be tested. In other words, the thermal resistance of a single stack of semiconductor chips as a whole can only be tested within a single semiconductor structure. Furthermore, for thermal testing of multiple semiconductor structures, each semiconductor structure requires an additional heating layer and a sensing layer, significantly increasing the space occupied by the multiple semiconductor structures.

[0045] To address the aforementioned issues, this application provides a semiconductor structure and its testing method, which can reduce the size of the semiconductor structure, improve testing efficiency, and enable the semiconductor structure to be suitable for testing different performance characteristics.

[0046] In some embodiments, such as Figures 1-3 As shown, this application provides a semiconductor structure 100. The semiconductor structure 100 includes: a semiconductor substrate 110, a stacked structure 120, at least one first test pad 130, at least one second test pad 140, at least one third test pad 150, and at least one fourth test pad 160.

[0047] For example, the semiconductor substrate 110 may be a composite layer of multilayer materials. For instance, the semiconductor substrate 110 may include a conductive stack and a dielectric stack with conductive signal lines formed thereon. The specific structure of the semiconductor substrate 110 can be configured according to actual needs and is not limited herein.

[0048] The stacked structure 120 is disposed on one side of the semiconductor substrate 110 and includes a plurality of test chips 121 stacked and coupled to each other and a conductive layer 122. The conductive layer 122 is disposed between two adjacent test chips 121 and coupled to the test chips 121.

[0049] For example, test chip 121 can be either a chip or a die. It can be understood that both chip and die refer to the same structure (the names are interchangeable), and a die can be an unpackaged chip. This application does not limit the specific structure of test chip 121; in subsequent examples, test chip 121 refers to an integrated structure with internal circuitry.

[0050] At least one first test pad 130 is disposed on the side of the stacked structure 120 away from the semiconductor substrate 110 and is coupled to the stacked structure 120.

[0051] At least one second test pad 140 is disposed on the side of the stacked structure 120 away from the semiconductor substrate 110 and is spaced apart from at least one first test pad 130. At least one second test pad 140 is coupled to the stacked structure 120.

[0052] At least one third test pad 150 is disposed on the side of the stacked structure 120 near the semiconductor substrate 110 and coupled to the stacked structure 120.

[0053] At least one fourth test pad 160 is disposed on the side of the stacked structure 120 near the semiconductor substrate 110 and is spaced apart from at least one third test pad 150. At least one fourth test pad 160 is coupled to the stacked structure 120.

[0054] For example, the first test pad 130, the second test pad 140, the third test pad 150, and the fourth test pad 160 can be conductive structures that transmit current or voltage signals from external test equipment to the stack structure 120. For instance, the first test pad 130 can be a solder ball. Similarly, the second test pad 140, the third test pad 150, and the fourth test pad 160 can be conductive structures with the same structure and materials as the first test pad 130, and can be fabricated using the same process, thus improving process efficiency.

[0055] The conductive layer 122 includes multiple conductive structures 1221 spaced apart along a stacking direction perpendicular to the semiconductor substrate 110 and the stacked structure 120. For example, the conductive layer 122 may consist of multiple independent conductive structures 1221 formed in the same layer and using the same process, with one conductive structure 1221 used to implement a test structure (based on the varying number of test chips stacked between the conductive structure 1221 and the test pads); alternatively, it may consist of multiple conductive structures 1221 coupled to different regions of the same signal line based on variations in the extension direction of the signal lines within different test chips, with multiple conductive structures used to implement a test structure. This application does not impose specific limitations on the arrangement of the point structures and test chips, and can adjust them according to actual needs.

[0056] A first test pad 130 is coupled to a second test pad 140 via a conductive structure 1221. A third test pad 150 is coupled to a fourth test pad 160 via a conductive structure 1221.

[0057] For example, the conductive structure 1221 that couples a first test pad 130 and a second test pad 140 can be the same as or different from the conductive structure 1221 that couples a third test pad 150 and a fourth test pad 160, depending on the actual requirements.

[0058] In the aforementioned semiconductor structure 100, the stacked structure 120 can be divided into upper and lower test structures based on the connection relationship and arrangement of the conductive layer 122. With a first test pad 130 coupled to a second test pad 140 via a conductive structure 1221, and a third test pad 150 coupled to a fourth test pad 160 via a conductive structure 1221, the upper and lower test structures reduce the space occupied by the semiconductor structure 100 compared to two test structures arranged horizontally.

[0059] Furthermore, considering that the semiconductor structure 100 is used to test the performance of multilayer chips, a portion of the test structure can be tested through the conductive structure 1221, a first test pad 130, and a second test pad 140; another portion of the test structure can be tested through the conductive structure 1221, a third test pad 150, and a fourth test pad 160. This can improve testing efficiency, and in particular, broaden the applicability of the semiconductor structure 100 for testing different properties.

[0060] In some examples, such as Figure 2 As shown, a conductive structure 1221 is coupled to a first test pad 130 and a second test pad 140, and is also coupled to a third test pad 150 and a fourth test pad 160.

[0061] A conductive structure 1221 can be coupled to a first test pad 130, a second test pad 140, a third test pad 150 and a fourth test pad 160 respectively, which is beneficial to improve the electrical connection effect of the conductive structure 1221 in the scenario of testing the semiconductor structure 100, and improve the testing accuracy of the test chip 121 of the upper / lower half of the conductive structure 1221.

[0062] In some examples, such as Figure 2 and Figure 3 As shown, the number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 may be different from the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110.

[0063] For example, such as Figure 2 As shown, in a semiconductor structure 100, the stacked structure 120 includes seven layers of test chips 121 stacked together. The number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is three, and the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 is four.

[0064] In this way, test structures with different numbers of stacked chips (i.e., the structure between the test pads and the conductive layer 122) can be tested, satisfying the performance testing of semiconductor structures 100 in application scenarios with different numbers of stacked test chips 121.

[0065] For example, such as Figure 3 As shown, in a semiconductor structure 100, the stacked structure 120 includes eight layers of test chips 121 stacked together. The number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is 3, and the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 is 5.

[0066] In different semiconductor structures 100, the conductive layer 122 can be disposed at different locations. For example, multiple semiconductor structures 100 each include eight test chips 121. In one semiconductor structure 100, the conductive layer 122 can be disposed between the first test chip 121 and the second test chip 121. Alternatively, in one semiconductor structure 100, the conductive layer 122 can be disposed between the second test chip 121 and the third test chip 121, and so on. In multiple semiconductor structures 100 with the same number of stacked test chips 121, changing the position of the conductive layer 122 allows for testing the performance of test chips 121 with different stacked numbers.

[0067] In this way, compared to testing semiconductor structures composed of each test structure separately, the semiconductor structure 100 provided in this application has two test structures, which can reduce the number of semiconductor structures 100 to be fabricated and improve testing efficiency.

[0068] Furthermore, the number of test chips 121 on the side of the conductive layer 122 closest to the semiconductor substrate 110 is four. The number of test chips 121 on the side of the conductive layer 122 furthest from the semiconductor substrate 110 can be the same as the number of test chips 121 on the side of the conductive layer 122 closest to the semiconductor substrate 110.

[0069] For example, such as Figure 1 As shown, in a semiconductor structure 100, the stacked structure 120 includes eight layers of test chips 121 stacked together. The number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is four.

[0070] When testing the test chip 121 on the upper half of the conductive layer 122, a preliminary test is performed based on the potential interference of the test chip 121 on the signal transmission performance or thermal balance, and this data is stored as reference data. Thus, during the testing of the test chips 121 on both the upper and lower halves of the entire semiconductor structure 100, the influence of the preliminary test reference data is eliminated, and the impact of the test chip 121 on the signal transmission performance or thermal balance through the first test pad 130 and the second test pad 140 (or the third test pad 150 and the fourth test pad 160) can be quickly determined.

[0071] In some examples, such as Figure 2 As shown, the semiconductor structure 100 includes an interconnect structure 170 and a transition structure 180.

[0072] Multiple interconnect structures 170 are disposed within the test chip 121. The opposite ends of the interconnect structures 170 extending along the stacking direction of the semiconductor substrate 110 and the stacked structure 120 are exposed from the surface of the test chip 121.

[0073] For example, the interconnect structure 170 can be a conductive structure that penetrates the test chip 121 based on TSV vias. This application does not impose specific restrictions on how the interconnect structure 170 penetrates the test chip 121, and it can be adjusted according to the arrangement of the integrated circuit structure inside different test chips 121.

[0074] like Figure 2 As shown, the adapter structure 180 is disposed between two adjacent test chips 121. One adapter structure 180 is coupled to two interconnect structures 170 of the two adjacent test chips 121 respectively.

[0075] For example, the adapter structure 180 is configured to improve the connection reliability of different interconnect structures 170. For instance, in the process of coupling different test chips 121 through interconnect structures 170, the adapter structure 180 is configured to couple interconnect structures 170 located in different regions (where one end of the two interconnect structures 170 is not directly opposite each other).

[0076] In some examples, the interconnect structures 170 within different test chips 121 are made of the same material and / or have the same dimensions.

[0077] For example, the interconnect structures 170 within different test chips 121 are made of the same material. Alternatively, the interconnect structures 170 within different test chips 121 are of the same size. Or, the interconnect structures 170 within different test chips 121 are made of the same material and have the same size.

[0078] In this way, when testing multiple stacked test chips 121, the signal transmission loss caused by interconnect structures 170 of different materials and / or sizes can be reduced, thereby improving test accuracy.

[0079] In some examples, the material of interconnect structure 170 is the same as that of transition structure 180; and / or, the material of conductive layer 122 is the same as that of interconnect structure 170.

[0080] For example, the material of interconnect structure 170 is the same as the material of transition structure 180. Alternatively, the material of conductive layer 122 is the same as the material of interconnect structure 170. Or, the material of interconnect structure 170 is the same as the material of transition structure 180, and the material of conductive layer 122 is the same as the material of interconnect structure 170.

[0081] In this way, when testing multiple stacked test chips 121, the difference in the impact of different materials on signal transmission loss can be reduced, and the test accuracy can be improved.

[0082] In some examples, such as Figure 3As shown, along the stacking direction parallel to the semiconductor substrate 110 and the stacked structure 120, the conductive layer 122 is located between the first test chip 121a and the second test chip 121b.

[0083] Along the stacking direction parallel to the semiconductor substrate 110 and the stacked structure 120, a conductive structure 1221 covers two interconnect structures 170 of the first test chip 121a and two interconnect structures 170 of the second test chip 121b.

[0084] For example, when the conductive structure 1221 can couple the first test pad 130, the second test pad 140, the third test pad 150, and the fourth test pad 160, based on the structure in which the test chips 121 are coupled to each other through the interconnect structure 170, the dimensions of the conductive structure 1221 along the stacking direction perpendicular to the semiconductor substrate 110 and the stacked structure 120 can be set so that the conductive structure 1221 can be coupled to the two interconnect structures 170 of the first test chip 121a and the two interconnect structures 170 of the second test chip 121b, thereby improving the electrical connection reliability of the first test chip 121a and the second test chip 121b. During the testing of the entire semiconductor structure 100, the probability of signal loss due to poor electrical connection effect can be reduced, thereby improving the accuracy of the test.

[0085] In some examples, such as Figure 2 As shown, the test chip 121 includes a first redistribution layer 1211 and a second redistribution layer 1212 located on opposite side surfaces of the test chip 121 along the stacking direction of the semiconductor substrate 110 and the stacked structure 120.

[0086] It is understood that the first redistribution layer 1211 and the second redistribution layer 1212 are respectively disposed on opposite sides of the test chip 121, or they can be disposed on the same side of the test chip 121, which can be adjusted according to actual needs. In order to facilitate the use of the semiconductor structure for thermal testing, this application utilizes the signal lines in the redistribution layer as a heat-generating layer to reduce the thickness of the semiconductor structure 100, and therefore the first redistribution layer 1211 and the second redistribution layer 1212 are respectively disposed on opposite sides of the test chip 121.

[0087] For example, in a structure in which multiple test chips 121 are stacked, the first wiring layer 1211 may be located on the side of the test chip 121 away from the semiconductor substrate 110, and the second wiring layer 1212 may be located on the side of the test chip 121 close to the semiconductor substrate 110.

[0088] One conductive signal line in the first redistribution layer 1211 serves as the first heating layer (not shown in the figure), and the first heating layer is coupled to the first test pad 130 and the second test pad 140.

[0089] And / or, a conductive signal line in the second rewiring layer 1212 serves as a second heating layer (not shown in the figure), and the second heating layer is coupled to the third test pad 150 and the fourth test pad 160.

[0090] The conductive layer 122 serves as the sensing layer.

[0091] For example, a conductive signal line in the first redistribution layer 1211 serves as a first heating layer (not shown in the figure), and the first heating layer is coupled to the first test pad 130 and the second test pad 140.

[0092] The conductive layer 122 serves as the sensing layer.

[0093] In this way, thermal testing can be performed on multiple test chips 121 stacked between the first heating layer and the conductive layer 122 through the first test pad 130 and the second test pad 140.

[0094] As another example, a conductive signal line in the second rewiring layer 1212 serves as a second heating layer (not shown in the figure), which is coupled to the third test pad 150 and the fourth test pad 160.

[0095] The conductive layer 122 serves as the sensing layer.

[0096] In this way, thermal testing can be performed on multiple test chips 121 stacked between the first heating layer and the conductive layer 122 through the first test pad 130 and the second test pad 140.

[0097] As another example, a conductive signal line in the first redistribution layer 1211 serves as a first heating layer (not shown in the figure), and the first heating layer is coupled to the first test pad 130 and the second test pad 140.

[0098] One conductive signal line in the second wiring layer 1212 serves as the second heating layer (not shown in the figure), and the second heating layer is coupled to the third test pad 150 and the fourth test pad 160.

[0099] The conductive layer 122 serves as the sensing layer.

[0100] In this way, multiple test chips 121 stacked between the first heating layer and the conductive layer 122 can be thermally tested through the first test pad 130 and the second test pad 140 respectively; and the thermal testing efficiency of the semiconductor structure 100 can be improved by using the first test pad 130 and the second test pad 140 to perform thermal testing on the multiple test chips 121 stacked between the first heating layer and the conductive layer 122.

[0101] In some embodiments, such as Figure 4As shown, this application provides a testing method for a semiconductor structure 100, used to test the radio frequency parameters of the semiconductor structure 100 as provided in any of the above examples.

[0102] like Figure 3 As shown, the semiconductor structure 100 includes a first test structure 1001 and a second test structure 1002. The first test structure 1001 includes a plurality of test chips 121 stacked between a first test pad 130 and a conductive layer 122. The second test structure 1002 includes a plurality of test chips 121 stacked between a third test pad 150 and a conductive layer 122.

[0103] like Figure 4 As shown, the test method includes S100 and S200.

[0104] S100: Measure the return loss of the reflected signals from the first test pad 130 and the second test pad 140 respectively, and measure the power of the transmitted signal between the first test pad 130 and the second test pad 140 to determine the power of the transmitted signal of the first test structure 1001.

[0105] For example, by using a vector network analyzer (VNA) to transmit power to the first test structure 1001 through the first test pad 130, and then measuring the return loss of the reflected signal from the first test pad 130, the noise of the transmitted signal from the first test structure 1001 can be determined, and the power of the transmitted signal from the first test structure 1001 can be determined.

[0106] Similarly, a vector network analyzer (VNA) can be used to transmit power to the first test structure 1001 through the second test pad 140. Then, by measuring the return loss of the reflected signal from the second test pad 140, the noise of the transmitted signal from the first test structure 1001 can be determined, and the power of the transmitted signal from the first test structure 1001 can be determined.

[0107] In addition, the power transmitted from the first test pad 130 to the second test pad 140 can be measured. Alternatively, the power transmitted from the second test pad 140 to the first test pad 130 can be measured. This application does not impose specific limitations on the testing method for the signal transmission performance of the semiconductor structure 100, and it can be set according to actual needs.

[0108] S200: Measure the return loss of the reflected signals of the third test pad 150 and the fourth test pad 160 respectively, and measure the power of the transmitted signal between the third test pad 150 and the fourth test pad 160 to determine the power of the transmitted signal of the second test structure 1002.

[0109] For example, by using a vector network analyzer (VNA) to transmit power to the second test structure 1002 through the third test pad 150, and then measuring the return loss of the reflected signal from the third test pad 150, the noise of the transmitted signal in the second test structure 1002 can be determined, and the power of the transmitted signal in the second test structure 1002 can be determined.

[0110] Similarly, a vector network analyzer (VNA) can be used to transmit power to the second test structure 1002 through the fourth test pad 160. Then, by measuring the return loss of the reflected signal from the fourth test pad 160, the noise of the transmitted signal in the second test structure 1002 can be determined, and the power of the transmitted signal in the second test structure 1002 can be determined.

[0111] In addition, the power transmitted from the third test pad 150 to the fourth test pad 160 can be measured. Alternatively, the power transmitted from the fourth test pad 160 to the third test pad 150 can be measured. This application does not impose specific limitations on the testing method for the signal transmission performance of the semiconductor structure 100, and it can be set according to actual needs.

[0112] In the aforementioned process of performing RF parameter testing on semiconductor structure 100, the first test structure 1001 can be tested using conductive structure 1221, a first test pad 130, and a second test pad 140; alternatively, the second test structure 1002 can be tested using conductive structure 1221, a third test pad 150, and a fourth test pad 160, thereby improving testing efficiency. The first test structure 1001 and the second test structure 1002 can be tested separately. Within a single testing machine, only the test pads coupled to semiconductor structure 100 need to be changed to achieve testing of different test structures, which further enhances testing efficiency.

[0113] In some embodiments, such as Figure 5 As shown, this application provides a testing method for a semiconductor structure 100, used to perform thermal testing on the semiconductor structure 100 provided in any of the above examples.

[0114] like Figure 3 As shown, the semiconductor structure 100 includes a first test structure 1001 and a second test structure 1002. The first test structure 1001 includes a plurality of test chips 121 stacked between a first test pad 130 and a conductive layer 122. The second test structure 1002 includes a plurality of test chips 121 stacked between a third test pad 150 and a conductive layer 122.

[0115] like Figure 5 As shown, the test method includes S300 and S400.

[0116] S300: Input current through the first test pad 130 to the first test structure 1001 to reach thermal equilibrium, determine the current and voltage between the first test pad 130 and the second test pad 140; determine the temperature of the conductive structure 1221 and the thermal resistance of the first test structure 1001.

[0117] For example, a first current is input to the conductive layer 122 through the first test pad 130 to the first test structure 1001 to reach a thermal equilibrium state.

[0118] Determine the first voltage between the first test pad 130 and the second test pad 140.

[0119] Based on the first current and the first voltage, and the relationship between the resistivity of the conductive structure 1221 and the temperature, the temperature of the conductive structure 1221 and the thermal resistance of the first test structure 1001 are determined.

[0120] S400: Input current through the third test pad 150 to the second test structure 1002 to reach thermal equilibrium, determine the current and voltage between the third test pad 150 and the fourth test pad 160; determine the temperature of the conductive structure 1221 and the thermal resistance of the second test structure 1002.

[0121] For example, a second current is input to the conductive layer 122 through the third test pad 150 to the second test structure 1002 to reach a thermal equilibrium state.

[0122] Determine the second voltage between the third test pad 150 and the fourth test pad 160.

[0123] Based on the second current and the second voltage, and the relationship between the resistivity of the conductive structure 1221 and the temperature, the temperature of the conductive structure 1221 and the thermal resistance of the second test structure 1002 are determined.

[0124] It is understood that in the relationship between the resistivity of the conductive structure 1221 and temperature, the material, thickness, area, etc. of the conductive structure 1221 are all factors affecting the resistivity, and need to be determined according to the conductive structure 1221 coupled to different test structures. This application does not impose any restrictions on this.

[0125] During the thermal testing of semiconductor structure 100 described above, the first test structure 1001 can be tested through conductive structure 1221, a first test pad 130, and a second test pad 140; the second test structure 1002 can be tested through conductive structure 1221, a third test pad 150, and a fourth test pad 160. The first test structure 1001 and the second test structure 1002 can be tested separately, or thermal test data can be collected simultaneously while fulfilling the RF signal testing procedures. Specifically, interference factors involved in the actual testing operation can be eliminated before implementation to improve testing efficiency.

[0126] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a semiconductor substrate; a stack structure disposed on one side of the semiconductor substrate, comprising a plurality of test chips and a conductive layer stacked and coupled with each other; the conductive layer is disposed between two adjacent test chips and coupled with the test chips; at least one first test pad is disposed on the side of the stack structure away from the semiconductor substrate and coupled with the stack structure; at least one second test pad is disposed on the side of the stack structure away from the semiconductor substrate and spaced apart from the at least one first test pad; the at least one second test pad is coupled with the stack structure; at least one third test pad is disposed on the side of the stack structure close to the semiconductor substrate and coupled with the stack structure; at least one fourth test pad is disposed on the side of the stack structure close to the semiconductor substrate and spaced apart from the at least one third test pad; the at least one fourth test pad is coupled with the stack structure; wherein the conductive layer comprises a plurality of conductive structures spaced apart along a direction perpendicular to the semiconductor substrate and the stack structure; one of the first test pads is coupled with one of the second test pads through one of the conductive structures; one of the third test pads is coupled with one of the fourth test pads through one of the conductive structures.

2. The semiconductor structure of claim 1, wherein, one of the conductive structures is coupled with one of the first test pads and one of the second test pads, and coupled with one of the third test pads and one of the fourth test pads.

3. The semiconductor structure of claim 1, wherein, The number of test chips on the side of the conductive layer away from the semiconductor substrate can be different from the number of test chips on the side of the conductive layer close to the semiconductor substrate.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure comprises: a plurality of interconnection structures disposed in the test chips; the opposite ends of the interconnection structures extending along the stacking direction of the semiconductor substrate and the stack structure are respectively exposed from the surface of the test chip; an adapter structure is disposed between two adjacent test chips; one of the adapter structures is coupled with two of the interconnection structures of the two adjacent test chips.

5. The semiconductor structure of claim 4, wherein, The conductive layer is located between the first test chip and the second test chip along a direction parallel to the stacking direction of the semiconductor substrate and the stack structure; one of the conductive structures covers two of the interconnection structures of the first test chip and two of the interconnection structures of the second test chip along a direction parallel to the stacking direction of the semiconductor substrate and the stack structure.

6. The semiconductor structure of claim 1, wherein, The test chip comprises a first redistribution layer and a second redistribution layer located on the opposite side surfaces of the test chip along the stacking direction of the semiconductor substrate and the stack structure; one of the conductive signal lines in the first redistribution layer serves as a first heat layer, and the first heat layer is coupled with the first test pad and the second test pad; and / or, one of the conductive signal lines in the second redistribution layer serves as a second heat layer, and the second heat layer is coupled with the third test pad and the fourth test pad; the conductive layer serves as a sensing layer.

7. The semiconductor structure of claim 4, wherein, The material and / or size of the interconnection structure in different test chips are the same.

8. The semiconductor structure of claim 4, wherein, The material of the interconnection structure is the same as the material of the adapter structure. The conductive layer is the same as the material of the interconnection structure.

9. A method of testing a semiconductor structure, characterized by, The semiconductor structure includes a first test structure and a second test structure; the first test structure includes a plurality of test chips stacked between a first test pad and a conductive layer; The second test structure includes a plurality of test chips stacked between a third test pad and a conductive layer; The test method includes: Measuring the return loss of the reflected signal of the first test pad and the second test pad respectively, and measuring the power of the transmitted signal between the first test pad and the second test pad to determine the power of the transmitted signal of the first test structure. Measuring the return loss of the reflected signal of the third test pad and the fourth test pad respectively, and measuring the power of the transmitted signal between the third test pad and the fourth test pad to determine the power of the transmitted signal of the second test structure.

10. A method of testing a semiconductor structure, characterized by, The semiconductor structure includes a first test structure and a second test structure; the first test structure includes a plurality of test chips stacked between a first heat layer in a first redistribution layer coupled with a first test pad and a conductive layer; The second test structure includes a plurality of test chips stacked between a second heat layer in a second redistribution layer coupled with a third test pad and a conductive layer; The test method includes: Inputting current to the first test structure through the first test pad to reach a thermal equilibrium state, determining the current and voltage between the first test pad and the second test pad; Determining the temperature of the conductive structure and the thermal resistance of the first test structure; And inputting current to the second test structure through the third test pad to reach a thermal equilibrium state, determining the current and voltage between the third test pad and the fourth test pad; Determining the temperature of the conductive structure and the thermal resistance of the second test structure.

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