Satellite-borne SAR antenna

Abstract

The invention relates to a spaceborne SAR antenna, which comprises a plurality of standardized antenna modules working independently and concurrently, each standardized antenna module in the plurality of standardized antenna modules comprises a low-power radio frequency module, and the low-power radio frequency module comprises a digital receiving module with an optical fiber interface. The digital receiving module comprises an FPGA (Field Programmable Gate Array) module and a time buffer module connected with the FPGA module; and the FPGA module is used for receiving and analyzing the SAR antenna system synchronization signal according to the optical fiber interface, and taking the analyzed synchronization signal as a synchronization trigger signal SYNC of the time buffer module, so that an SYSREF signal output by the time buffer module based on the synchronization trigger signal SYNC is synchronized with the SAR antenna system synchronization signal. Therefore, the time delay consistency of the multi-channel high-speed data acquisition circuit can be realized.

Description

Technical Field

[0001] The invention relates to the technical field of high-speed digital acquisition and processing of satellite SAR antennas, and in particular to a satellite-borne SAR antenna. Background Art

[0002] In the spaceborne SAR antenna, the high-speed digital acquisition circuit, as a bridge for converting analog signals to digital signals, occupies an important position in the system. It mainly completes the intermediate frequency sampling, digital mixing, digital filtering and data transmission of the SAR antenna echo signal, while also taking into account the SAR antenna array wave control function. The key performance indicators of the high-speed data acquisition circuit, such as instantaneous bandwidth, signal-to-noise ratio, spurious-free dynamic range, in-band fluctuation, and phase nonlinearity, affect the pulse compression performance of the SAR radar, and thus restrict the image quality of the SAR radar. At the same time, the delay uncertainty of high-speed digital acquisition will affect the accuracy of spaceborne SAR interferometry, especially in the digital array SAR payload. The delay uncertainty between multiple digital acquisition channels limits the coherence performance of the SAR radar and seriously affects the image quality of the SAR radar.

[0003] At present, traditional spaceborne SAR antennas generally use analog phased array systems to output single-channel echo data, requiring only a single digital acquisition channel. However, single-channel SAR antennas cannot achieve high resolution and wide bandwidth, which seriously restricts the high-precision and large-scale imaging capabilities of SAR satellites. Therefore, spaceborne SAR antennas will develop towards a digital, multi-channel technology system in the future, so it is necessary to solve the problem of multi-channel high-speed digital acquisition delay consistency. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a spaceborne SAR antenna, which solves the technical problem of time delay consistency of multi-channel high-speed digital acquisition.

[0006] (II) Technical solution

[0007] In order to achieve the above object, the main technical solutions adopted by the present invention include:

[0008] The embodiment of the present invention provides a spaceborne SAR antenna, comprising a plurality of independently parallel working standardized antenna modules, each of the plurality of standardized antenna modules comprising a low-power radio frequency module, and the low-power radio frequency module comprising a digital receiving module having an optical fiber interface, and the digital receiving module comprising an FPGA module and a time buffer module connected to the FPGA module;

[0009] The FPGA module is used to receive and parse the SAR antenna system synchronization signal according to the optical fiber interface, and use the parsed synchronization signal as the synchronization trigger signal SYNC of the time buffer module, so that the SYSREF signal output by the time buffer module based on the synchronization trigger signal SYNC is synchronized with the SAR antenna system synchronization signal.

[0010] In a possible embodiment, each standardized radio frequency module further includes a waveguide antenna and a plurality of TR components; wherein the low-power radio frequency module and the plurality of TR components are arranged on the radiation surface of the waveguide antenna, and the low-power radio frequency modules are connected to the plurality of TR components.

[0011] In a possible embodiment, the low-power radio frequency modules further include a radio frequency receiving module connected to the digital receiving module.

[0012] In a possible embodiment, the digital receiving modules further include a clock driving module, a time measurement module and an ADC sampling module based on the JESD204B protocol, and the clock driving module, the time measurement module and the ADC sampling module are all connected to the FPGA module and the time buffer module; the SYSREF signal includes a SYSREF0 signal, a SYSREF1 signal and a SYSREF2 signal;

[0013] The clock driving module outputs SYNC_A signal and SYNC_B signal respectively according to the synchronization trigger signal SYNC, and the time measurement module uses the SYNC_A signal as the delay measurement reference signal, and the time buffer module outputs SYSREF0 signal, SYSREF1 signal and SYSREF2 signal according to the SYNC_B signal; among which, the SYSREF0 signal is used as the multi-frame clock synchronization pulse of the ADC sampling module, the SYSREF1 signal is used as the multi-frame clock synchronization pulse of the FPGA module, and the SYSREF2 signal is used as the STOP input signal of the time measurement module.

[0014] In a possible embodiment, the digital receiving modules further include a clock distribution module, a clock generation module and a broadband RF synthesizer, the clock generation module is respectively connected to the clock distribution module and the FPGA module, and the broadband RF synthesizer is respectively connected to the clock distribution module and the time buffer module.

[0015] In a possible embodiment, the FPGA module includes a counter; the FPGA module is specifically configured to trigger the counter to generate a synchronization trigger signal SYNC according to a SAR antenna system synchronization signal.

[0016] In one possible embodiment, the FPGA module further includes an ODELAY delay module; the FPGA module is further specifically used to read the delay value of the SYNC_A signal and the SYSREF2 signal measured by the time measurement module, and based on the delay value, determine whether the time buffer module can stably sample the SYNC_B signal, and if the SYNC_B signal is not stably sampled, adjust the tap coefficient of the ODELAY delay module.

[0017] In a possible embodiment, the FPGA module is further specifically configured to perform two-stage register beat processing on the SYSREF1 signal, and use the signal after the beat processing as a multi-frame clock synchronization pulse on the receiving side of the JESD204B interface.

[0018] (III) Beneficial effects

[0019] The beneficial effects of the present invention are:

[0020] An embodiment of the present application proposes a satellite-borne SAR antenna, comprising a plurality of independently working in parallel standardized antenna modules, each of the plurality of standardized antenna modules comprising a low-power radio frequency module, and the low-power radio frequency module comprising a digital receiving module having an optical fiber interface, and the digital receiving module comprising an FPGA module and a time buffer module connected to the FPGA module, and the FPGA module is capable of receiving and parsing a SAR antenna system synchronization signal according to the optical fiber interface, and using the parsed synchronization signal as a synchronization trigger signal SYNC of the time buffer module, so that the SYSREF signal output by the time buffer module based on the synchronization trigger signal SYNC is synchronized with the SAR antenna system synchronization signal, thereby enabling the delay consistency of a multi-channel high-speed data acquisition circuit to be achieved.

[0021] In order to make the above-mentioned objectives, features and advantages to be achieved by the embodiments of the present application more obvious and understandable, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of a standardized antenna module provided in an embodiment of the present application is shown;

[0024] Figure 2 A schematic diagram of the structure of a low-power radio frequency module provided in an embodiment of the present application is shown;

[0025] Figure 3 A schematic diagram of the structure of a digital receiving module provided in an embodiment of the present application is shown;

[0026] Figure 4 A specific structural schematic diagram of a digital receiving module provided in an embodiment of the present application is shown;

[0027] Figure 5 A schematic diagram of the structure of a circuit for generating a synchronization trigger signal SYNC in an FPGA module provided in an embodiment of the present application is shown;

[0028] Figure 6 A schematic diagram of a circuit structure for processing a SYSREF1 signal in an FPGA module provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0030] In order to solve the problem of time delay consistency in multi-channel high-speed digital acquisition, the embodiment of the present application proposes a satellite-borne SAR antenna, which realizes the time delay consistency of the multi-channel high-speed data acquisition circuit through a combination of software and hardware design, thereby ensuring the coherence of the multi-channel echoes of the digital array SAR antenna. This technology is applied to satellite SAR antennas to achieve high-resolution and wide-bandwidth imaging of satellite-borne SAR.

[0031] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0032] It should be noted here that the spaceborne SAR antenna of the present application includes multiple standardized antenna modules that work independently and in parallel. For ease of understanding, the following description is taken as an example to describe any one of the multiple standardized antenna modules. The other standardized antenna modules are similar. For details, please refer to the following related description.

[0033] See also Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of the structure of a standardized antenna module provided in an embodiment of the present application. Figure 1As shown, the standardized antenna module includes a waveguide antenna, four TR components (i.e., TR component 1 to TR component 4) and a low-power RF module, and the low-power RF module and the four TR components are arranged on the radiation surface of the waveguide antenna, and the low-power RF module can be connected to the four TR components. In addition, the external interfaces of the digital standard antenna module are only power supply, clock and optical fiber.

[0034] It should be noted here that although Figure 1 The description is made by taking four TR components as an example, and those skilled in the art may set the specific number of TR components according to actual needs. For example, the standardized antenna module may include eight TR components.

[0035] Further, see Figure 2 , Figure 2 FIG. 1 shows a schematic diagram of the structure of a low-power radio frequency module provided in an embodiment of the present application. Figure 2 As shown, the low-power RF module includes a RF receiving module and a digital receiving module, and the digital receiving module has an ADC acquisition channel, that is, if the satellite-borne SAR antenna has N standard antenna modules, there are N digital receiving modules, and the N digital receiving modules have N ADC acquisition channels.

[0036] Further, see Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of the structure of a digital receiving module provided in an embodiment of the present application. Figure 3 As shown in the figure, the digital receiving module includes an ADC sampling module, a power management module, a clock management module and an optoelectronic / electro-optical conversion module. After the external analog intermediate frequency signal enters the digital receiving module, it is converted into a digital signal by the ADC sampling module. The digital signal is further processed inside the FPGA module and output by the electro-optical conversion module. The circuit management module is responsible for converting the external power supply into the voltage required by various chips inside the digital receiving. The clock management module is responsible for converting the external reference clock into various clocks required inside the digital receiving.

[0037] It should be understood that the specific modules of the ADC sampling module, the specific modules of the power management module, the specific modules of the clock management module and the specific modules of the optoelectronic / electro-optical conversion module can all be set according to actual needs, and the embodiments of the present application are not limited to this.

[0038] For example, the digital receiving ADC sampling module uses the high-speed ADC acquisition chip AD9689 based on the JESD204B protocol, which supports deterministic delay. At the same time, the clock management module matching the ADC uses the high-performance, 14-channel output clock buffer HMC7043 that provides multi-channel clocks for high-speed serial interface (JESD204B type) chips. The device selection and circuit design of the digital receiving module meet the hardware requirements of high-speed multi-channel synchronous acquisition.

[0039] Further, see Figure 4 , Figure 4 FIG. 2 shows a specific structural diagram of a digital receiving module provided in an embodiment of the present application. Figure 4 As shown, the external reference clock outputs three clocks through the clock distribution module: one of which is used as the reference clock source for the FPGA module, another is used as the clock source for the clock generation module, and the last is used as the clock source for the broadband RF synthesizer. Also, the clock generation module generates two sets of reference clocks, which are used as the MGT reference clock of the optical fiber link and the MGT reference clock of the JESD204B link of the FPGA respectively. Also, the clock generated by the broadband RF synthesizer can be used as the input clock of the time buffer module. Also, the time buffer module mainly provides a multi-channel clock for the high-speed serial interface (JESD204B type) chip, and the time buffer module outputs four clocks: DCLK signal, SYSREF0 signal, SYSREF1 signal and SYSREF2 signal. Among them, the DCLK signal is used as the sampling clock of the ADC sampling module; the SYSREF0 signal is configured as the multi-frame clock synchronization pulse of the JESD204B interface of the ADC sampling module; the SYSREF1 signal is configured as the multi-frame clock synchronization pulse of the JESD204B interface of the FPGA module; and the SYSREF2 signal is used as the input pulse of the time measurement module.

[0040] Furthermore, the FPGA module receives and analyzes the SAR antenna system synchronization signal through the optical fiber interface, and generates a synchronization trigger signal SYNC according to the analyzed synchronization signal. Furthermore, the synchronization trigger signal SYNC outputs two signals, SYNC_A signal and SYNC_B signal, through the clock driver module. Furthermore, the SYNC_A signal is sent to the time measurement module, and is used as the START signal as the delay measurement reference signal; the SYNC_B signal is used as the synchronization trigger input signal of the time buffer module, triggering the time buffer module to output the SYSREF0 signal, the SYSREF1 signal and the SYSREF2 pulse signal. Among them, the SYSREF0 signal is used as the multi-frame clock synchronization pulse of the JESD204B interface sending side (ADC sampling module); the SYSREF1 signal is used as the multi-frame clock synchronization pulse of the JESD204B interface receiving side (FPGA module); and the SYSREF2 signal is used as the STOP input signal of the clock driver module.

[0041] Furthermore, the SYSREF0 signal and SYSREF1 signal output by the time buffer module can be used as multi-frame clock synchronization signals of the JESD204B interface link to achieve deterministic delay of the link between the ADC sampling module and the FPGA module. At the same time, the SYSREF0 signal, SYSREF1 signal, and SYSREF2 signal output by the time buffer module can be generated synchronously by the SYNC_B signal, and the SYNC_B signal can be generated by the SAR antenna system synchronization signal through the clock driving module, that is, the SYNC_B signal is synchronized with the SAR antenna system synchronization signal. Therefore, the signal acquisition of the N acquisition channels of the N standard antenna modules is synchronized with the SAR antenna system synchronization signal, thereby achieving deterministic delay of the N acquisition channels and achieving the purpose of multi-channel acquisition synchronization design.

[0042] It should be understood that the specific modules of all modules in the digital receiving module can be set according to actual needs, and the embodiments of the present application are not limited to this.

[0043] For example, the clock distribution module may be a clock distribution chip ADCLK944; for another example, the clock generation module may be a clock chip AD9516; for another example, the broadband RF synthesizer may be a LMX2594 chip; for another example, the time buffer module may be a clock buffer HMC7043; for another example, the clock drive module may be a clock driver AD9508; for another example, the clock drive module may be a time measurement chip TDC-GP22; for another example, the ADC sampling module may be a high-speed ADC acquisition chip AD9689 based on the JESD204B protocol.

[0044] Further, see Figure 5 , Figure 5FIG. 1 is a schematic diagram showing a circuit structure for generating a synchronization trigger signal SYNC in an FPGA module provided by an embodiment of the present application. Figure 5 As shown, the FPGA module triggers the counter to generate a SYNC signal based on the SAR antenna system synchronization signal transmitted by the analytical optical fiber. The pulse period of the SYNC signal is configured as an integer multiple of the multi-frame clock period of the JESD204B interface LMFC. In addition, the SYNC signal is output through the ODELAY delay module, and the delay value of the SYNC_A signal measured by the time measurement module and the output SYSREF2 signal is read to determine whether the time buffer module can stably collect the synchronization trigger signal SYNC_B. In addition, if the SYNC_B signal is not stably collected, the delay of the SYNC output can be adjusted by changing the tap coefficient of the ODELAY delay module, so that the working clock of the time buffer module can stably collect the SYNC_B signal, ensuring that the phase difference between the SYSREF0 signal, SYSREF1 signal and the SYNC signal output by the time buffer module is stable.

[0045] Further, see Figure 6 , Figure 6 FIG. 1 shows a schematic diagram of a circuit structure for processing a SYSREF1 signal in an FPGA module provided in an embodiment of the present application. Figure 6 As shown in the figure, the SYSREF1 signal output by the time buffer module enters the FPGA module. After being processed by the two-level registers inside the FPGA module, the signal is used as a multi-frame clock synchronization pulse on the receiving side of the JESD204B interface. Among them, the position of the first-level tapping D flip-flop (i.e., register) can be constrained and fixed inside the FPGA, and the second-level tapping D flip-flop (i.e., register) can be used to ensure timing convergence. Through the two-level register tapping processing, it is ensured that the SYSREF1 signal can be stably sampled on the FPGA side.

[0046] Therefore, with the help of the above technical solution, the present application has the following technical effects:

[0047] Simple system architecture: high-speed digital acquisition circuit realizes integrated transmission of large-capacity data and radar timing signals through optical fiber, simplifying system interfaces and interconnecting cables;

[0048] High system coherence: The delay and phase of each multi-channel startup are consistent, which ensures the coherence of the multi-channel acquisition circuit from the hardware perspective. Compared with the software correction implementation method, it has good coherence and delay consistency, thus improving the performance of spaceborne SAR interferometry.

[0049] High system test efficiency: By ensuring the synchronization of multi-channel acquisition circuits through hardware, the SAR antenna integration test time can be greatly simplified. There is no need to integrate all standard antenna modules and then perform software calibration. The SAR antenna system test can be carried out after completing the TR component amplitude and phase calibration at the standard antenna module level.

[0050] It should be understood that the above-mentioned space-borne SAR antenna is only exemplary, and those skilled in the art may make various modifications according to the above-mentioned method, and the modified scheme also belongs to the protection scope of the present application.

[0051] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0052] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions.

[0053] It should be noted that in the claims, any reference numerals placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In the claims enumerating several means, several of these means may be embodied by the same hardware. The use of the words first, second, third, etc., is for convenience of expression only and does not indicate any order. These words may be understood as part of the component name.

[0054] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0055] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments after knowing the basic creative concept. Therefore, the claims should be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0056] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention should also include these modifications and variations.

Claims

1. A spaceborne SAR antenna, characterized in that: It comprises a plurality of independently parallel working standardized antenna modules, each of the plurality of standardized antenna modules comprises a low-power radio frequency module, and the low-power radio frequency module comprises a digital receiving module with an optical fiber interface, and the digital receiving module comprises an FPGA module and a time buffer module connected to the FPGA module; The FPGA module is used to receive and parse the SAR antenna system synchronization signal according to the optical fiber interface, and use the parsed synchronization signal as the synchronization trigger signal SYNC of the time buffer module, so that the SYSREF signal output by the time buffer module based on the synchronization trigger signal SYNC is synchronized with the SAR antenna system synchronization signal.

2. The spaceborne SAR antenna according to claim 1, characterized in that: Each of the standardized radio frequency modules further includes a waveguide antenna and a plurality of TR components; wherein the low-power radio frequency module and the plurality of TR components are arranged on the radiation surface of the waveguide antenna, and the low-power radio frequency modules are connected to the plurality of TR components.

3. The spaceborne SAR antenna according to claim 2, characterized in that: The low-power radio frequency modules further include a radio frequency receiving module connected to the digital receiving module.

4. The spaceborne SAR antenna according to claim 1, characterized in that: The digital receiving modules further include a clock driving module, a time measurement module and an ADC sampling module based on the JESD204B protocol, wherein the clock driving module, the time measurement module and the ADC sampling module are all connected to the FPGA module and the time buffer module; the SYSREF signal includes a SYSREF0 signal, a SYSREF1 signal and a SYSREF2 signal; The clock driving module outputs a SYNC_A signal and a SYNC_B signal respectively according to the synchronization trigger signal SYNC, and the time measurement module uses the SYNC_A signal as a delay measurement reference signal, and the time buffer module outputs the SYSREF0 signal, the SYSREF1 signal and the SYSREF2 signal according to the SYNC_B signal; wherein the SYSREF0 signal serves as a multi-frame clock synchronization pulse of the ADC sampling module, the SYSREF1 signal serves as a multi-frame clock synchronization pulse of the FPGA module, and the SYSREF2 signal serves as a STOP input signal of the time measurement module.

5. The spaceborne SAR antenna according to claim 4, characterized in that: The digital receiving modules further include a clock distribution module, a clock generation module and a broadband RF synthesizer. The clock generation module is respectively connected to the clock distribution module and the FPGA module, and the broadband RF synthesizer is respectively connected to the clock distribution module and the time buffer module.

6. The spaceborne SAR antenna according to claim 4, characterized in that: The FPGA module includes a counter; the FPGA module is specifically used to trigger the counter to generate a synchronization trigger signal SYNC according to the SAR antenna system synchronization signal.

7. The spaceborne SAR antenna according to claim 6, characterized in that: The FPGA module further includes an ODELAY delay module; the FPGA module is further specifically used to read the delay value of the SYNC_A signal and the SYSREF2 signal measured by the time measurement module, and based on the delay value, determine whether the time buffer module can stably sample the SYNC_B signal; if the SYNC_B signal is not stably sampled, adjust the tap coefficient of the ODELAY delay module.

8. The spaceborne SAR antenna according to claim 4, characterized in that: The FPGA module is further specifically used to perform two-stage register beat processing on the SYSREF1 signal, and use the signal after the beat processing as a multi-frame clock synchronization pulse on the receiving side of the JESD204B interface.

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