A protection circuit for reducing chip area

Abstract

The present invention relates to the technical field of circuit protection, and particularly relates to a protection circuit for reducing chip area. The protection circuit includes: a soft start circuit, a periodic time generation circuit, a timing circuit, and a protection signal generation circuit. The timing circuit includes a plurality of D flip-flops connected in series. The first end of the periodic time generation circuit is connected to the first end of the protection signal generation circuit and receives an external circuit abnormal signal. In the present invention, a periodic time signal is generated by using the soft start circuit and the periodic time generation circuit. Since the periodic time of this periodic time signal is much longer than the periodic time generated by the oscillator inside the power chip, therefore, on the basis of adding a small number of additional devices, the protection circuit greatly reduces the number of D flip-flops, thereby reducing the chip area. At the same time, the protection circuit in the present invention realizes the function of soft start when the circuit is working normally, and realizes the function of the protection circuit when the circuit has an abnormal condition, so that the circuit realizes function multiplexing.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit protection, and particularly to a protection circuit for reducing chip area. Background Art

[0002] The protection circuit is an essential component in the internal circuit of a power chip. When the protection circuit receives an abnormal signal from the external circuit of the power chip, it usually first outputs a high-level signal (the protection circuit outputs a low-level signal during normal circuit operation) for a period of time T0, and then switches to output a low-level signal, so that the external circuit of the power chip is turned off for a period of time T0 and then starts working again. If there is still an abnormal condition in the external circuit of the power chip, the protection circuit will continue to turn off the external circuit of the power chip for a period of time T0 and then start working again until the external circuit of the power chip returns to normal.

[0003] In the prior art, the protection circuit usually uses an oscillator and a D flip-flop inside the power chip in cooperation to achieve the function of first outputting a high-level signal for a period of time T0 and then switching to output a low-level signal. However, since the output of the oscillator inside the power chip is a high-frequency signal, many D flip-flops are required to obtain the time T0, thus increasing the chip area. Summary of the Invention

[0004] In view of this, the present invention provides a protection circuit for reducing chip area to solve the technical problem that a large number of D flip-flops need to be set in the protection circuit of the prior art, which increases the chip area.

[0005] The technical solution provided by the present invention is as follows:

[0006] In a first aspect, the present invention provides a protection circuit for reducing chip area, including: a soft start circuit, a cycle time generation circuit, a timing circuit, and a protection signal generation circuit. The first end of the cycle time generation circuit is connected to the first end of the protection signal generation circuit and receives an abnormal signal from the external circuit;

[0007] When the abnormal signal from the external circuit is a low-level signal, the cycle time generation circuit generates a low-level signal and makes the soft start circuit in a working state. The timing circuit is in an unworking state according to the low-level signal, and the protection signal generation circuit outputs a low-level protection signal according to the low-level signal and the timing circuit.

[0008] When the abnormal signal from the external circuit is a high-level signal, the working states of the cycle time generation circuit and the soft start circuit affect each other, so that the cycle time generation circuit outputs a cycle time signal. The timing circuit outputs a periodic signal according to the cycle time signal and a reset signal, and the protection signal generation circuit outputs a reset signal according to the periodic signal. The protection signal generation circuit also outputs a protection signal according to the abnormal signal from the external circuit and the reset signal.

[0009] In an alternative embodiment, a soft start circuit has its first end, second end, and third end connected to the second end, third end, and fourth end of a cycle time generation circuit respectively, its first end is also connected to an external power supply, and its second end is grounded; a cycle time generation circuit has its fifth end connected to the first end of a timing circuit; a timing circuit has its second end, third end, and fourth end connected to the second end, third end, and fourth end of a protection signal generation circuit respectively; a protection signal generation circuit outputs a protection signal at its fifth end.

[0010] In an alternative embodiment, the soft start circuit includes a first current source and a first capacitor. One end of the first current source is connected to the external power supply and the second end of the cycle time generation circuit, and the other end of the first current source is connected to one end of the first capacitor and the fourth end of the cycle time generation circuit. The other end of the first capacitor is connected to the third end of the cycle time generation circuit and grounded.

[0011] In an alternative embodiment, the cycle time generation circuit includes a first switching transistor, a second switching transistor, a comparator, a first inverter, a first AND gate, a second current source, and a second capacitor; the first input terminal of the first AND gate receives an external circuit abnormality signal, the second input terminal of the first AND gate is connected to the output terminal of the comparator, the output terminal of the first AND gate is connected to the first end of the second switching transistor, the second end of the second switching transistor is connected to one end of the second capacitor, the first end of the first switching transistor, and grounded, the third end of the second switching transistor is connected to the other end of the second capacitor, the input terminal of the first inverter, and one end of the second current source, the other end of the second current source is connected to the external power supply, the output terminal of the first inverter is connected to the second end of the first switching transistor and the first end of the timing circuit, the third end of the first switching transistor is connected to the third end of the soft start circuit and the positive input terminal of the comparator, and the negative input terminal of the comparator receives a first voltage.

[0012] In an alternative embodiment, the output terminal of the first inverter outputs a cycle time signal.

[0013] In an alternative embodiment, the timing circuit includes a plurality of serially connected D flip-flops. Among the plurality of serially connected D flip-flops, the clock input terminal of the first D flip-flop is connected to the fifth end of the cycle time generation circuit, the clear terminal of the first D flip-flop is grounded, and starting from the second D flip-flop, the clock input terminal of each D flip-flop is connected to the inverted output terminal and the signal input terminal of the previous D flip-flop, and the clear terminal of each D flip-flop is connected to the second end of the protection signal generation circuit.

[0014] In an alternative embodiment, the protection signal generation circuit includes a second AND gate, an RS flip-flop, and a second inverter. The first input terminal of the second AND gate is connected to the period time generation circuit and receives an external circuit abnormal signal. The second input terminal of the second AND gate receives a reset signal output by the RS flip-flop. The second AND gate outputs a protection signal. The reset terminal of the RS flip-flop is connected to the inverted output terminal of the last D flip-flop among a plurality of D flip-flops. The set terminal of the RS flip-flop is connected to the inverted output terminal of the first D flip-flop among a plurality of D flip-flops. The output terminal of the RS flip-flop is connected to the input terminal of the second inverter. The output terminal of the second inverter serves as the second terminal of the protection signal generation circuit.

[0015] In an alternative embodiment, the protection signal generation circuit includes a second AND gate, an RS flip-flop, a second inverter, and a third inverter. The first input terminal of the second AND gate is connected to the period time generation circuit and receives an external circuit abnormal signal. The second input terminal of the second AND gate receives a reset signal output by the RS flip-flop. The second AND gate outputs a protection signal. The input terminal of the third inverter is connected to the output terminal of the last D flip-flop among a plurality of D flip-flops. The output terminal of the third inverter is connected to the reset terminal of the RS flip-flop. The set terminal of the RS flip-flop is connected to the inverted output terminal of the first D flip-flop among a plurality of D flip-flops. The output terminal of the RS flip-flop is connected to the input terminal of the second inverter. The output terminal of the second inverter serves as the second terminal of the protection signal generation circuit.

[0016] In an alternative embodiment, the number of D flip-flops is determined according to the period of the period time signal and a preset turn-off time when the external circuit is abnormal.

[0017] In an alternative embodiment, the timing circuit includes at least two D flip-flops.

[0018] In a second aspect, the present invention provides an analog integrated circuit control chip, including the protection circuit for reducing the chip area according to the first aspect and any one of the first aspect of the present invention.

[0019] In a third aspect, the present invention provides a power supply circuit, including the analog integrated circuit control chip according to the second aspect of the present invention.

[0020] The technical solution of the present invention has the following advantages:

[0021] The protection circuit for reducing chip area provided by the present invention uses a soft start circuit and a cycle time generation circuit to generate a cycle time signal. Since the cycle time of this cycle time signal is much larger than the cycle time generated by the oscillator inside the power chip, on the basis of adding a small number of additional devices, the protection circuit significantly reduces the number of D flip-flops, thereby reducing the chip area. At the same time, the protection circuit in the present invention realizes the function of soft start when the circuit is working normally, and realizes the function of the protection circuit when the circuit has an abnormal condition, enabling the circuit to achieve function multiplexing.

[0022] The analog integrated circuit control chip provided by the present invention reduces the volume of the analog integrated circuit control chip due to the above-mentioned protection circuit for reducing chip area.

[0023] The power supply circuit provided by the present invention further reduces the volume of the power supply circuit when an analog integrated circuit control chip is provided in the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 It is a block diagram of the protection circuit for reducing chip area in an embodiment of the present invention;

[0026] Figure 2 It is a schematic diagram of the protection circuit for reducing chip area in an embodiment of the present invention;

[0027] Figure 3 It is a waveform diagram of each signal in the protection circuit when the external circuit is working normally in an embodiment of the present invention;

[0028] Figure 4 It is the first waveform diagram of each signal in the protection circuit when the external circuit is working abnormally in an embodiment of the present invention;

[0029] Figure 5 It is the second waveform diagram of each signal in the protection circuit when the external circuit is working abnormally in an embodiment of the present invention;

[0030] Figure 6 It is a schematic diagram of another protection circuit for reducing chip area in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0032] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0033] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0034] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] An embodiment of the present invention provides a protection circuit for reducing the chip area, as Figure 1 shown. The protection circuit includes: a soft start circuit 10, a cycle time generation circuit 20, a timing circuit 30, and a protection signal generation circuit 40. The timing circuit 30 includes a plurality of D flip-flops connected in series. The first end of the cycle time generation circuit 20 is connected to the first end of the protection signal generation circuit 40 and receives an external circuit abnormal signal, that is, a first signal S1;

[0036] When the external circuit abnormal signal is a low-level signal, the cycle time generation circuit 20 generates a low-level signal and makes the soft start circuit 10 in a working state. The timing circuit 30 is in a non-working state according to the low-level signal, and the protection signal generation circuit 40 outputs a low-level protection signal according to the low-level signal and the timing circuit 30 in the non-working state;

[0037] When the external circuit abnormal signal is a high-level signal, the operating states of the cycle time generation circuit 20 and the soft start circuit 10 affect each other, causing the operating state of the cycle time generation circuit 20 to change periodically. The cycle time generation circuit 20 outputs a cycle time signal, and the timing circuit 30 outputs a plurality of periodic signals according to the cycle time signal and the reset signal input by the protection signal generation circuit 40. The protection signal generation circuit 40 outputs a protection signal that periodically changes between high and low levels according to the external circuit abnormal signal and the reset signal. The reset signal is generated by the protection signal generation circuit 40 through logical processing of the plurality of periodic signals output by the timing circuit 30.

[0038] The soft start circuit 10, its first end, second end, and third end are respectively connected to the second end, third end, and fourth end of the cycle time generation circuit 20. Its first end is also connected to an external power supply, and its second end is grounded; the cycle time generation circuit 20, its fifth end is connected to the first end of the timing circuit 30; the timing circuit 30, its second end, third end, and fourth end are respectively connected to the second end, third end, and fourth end of the protection signal generation circuit 40; the protection signal generation circuit 40, its fifth end outputs a protection signal, that is, the tenth signal S10.

[0039] Specifically, the protection circuit is a protection circuit inside the power chip. The external circuit abnormal signal can be a signal generated when a fault occurs in the external circuit (such as a short circuit). When the external circuit is operating normally, the external circuit abnormal signal is a low-level signal. When the external circuit is abnormal, the external circuit abnormal signal is a high-level signal.

[0040] Among them, when the external circuit abnormal signal is a low-level signal, the first end of the cycle time generation circuit is at a low level. Based on this low-level signal, the fifth end of the cycle time generation circuit is also at a low level, that is, no high-level signal is input to the timing circuit, so the timing circuit does not work (is in an unoperated state). The first end of the protection signal generation circuit receives the external circuit abnormal signal, so its first end is also at a low level; at the same time, since the timing circuit is in an unoperated state, there is no level signal input to the second, third, and fourth ends connected to the protection signal generation circuit and the timing circuit. Therefore, the protection signal generation circuit is also in an unoperated state, and the protection signal output by its fifth end is also a low-level signal. In addition, when a low level is input to the first end of the cycle time generation circuit, it will cause the soft start circuit to be in a normal operating state.

[0041] When the external circuit abnormal signal is a high-level signal, the first terminal of the cycle time generation circuit is at a high level. The input of this high-level signal to the cycle time generation circuit causes a change in its operating state, which further causes a change in the operating state of the soft start circuit connected thereto. The change in the operating state of the soft start circuit in turn affects the cycle time generation circuit, causing the operating state of the cycle time generation circuit to change again. Thus, based on the mutual influence of the operating states of the cycle time generation circuit and the soft start circuit, the cycle time signal is output from the fifth terminal of the cycle time generation circuit. This cycle time signal is a signal that periodically changes between high and low levels.

[0042] Based on this cycle time signal, the timing circuit enters the operating state. At the same time, based on the connection between the timing circuit and the protection signal generation circuit, the protection signal generation circuit receives the signal output by the timing circuit, performs logical processing, and then inputs it to the clear terminal of the timing circuit to reset the D flip-flop. Thus, the timing circuit outputs a plurality of periodically changing signals under the action of the cycle time signal and the reset signal input by the protection signal generation circuit. Based on the structural design of the protection signal generation circuit, the waveforms of the protection signal and the reset signal it outputs are the same, and the reset signal is determined according to the plurality of periodically changing signals output by the timing circuit. Thus, the protection signal is also a periodically changing signal.

[0043] Among them, the protection signal output by the protection signal generation circuit first outputs a high-level signal and then outputs a low-level signal, which causes the external circuit to be turned off for a period of time (the duration of the high-level signal) and then restart. If the external circuit is still in an abnormal state after restarting, that is, the external circuit abnormal signal is still a high-level signal, the protection circuit continues to output a high-level signal. Thus, if the external circuit abnormal signal is always a high-level signal, the protection signal output by the protection circuit is a signal that periodically changes between high and low levels. In addition, the requirements for the turn-off time are different in different application scenarios, and the turn-off time can be changed by changing the number of D flip-flops. At the same time, the operation of the timing circuit is also affected by the cycle time signal. Therefore, the number of D flip-flops is determined according to the period of the cycle time signal and the preset turn-off time when the external circuit is abnormal.

[0044] In the present invention, the cycle time signal is generated by using the soft start circuit and the cycle time generation circuit. Since the cycle time of this cycle time signal is much longer than the cycle time generated by the oscillator inside the power supply chip, therefore, on the basis of adding a small number of additional devices, the protection circuit significantly reduces the number of D flip-flops, thereby reducing the chip area. At the same time, the protection circuit in the present invention realizes the function of soft start when the circuit is working normally and realizes the function of the protection circuit when the circuit has an abnormal condition, enabling the circuit to achieve function multiplexing.

[0045] In an alternative embodiment, such asFigure 2 As shown, the soft start circuit includes a first current source I1 and a first capacitor C1. One end of the first current source I1 is connected to the external power supply and the second end of the cycle time generation circuit. The other end of the first current source I1 is connected to one end of the first capacitor C1 and the fourth end of the cycle time generation circuit. The other end of the first capacitor C1 is connected to the third end of the cycle time generation circuit and is grounded.

[0046] The cycle time generation circuit includes a first switching transistor M1, a second switching transistor M2, a comparator A1, a first inverter NOT1, a first AND gate AND1, a second current source I2, and a second capacitor C2. The first input terminal of the first AND gate AND1 is connected to the first end of the protection signal generation circuit and receives an external circuit abnormal signal. The second input terminal of the first AND gate AND1 is connected to the output terminal of the comparator A1. The output terminal of the first AND gate AND1 is connected to the first end of the second switching transistor M2. The second end of the second switching transistor M2 is connected to one end of the second capacitor C2, the first end of the first switching transistor M1, and is grounded. The third end of the second switching transistor M2 is connected to the other end of the second capacitor C2, the input terminal of the first inverter NOT1, and one end of the second current source I2. The other end of the second current source I2 is connected to the external power supply. The output terminal of the first inverter NOT1 is connected to the second end of the first switching transistor M1 and the first end of the timing circuit. The third end of the first switching transistor M1 is connected to the third end of the soft start circuit and the positive input terminal of the comparator A1. The negative input terminal of the comparator A1 receives a first voltage.

[0047] Among multiple serially connected D flip-flops, the clock input terminal of the first D flip-flop is connected to the fifth end of the cycle time generation circuit, and the clear terminal of the first D flip-flop is grounded. Starting from the second D flip-flop, the clock input terminal of each D flip-flop is connected to the inverted output terminal and the signal input terminal of the previous D flip-flop. The clear terminal of each D flip-flop is connected to the second end of the protection signal generation circuit. Additionally, the minimum number of D flip-flops in the timing circuit can be only two. Compared with the protection circuit using an oscillator and D flip-flops, the number of D flip-flops used is greatly reduced.

[0048] The protection signal generation circuit includes a second AND gate AND2, an RS flip-flop A2, and a second inverter NOT2. The first input terminal of the second AND gate AND2 is connected to the cycle time generation circuit and receives an external circuit abnormal signal. The second input terminal of the second AND gate AND2 receives a reset signal output by the RS flip-flop A2. The second AND gate AND2 outputs a protection signal. The reset terminal of the RS flip-flop A2 (the third terminal of the protection signal generation circuit) is connected to the inverted output terminal of the last D flip-flop among a plurality of D flip-flops (the third terminal of the timing circuit). The set terminal of the RS flip-flop A2 (the fourth terminal of the protection signal generation circuit) is connected to the inverted output terminal of the first D flip-flop among a plurality of D flip-flops (the fourth terminal of the timing circuit). The output terminal of the RS flip-flop A2 is connected to the input terminal of the second inverter NOT2. The output terminal of the second inverter NOT2 serves as the second terminal of the protection signal generation circuit.

[0049] Specifically, when the external circuit is in a normal operating state, that is, when the external circuit abnormal signal is a low-level signal, the first signal S1 is at a low level. Therefore, at this time, both the tenth signal S10 output by the second AND gate AND2 and the signal output by the first AND gate AND1 are also at low levels. Since the first AND gate AND1 outputs a low-level signal, the second switching transistor M2 is turned off, and the second current source I2 continuously charges the second capacitor C2. The first inverter NOT1 inputs a high level, and the fourth signal S4 output by the first inverter NOT1 is at a low level. The first switching transistor M1 is turned off, and the first current source I1 continuously charges the first capacitor C1. The voltage of the third signal S3 continuously increases. When the voltage of the third signal S3 increases to be greater than the first voltage V1, the second signal S2 output by the comparator A1 switches from a low level to a high level and always maintains a high-level state. After that, the voltage of the third signal S3 continues to increase until the first capacitor C1 is fully charged. In addition, since the fourth signal S4 is always at a low level, after this low-level fourth signal S4 is input to the timing circuit, the timing circuit is always in a non-operating state.

[0050] From the above analysis, when the external circuit is in a normal operating state, only the soft start circuit in the protection circuit is in a normal operating state, and the protection circuit is only used as a soft start circuit. Figure 3 shows the waveform diagrams of various signals in the protection circuit when the external circuit is in a normal operating state. From Figure 3 it can be seen that when the external circuit is in a normal operating state, the third signal S3 (i.e., the soft start signal) gradually increases. When the third signal S3 increases to the maximum value, the circuit completes the startup process.

[0051] When the external circuit is in an abnormal operating state, that is, when the external circuit abnormal signal is a high-level signal, the first signal S1 switches to a high level, and from Figure 3It can be known that when the external circuit is in a normal working state, the second signal S2 is at a high level. Therefore, at this time, the output of the first AND gate AND1 switches from a low level to a high level, the second switching transistor M2 conducts, the input terminal of the first inverter NOT1 is pulled low, the fourth signal S4 switches to a high level, the first switching transistor M1 conducts, and the third signal S3 switches to a low level. At this time, the second signal S2 output by the comparator A1 also switches to a low level. After that, the output of the first AND gate AND1 switches from a high level to a low level, the second switching transistor M2 turns off, the second current source I2 charges the second capacitor C2. When the terminal voltage of the second capacitor C2 is greater than the switching threshold voltage of the first inverter NOT1, the fourth signal S4 switches from a high level to a low level, the first switching transistor M1 turns off, the first current source I1 starts to charge the first capacitor C1, and the voltage of the third signal S3 starts to gradually increase. When the voltage of the third signal S3 increases to be greater than the first voltage V1, the second signal S2 output by the comparator A1 switches from a low level to a high level. At this time, the output of the first AND gate AND1 switches from a low level to a high level again, the second switching transistor M2 conducts again, the input terminal of the first inverter NOT1 is pulled low, the fourth signal S4 switches to a high level, and the circuit enters the next cycle. At this time, the first waveform diagram when the external circuit is in an abnormal working state as shown in Figure 4 can be obtained. At this time, the fourth signal S4 can also be called a periodic time signal.

[0052] From Figure 4 the waveform, it can be seen that when the circuit is in an abnormal working state, after a short time when the first signal S1 switches to a high level, the second signal S2 switches from a high level state to a low level state. This short time is the feedback adjustment time of the circuit. In each subsequent cycle, the second signal S2 switches from a high level state to a low level state after this short time; the time for the fourth signal S4 to maintain a high level = the time for the third signal S3 to maintain a low level ≈ the time for the second capacitor C2 to be charged to a terminal voltage greater than the switching threshold voltage of the first inverter NOT1.

[0053] At the same time, from Figure 2 it can be known that the first signal S1 and the ninth signal S9 pass through the second AND gate AND2 and then output the tenth signal S10. When the circuit is in an abnormal working state, the first signal S1 is always at a high level. Therefore, the waveform of the tenth signal S10 is the same as the waveform of the ninth signal S9. At this time, first design the number of D flip - flops in the timing circuit to be three, and then analyze the waveform of the ninth signal S9:

[0054] Since the fourth signal S4 is input to the clock input terminal of the first D flip-flop, the fifth signal S5 is input to the clock input terminal of the second D flip-flop, and the sixth signal S6 is input to the clock input terminal of the third D flip-flop, the waveforms of the fifth signal S5, the sixth signal S6, and the seventh signal S7 can be obtained according to the waveform of the fourth signal S4, as Figure 5 shown.

[0055] As Figure 5 shown, the initial signals of the fifth signal S5, the sixth signal S6, and the seventh signal S7 are all high-level signals. When the rising edge of the fourth signal S4 arrives, the fifth signal S5 changes its level and outputs. When the rising edge of the fifth signal S5 arrives, the sixth signal S6 changes its level and outputs. When the rising edge of the sixth signal S6 arrives, the seventh signal S7 changes its level and outputs. At this time, since the seventh signal S7 is input to the R terminal (reset terminal) of the RS flip-flop A2, the signal input to the R terminal of the RS flip-flop is in the same phase as the seventh signal S7, and the signal input to the S terminal (set terminal) of the RS flip-flop is the fifth signal S5. That is, at this time, according to the waveforms of the fifth signal S5 and the seventh signal S7, the waveform of the ninth signal S9 (which can also be called the reset signal) at the output terminal of the RS flip-flop A2 can be obtained. In the first cycle of the fourth signal S4, the fifth signal S5 is at a low level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 is at a high level. In the second cycle of the fourth signal S4, the fifth signal S5 is at a high level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 remains at a high level. In the third cycle of the fourth signal S4, the fifth signal S5 is at a low level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 is at a high level. In the fourth cycle of the fourth signal S4, the fifth signal S5 is at a high level and the seventh signal S7 is at a low level. Therefore, the ninth signal S9 is at a low level. At this time, since the ninth signal S9 passes through the second inverter NOT2 and is input to the CL terminals (clear terminals) of the second D flip-flop and the third D flip-flop, and the D flip-flop resets when the CL terminal receives a high level, when the ninth signal S9 is at a low level, the second D flip-flop and the third D flip-flop are immediately reset, and the seventh signal S7 and the sixth signal S6 return to the initial high-level state. At this time, the fifth signal S5 is at a high level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 remains at a low level. After that, in the fifth cycle of the fourth signal S4, the fifth signal S5 is at a low level and the seventh signal S7 is at a high level, and the ninth signal S9 switches to a high level again. After that, the circuit keeps working in a loop according to the above working process.

[0056] Therefore, when the tenth signal S10 (protection signal) output by the protection circuit is at a high level, the external circuit is controlled to enter the protection state. When the tenth signal S10 (protection signal) output by the protection circuit is at a low level, the external circuit is controlled to enter the normal working state. If the abnormal condition of the external circuit still exists, the circuit enters the protection state again.

[0057] In an alternative embodiment, as Figure 6 shown, the protection signal generation circuit includes a second AND gate AND2, an RS flip-flop A2, a second inverter NOT2, and a third inverter NOT3. The first input terminal of the second AND gate AND2 is connected to the period time generation circuit and receives the external circuit abnormal signal. The second input terminal of the second AND gate AND2 receives the reset signal output by the RS flip-flop A2. The second AND gate AND2 outputs the protection signal. The input terminal of the third inverter NOT3 (the third terminal of the protection signal generation circuit) is connected to the output terminal of the last D flip-flop among a plurality of D flip-flops (the third terminal of the timing circuit). The output terminal of the third inverter NOT3 is connected to the reset terminal of the RS flip-flop A2. The set terminal of the RS flip-flop A2 (the fourth terminal of the protection signal generation circuit) is connected to the inverted output terminal of the first D flip-flop among a plurality of D flip-flops (the fourth terminal of the timing circuit). The output terminal of the RS flip-flop A2 is connected to the input terminal of the second inverter NOT2. The output terminal of the second inverter NOT2 serves as the second terminal of the protection signal generation circuit.

[0058] Specifically, by providing the third inverter NOT3 in the protection signal generation circuit, the input terminal of the third inverter NOT3 is connected to the output terminal of the last D flip-flop, that is, the eighth signal S8 output by the output terminal of the last D flip-flop is inverted and then input to the RS flip-flop A2. The eighth signal S8 actually has the same waveform as the seventh signal S7 output by the inverted output terminal of the last D flip-flop. However, by further providing the third inverter NOT3 in the protection signal generation circuit, the current capacity of the signal can be improved, and the circuit response speed can be accelerated.

[0059] The present invention also provides an analog integrated circuit control chip, including the protection circuit for reducing the chip area in the above embodiment.

[0060] The present invention also provides a power supply circuit, including the analog integrated circuit control chip in the above embodiment.

[0061] Specifically, when an analog integrated circuit control chip is provided in the power supply circuit, the chip can control the power supply process of the power supply circuit. Moreover, in addition to the analog integrated circuit control chip, structures such as a power circuit can also be provided in the power supply circuit. Since the above-mentioned protection circuit for reducing the chip area is provided in the analog integrated circuit control chip, the volume of the analog integrated circuit control chip is thus reduced; and when the analog integrated circuit control chip is provided in the power supply circuit, the volume of the power supply circuit is further reduced.

[0062] Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims. Such modifications and variations fall within the scope defined by the appended claims. For other examples, those of ordinary skill in the art should easily understand that the order of process steps can be changed while maintaining the scope of protection of the present invention.

[0063] In addition, the application scope of the present invention is not limited to the processes, mechanisms, manufacturing, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of the present invention, as those of ordinary skill in the art will readily understand, for the processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps that currently exist or will be developed in the future, and which perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in the present invention, they can be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps within their scope of protection.

Claims

1. A protection circuit for reducing chip area, characterized in that: include: A soft start circuit, a cycle time generating circuit, a timing circuit and a protection signal generating circuit, wherein a first end of the cycle time generating circuit is connected to a first end of the protection signal generating circuit and receives an external circuit abnormality signal; When the external circuit abnormality signal is a low-level signal, the cycle time generating circuit generates a low-level signal and makes the soft start circuit in a working state, the timing circuit is in a non-working state according to the low-level signal, and the protection signal generating circuit outputs a low-level protection signal according to the low-level signal and the timing circuit; When the external circuit abnormality signal is a high-level signal, the working states of the cycle time generation circuit and the soft start circuit affect each other so that the cycle time generation circuit outputs a cycle time signal, the timing circuit outputs a periodic signal according to the cycle time signal and the reset signal, the protection signal generation circuit outputs a reset signal according to the periodic signal, and the protection signal generation circuit also outputs a protection signal according to the external circuit abnormality signal and the reset signal; A soft start circuit, wherein the first end, the second end and the third end are respectively connected to the second end, the third end and the fourth end of the cycle time generating circuit, the first end is also connected to an external power supply, and the second end is grounded; a cycle time generating circuit, a fifth terminal of which is connected to the first terminal of the timing circuit; a timing circuit, wherein the second end, the third end and the fourth end of the timing circuit are respectively connected to the second end, the third end and the fourth end of the protection signal generating circuit; A protection signal generating circuit, wherein the fifth terminal thereof outputs a protection signal; The cycle time generating circuit includes a first switch tube, a second switch tube, a comparator, a first inverter, a first AND gate, a second current source and a second capacitor; The first input end of the first AND gate receives an external circuit abnormality signal, the second input end of the first AND gate is connected to the output end of the comparator, the output end of the first AND gate is connected to the first end of the second switch tube, the second end of the second switch tube is connected to one end of the second capacitor, the first end of the first switch tube and grounded, the third end of the second switch tube is connected to the other end of the second capacitor, the input end of the first inverter and one end of the second current source, the other end of the second current source is connected to an external power supply, the output end of the first inverter is connected to the second end of the first switch tube and the first end of the timing circuit, the third end of the first switch tube is connected to the third end of the soft start circuit and the positive input end of the comparator, and the negative input end of the comparator receives the first voltage.

2. The chip area reducing protection circuit according to claim 1, characterized in that: The soft start circuit includes a first current source and a first capacitor, one end of the first current source is connected to an external power supply and a second end of a cycle time generating circuit, the other end of the first current source is connected to one end of the first capacitor and a fourth end of the cycle time generating circuit, and the other end of the first capacitor is connected to a third end of the cycle time generating circuit and is grounded.

3. The chip area reducing protection circuit according to claim 1, characterized in that: The output terminal of the first inverter outputs a periodic time signal.

4. The chip area reducing protection circuit according to claim 1, characterized in that: The timing circuit includes a plurality of D flip-flops connected in series. Among the plurality of D flip-flops connected in series, a clock input terminal of the first D flip-flop is connected to the fifth terminal of the cycle time generating circuit, and a reset terminal of the first D flip-flop is grounded. Starting from the second D flip-flop, a clock input terminal of each D flip-flop is connected to the inverting output terminal and the signal input terminal of the previous D flip-flop, and a reset terminal of each D flip-flop is connected to the second terminal of the protection signal generating circuit.

5. The chip area reducing protection circuit according to claim 4, characterized in that: The protection signal generating circuit includes a second AND gate, an RS trigger and a second inverter; The first input end of the second AND gate is connected to the cycle time generating circuit and receives the external circuit abnormality signal, the second input end of the second AND gate receives the reset signal output by the RS trigger, the second AND gate outputs a protection signal, the reset end of the RS trigger is connected to the inverting output end of the last D trigger among the multiple D triggers, the set end of the RS trigger is connected to the inverting output end of the first D trigger among the multiple D triggers, the output end of the RS trigger is connected to the input end of the second inverter, and the output end of the second inverter serves as the second end of the protection signal generating circuit.

6. The chip area reducing protection circuit according to claim 4, characterized in that: The protection signal generating circuit includes a second AND gate, an RS trigger, a second inverter and a third inverter; The first input end of the second AND gate is connected to the cycle time generating circuit and receives the external circuit abnormality signal, the second input end of the second AND gate receives the reset signal output by the RS trigger, the second AND gate outputs a protection signal, the input end of the third inverter is connected to the output end of the last D trigger among the multiple D triggers, the output end of the third inverter is connected to the reset end of the RS trigger, the set end of the RS trigger is connected to the inverting output end of the first D trigger among the multiple D triggers, the output end of the RS trigger is connected to the input end of the second inverter, and the output end of the second inverter serves as the second end of the protection signal generating circuit.

7. The chip area reducing protection circuit according to claim 4, characterized in that: The number of D flip-flops is determined according to the period of the periodic time signal and the preset off time when the external circuit is abnormal.

8. The chip area reducing protection circuit according to claim 4, characterized in that: The timing circuit includes at least two D flip-flops.

9. An analog integrated circuit control chip, characterized in that: A chip area reducing protection circuit comprising the chip area reducing protection circuit as claimed in any one of claims 1 to 8.

10. A power supply circuit, characterized in that: Includes the analog integrated circuit control chip as described in claim 9.

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