NPC Common-Mode Voltage Suppression Method, System and Medium Based on SVPWM

Abstract

The present invention provides a method, system, and medium for suppressing common-mode voltage in an NPC based on SVPWM, relating to the technical field of common-mode voltage suppression. The method comprises: dividing a three-level converter space vector diagram into six sectors, using a zero vector and two large vectors as the basic output voltage vectors for each sector, calculating the action time based on the volt-second balance principle, and establishing an action sequence for the output voltage vectors; performing a primary optimization of the action sequence of the output voltage vectors based on a phase duty cycle method; performing a secondary optimization of the action sequence after the primary optimization, wherein the secondary optimization eliminates vectors that generate common-mode voltage amplitudes exceeding Udc / 6 by constraining switch state combinations; and generating three-phase bridge arm drive signals. The present invention addresses the technical problem that existing modulation strategies often lack sufficient optimization when processing common-mode voltage, resulting in high switching losses under certain operating conditions, reducing the overall efficiency and stability of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of common-mode voltage suppression, and in particular to a method, system and medium for suppressing common-mode voltage of an NPC based on SVPWM. Background Art

[0002] Common-mode voltage refers to the voltage relative to ground. It can generate unnecessary current in electrical equipment, causing system imbalance, reduced efficiency, equipment damage, and electromagnetic interference. Common-mode voltage is particularly prominent in three-level converters due to the rapid switching of currents and high-frequency switching operations. Specifically, some voltage vectors in three-level converters can cause large common-mode voltages. Especially at high output voltages, the common-mode voltage amplitude may exceed the allowable range, causing equipment damage and system instability. Existing modulation strategies are often not sufficiently optimized to handle common-mode voltage, resulting in high switching losses and current fluctuations under certain operating conditions, reducing the overall efficiency and stability of the system. Summary of the Invention

[0003] This application provides an NPC common-mode voltage suppression method, system and medium based on SVPWM, aiming to solve the technical problem that the modulation strategy of the existing technology often lacks sufficient optimization when processing common-mode voltage, resulting in higher switching losses under certain operating conditions, reducing the overall efficiency and stability of the system.

[0004] The first aspect disclosed in the present application provides an NPC common-mode voltage suppression method based on SVPWM, the method comprising: dividing a three-level converter space vector diagram into six sectors, and using a zero vector and two large vectors as basic output voltage vectors for each sector, calculating the action time of each vector based on the volt-second balance principle, and synchronously establishing an action sequence of the output voltage vectors for each sector, wherein the zero vector is a voltage vector whose three-phase output states are all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is the DC bus voltage; performing a primary optimization on the action sequence of the output voltage vector based on a phase duty cycle method; performing a secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common-mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; and generating a three-phase bridge arm drive signal based on the action sequence and action time after the secondary optimization.

[0005] The second aspect disclosed in the present application provides an SVPWM-based NPC common-mode voltage suppression system, which is used for the above-mentioned SVPWM-based NPC common-mode voltage suppression method. The system includes: an action sequence establishment module, which is used to divide the three-level converter space vector diagram into 6 sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector through the volt-second balance principle, and synchronously establish the action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector with a three-phase output state of 0, the large vector is a voltage vector with a modulus equal to 2Udc / 3, and Udc is the DC bus voltage; a primary optimization module, which is used to perform a primary optimization of the action sequence of the output voltage vector based on a phase duty cycle method; a secondary optimization module, which is used to perform a secondary optimization of the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common-mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; and a drive signal generation module, which is used to generate a three-phase bridge arm drive signal based on the action sequence and action time after the secondary optimization.

[0006] According to a third aspect of the present application, a storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the NPC common-mode voltage suppression method based on SVPWM in the first aspect are implemented.

[0007] One or more technical solutions provided in this application have at least the following beneficial effects:

[0008] The three-level converter's spatial vector diagram is divided into six sectors, and the action time of each output voltage vector is calculated using the volt-second balance principle. This optimizes the time allocation of the output voltage vectors in each sector and optimizes the timing of the three-phase output, resulting in a smoother output voltage waveform and reducing harmonics and other undesirable voltage fluctuations. The output voltage vector action sequence is optimized based on the phase duty cycle method, helping the system achieve the required output voltage while avoiding unnecessary switching, reducing internal converter losses, and improving overall system stability. A secondary optimization is performed on the optimized action sequence, constraining the switching state combinations to eliminate vectors that generate common-mode voltage amplitudes exceeding Udc / 6. This effectively limits the common-mode voltage amplitude, reducing electrical noise, equipment damage, or electromagnetic interference caused by excessive common-mode voltage, thereby improving converter reliability and system stability. Based on the optimized action sequence and action time, precise three-phase bridge arm drive signals are generated, ensuring that each bridge arm switches according to the optimized timing. Precise timing control not only optimizes voltage output but also helps avoid timing overlap between bridge arms, reducing current fluctuations and imbalances, and ensuring smooth operation of the electrical system.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A flow chart of the NPC common-mode voltage suppression method based on SVPWM provided in an embodiment of the present application;

[0011] Figure 2 The spatial voltage vector diagram of the three-phase NPC three-level converter in the NPC common-mode voltage suppression method based on SVPWM;

[0012] Figure 3 In the NPC common mode voltage suppression method based on SVPWM, the sector Output voltage vector diagram;

[0013] Figure 4 This is an exemplary application of an NPC three-level converter in a photovoltaic power generation system using an SVPWM-based NPC common-mode voltage suppression method.

[0014] Figure 5 The sector when the phase duty cycle method is not used in the NPC common mode voltage suppression method based on SVPWM The action sequence of internal switch states;

[0015] Figure 6 In the NPC common mode voltage suppression method based on SVPWM, the phase duty cycle method is used to optimize the rear sector for the first time. The action sequence of internal switch states;

[0016] Figure 7 The voltage waveforms of the upper and lower capacitors on the DC side after the first optimized switching sequence are obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM.

[0017] Figure 8 The common-mode voltage waveform of the converter after the first optimized switching sequence is simulated in the NPC common-mode voltage suppression method based on SVPWM.

[0018] Figure 9 This is the waveform of the converter common-mode voltage amplification region after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM;

[0019] Figure 10 The line voltage waveform between the A-phase and B-phase bridge arms after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM;

[0020] Figure 11 The output current waveform of the three-level converter after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM;

[0021] Figure 12 For the NPC common mode voltage suppression method based on SVPWM, the second optimized sector The action sequence of internal switch states;

[0022] Figure 13 The voltage waveforms of the upper and lower capacitors on the DC side after the second optimized switching sequence are obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM.

[0023] Figure 14 The common-mode voltage waveform of the converter after the second optimized switching sequence is simulated in the NPC common-mode voltage suppression method based on SVPWM.

[0024] Figure 15 The line voltage waveform between the A-phase and B-phase bridge arms after the second optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM;

[0025] Figure 16 The output current waveform of the three-level converter after the second optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM;

[0026] Figure 17 This is a schematic diagram of the structure of the NPC common-mode voltage suppression system based on SVPWM provided in an embodiment of the present application.

[0027] Description of reference numerals: action sequence establishing module 10 , primary optimization module 20 , secondary optimization module 30 , driving signal generating module 40 . DETAILED DESCRIPTION

[0028] The embodiments of the present application provide an NPC common-mode voltage suppression method, system, and medium based on SVPWM, thereby solving the technical problem that the modulation strategies of the prior art often lack sufficient optimization when processing common-mode voltage, resulting in higher switching losses under certain operating conditions and reducing the overall efficiency and stability of the system.

[0029] After introducing the basic principles of this application, various non-limiting embodiments of this application will be specifically described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0030] Example 1, as Figure 1As shown, an embodiment of the present application provides an NPC common mode voltage suppression method based on SVPWM, the method comprising:

[0031] The three-level converter space vector diagram is divided into six sectors. A zero vector and two large vectors are used as the basic output voltage vectors for each sector. The action time of each vector is calculated using the volt-second balance principle, and the action sequence of the output voltage vector of each sector is synchronously established. The zero vector is a voltage vector with all three-phase output states at 0, the large vector is a voltage vector with a modulus equal to 2Udc / 3, and Udc is the DC bus voltage.

[0032] For the three-level converter space vector diagram, as shown in Figure 2 As shown, the entire voltage space is divided into 6 sectors, each sector representing a specific voltage output range. These sectors are divided based on phase angle, usually at intervals of 60 degrees. Each sector contains two large vectors and a zero vector. The large vector is a voltage vector with a modulus equal to 2Udc / 3. Udc is the DC bus voltage. In a three-level converter or other types of inverters, Udc is the input DC voltage, often provided by an external power supply (such as a battery or rectifier). It affects the amplitude of the output voltage and the operating performance of the system. The zero vector is a voltage vector with all three phase output states at 0. The sector numbers are distributed in a clockwise direction. Each sector has its own specific output voltage vector. For example, Figure 3 As shown, it is a sector Output voltage vector diagram.

[0033] The volt-second balance principle means that in a control system, the impact of each output voltage vector on the system is balanced based on its action time. Through this principle, it can be guaranteed that within each sampling period, the impact of each voltage vector is proportional to the voltage amplitude. The action time of each vector is calculated based on this principle to ensure that the overall output voltage waveform of the system meets the requirements while maintaining voltage stability.

[0034] The action sequence of the output voltage vector of each sector is synchronously established. That is, the calculated action times of each vector are organized into a sequence to achieve the corresponding output voltage. The output voltage vector sequence of each sector is formed based on the aforementioned action times. The synchronization of the action sequence means that all voltage vectors will change within the same time period, thereby achieving stable output voltage control.

[0035] The action sequence of the output voltage vector is optimized based on the phase duty cycle method.

[0036] The duty cycle is the ratio of the time a switch is in the on state to the total time within a cycle. In power electronics systems, the duty cycle directly affects the output voltage waveform. Based on the principle of the phase duty cycle method, the sequence of the three switching states (N, O, and P) can be optimized without changing the duty cycle (or operation time) of each phase bridge leg, without changing the output voltage of each phase bridge leg. Optimizing the three-phase bridge leg switching state sequence results in the inclusion of a small vector and a middle vector in the basic output voltage vector. Because the phase duty cycle method does not change the operation time of the three switching states (N, O, and P) for each phase, the sum of the midpoint currents generated by the optimized basic output voltage vector remains the same as before optimization. Therefore, although the optimized basic output voltage vector includes the small vector and the middle vector, the sum of the midpoint currents generated by them remains zero.

[0037] The action sequence after the primary optimization is subjected to secondary optimization, wherein the secondary optimization is to exclude vectors that generate common mode voltage amplitudes exceeding Udc / 6 by constraining the switch state combinations.

[0038] The purpose of secondary optimization is to further reduce the amplitude of the common-mode voltage, especially to prevent the common-mode voltage amplitude from exceeding Udc / 6. Udc represents the DC voltage, and Udc / 6 is one-sixth of the DC voltage. Common-mode voltage refers to the average voltage of the three-phase voltage that does not belong to any phase. It usually has an adverse effect on the system's electrical equipment and control systems, especially the motor drive system.

[0039] By constraining the switch state combinations, the secondary optimization excludes voltage vector combinations that may cause the common-mode voltage amplitude to exceed Udc / 6. Specifically, this means that in the selection of voltage vectors and the arrangement of the action sequence, certain inappropriate combinations must be avoided. These combinations may cause voltage imbalance in the three-phase system and thus generate a large common-mode voltage. By setting constraints, it is ensured that in the voltage vector sequence, the combination of switch states does not cause the common-mode voltage to exceed the predetermined limit. For example, by checking the common-mode voltage amplitude of each vector combination, if the amplitude exceeds Udc / 6, the combination is excluded from the sequence, thereby ensuring that the optimized voltage vector sequence meets the system stability requirements and further suppresses the common-mode voltage, controlling the common-mode voltage within a safe range.

[0040] The three-phase bridge arm driving signal is generated according to the action sequence and action time after secondary optimization.

[0041] Based on the action sequence and action time after secondary optimization, the output voltage vector at each moment is first determined. The output voltage vector consists of a zero vector and a large vector. The large vector corresponds to the voltage vector when all three phases are in the P or N output state. The output voltage vector at each moment determines the state that the three-phase bridge arm needs to achieve. Each output voltage vector corresponds to a specific bridge arm switch combination. A time-duty cycle mapping table can be used to determine the specific switch state of each bridge arm at each moment. Based on the output voltage vector at each moment and its corresponding action time, a three-phase bridge arm drive signal is generated within a period. The drive signal controls the opening and closing of the switches based on the state of each phase bridge arm (P, O, N), ensuring that each bridge arm outputs the correct voltage vector at the correct time.

[0042] Taking the application of diode neutral point clamped (NPC) three-level converter in photovoltaic power generation system as an example, the main circuit structure of the system is as follows: Figure 4 As shown, two capacitors of equal capacitance are connected in series between the positive and negative DC busbars. and , their midpoints As the midpoint of the three-level inverter, each phase bridge arm of the inverter has four switching tubes. Taking phase A as an example, the four switching tubes are - , each switch tube is connected in anti-parallel with a freewheeling diode. - , and There are two box diodes connected in series, which are - , and the series connection point of the two series clamping diodes is connected to the midpoint of the three-level inverter. This topology enables each phase to generate three levels, that is, each phase has three state outputs: P, O, and N.

[0043] When the given space voltage vector is located in sector I, such as Figure 5 As shown in the figure, the action sequence of the output voltage vector within a sampling period is given, which is represented by Figure 5 It can be seen that within one sampling period, the switching state of the Phase A arm switches twice; the switching state of the Phase B arm switches four times, jumping directly from the N state to the P state; and the switching state of the Phase C arm switches twice. When the three-phase switching state switches between OOO and PNN, all three arms need to switch simultaneously, increasing the number of switching cycles. Furthermore, when the three-phase switching state switches between PNN and PPN, the switching state of the Phase B arm jumps, causing all four switches in the arm to switch simultaneously, increasing switch damage and preventing smooth switching. To address these issues, the phase duty cycle method is used to optimize the action sequence of the output voltage vector.

[0044] After one optimization, the action sequence is as follows Figure 6 As shown by Figure 6 As can be seen, after using the phase duty cycle method, within one sampling period, the switching state of phase A is adjusted from O→P→O, switching twice; the switching state of phase B is adjusted from N→O→P→O→N, switching four times; and the switching state of phase C is adjusted from N→O→N, switching twice. Clearly, after optimization, the phenomenon of the three-phase switching state jumping directly from N to P is avoided.

[0045] In order to verify the effectiveness of the proposed method, a Figure 4 The corresponding simulation model optimizes the action sequence of the output voltage vector based on the phase duty cycle method, and gives the waveforms of the upper and lower capacitor voltages, common mode voltage, bridge arm line voltage and output current respectively. Figure 7 As shown in the figure, the voltage waveforms of the upper and lower capacitors on the DC side after the first optimization of the switching sequence are shown. It can be seen from the figure that the fluctuation of the upper and lower capacitor voltages is small, and the midpoint voltage remains balanced; Figure 8 As shown in the figure, the common-mode voltage waveform of the converter after the first optimization of the switching sequence is shown in the figure. Figure 9 As shown in Figure 1, the waveform of the converter common-mode voltage amplification region after the first optimization of the switching sequence is shown. As can be seen from the figure, the waveform of the common-mode voltage includes 0, ±Udc / 6 and ±Udc / 3 levels. This simulation result is consistent with the theoretical analysis. Figure 10 As shown in Figure 1, the line voltage waveform between the A-phase and B-phase bridge arms after the first optimization of the switching sequence is shown. As can be seen from the figure, the line voltage waveform contains ±Udc, ±Udc / 2 and 0, which is consistent with the theory. Figure 11 As shown in FIG, the output current waveform of the three-level converter after the first optimization of the switching sequence is obtained. As can be seen from the figure, the amplitude of the output current is equal to the reference given value, and the waveform quality is high.

[0046] according to Figure 6 The given action sequence of the three-phase switch states will cause the basic output voltage vector to include small vectors ONN and PPO, which should be avoided. Therefore, it is necessary to optimize the action sequence of the A, B, and C phase bridge arm switch states of sector I again. After the second optimization, the action sequence of the three-phase switch states is as follows: Figure 12 The second optimization simulation is performed on the action sequence after the first optimization, and the waveforms of the upper and lower capacitor voltages, common mode voltage, bridge arm line voltage and output current are also given. Figure 13 As shown in the figure, the voltage waveforms of the upper and lower capacitors on the DC side after the second optimization of the switching sequence are small, and the midpoint voltage remains balanced. Figure 14 The following figure shows the common mode voltage waveform of the converter after the second optimized switching sequence. Figure 8 、 Figure 9In comparison, the waveform of the common-mode voltage only contains 0 and ±Udc / 6 levels, and the common-mode voltage value is significantly reduced. Therefore, the secondary optimization can further suppress the common-mode voltage; Figure 15 As shown in Figure 1, the line voltage waveform between the A-phase and B-phase bridge arms after the second optimization of the switching sequence is shown. The line voltage waveform in the figure also contains ±Udc, ±Udc / 2 and 0, which is consistent with the theory. Figure 16 The output current waveform of the three-level converter after the second optimized switching sequence is shown in Figure 2. Figure 11 The simulation results are the same, and the waveform quality is high.

[0047] Furthermore, the optimization of the action sequence of the output voltage vector based on the phase duty cycle method includes:

[0048] A time-duty cycle mapping table for the PON state is established for each phase bridge arm; a level step constraint is established, and the state sequence of each phase bridge arm is symmetrically rearranged by the level step constraint, wherein the level step constraint is a constraint to confirm that the switching amplitude of adjacent states does not exceed one level step; and the symmetrical rearrangement result is optimized based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered with the preset sampling period.

[0049] To achieve precise voltage control, a time-duty cycle mapping table needs to be established for the PON state of each phase bridge arm. The function of this mapping table is to record the duty cycle of each state, that is, the proportion of time that the state lasts. The duty cycle directly affects the output voltage waveform and system efficiency. In the mapping table, each bridge arm state (P, O, N) will have a corresponding duty cycle value, which will show the proportion of time each state occupies in each cycle of the system.

[0050] Specifically, based on the voltage output requirements of each bridge arm, we first analyze how long each state (P, O, N) should last within a sampling period. Then, we establish a matrix or table to represent the PON state of each bridge arm at different time points and its corresponding duty cycle. Through these mappings, we can precisely control the switching time of each phase bridge arm, thereby achieving optimized voltage output.

[0051] A level step constraint is a restriction used to control the switching amplitude of voltage states. This constraint requires that when switching between states, the voltage change between adjacent states cannot exceed one level step. In other words, the voltage change cannot exceed the size of a step. A level step typically refers to the amount of change from one voltage value to another. This change limits the transition speed of each state in the system, preventing excessive current surges or voltage fluctuations caused by rapid switching.

[0052] Symmetrical rearrangement involves reordering the state sequence of each phase to ensure that the switching of each state complies with the requirements of the level step constraint. This ensures that the voltage variation between adjacent states is not excessive, thereby preventing system instability due to improper switching. The rearranged sequence ensures that the switching state changes of each phase bridge arm are smooth. Even when the state required by the system changes significantly, the switching process can remain smooth and will not cause any impact on the entire power system.

[0053] Specifically, the various states and switching points of each phase during the voltage change process are first identified, and then it is checked whether each state switch will cause the voltage change between adjacent states to exceed the limit of the level step. If this happens, the order of state switching is readjusted through symmetrical rearrangement to avoid excessive voltage amplitude. Symmetrical rearrangement can use some standard rearrangement algorithms, such as the rearrangement method based on the principle of central symmetry. In this way, it is ensured that the state change of each phase is centrally symmetrical and will not produce an amplitude exceeding the level step.

[0054] The sequence symmetry constraint means that the switching moments of the three phases need to be avoided as much as possible to reduce the generation of common-mode voltage and harmonic interference. By rearranging the switching states of the three phases symmetrically, the switching times of the three phases are adjusted so that they are staggered as much as possible.

[0055] In order to ensure that the switching time of each phase does not overlap, according to the sequence symmetry requirements, the optimization of the symmetrical rearrangement results is performed so that the switching time point of each phase is staggered by the preset sampling period. The preset sampling period is set to at least 1 / 4 of the sampling period, which means that the switching moment of each phase must be within a sampling period and staggered as much as possible by a time interval of 1 / 4 of the period. Specifically, in the rearranged state sequence, for the state change of each phase, if the difference between its switching moment and that of other phases is less than the predetermined 1 / 4 of the sampling period, then optimization is performed to ensure that the switching time of the three phases is staggered.

[0056] Furthermore, the step of establishing a time-duty cycle mapping table of a PON state for each phase bridge arm includes:

[0057] A three-phase bridge arm state duty cycle matrix is established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is as follows:

[0058] ;

[0059] in, Characterization sector The three-phase bridge arm state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

[0060] Specifically, the three-phase bridge arm state duty cycle matrix is as follows:

[0061] ;

[0062] in, Indicates that in a specific sector The voltage state duty cycle of the inner three-phase bridge arm, Indicates the current sector number. , represents one of six sectors, each of which corresponds to a specific voltage vector region.

[0063] is the duty cycle value, which indicates the duty cycle of each phase in the three phases. , Specifically, 、 、 Indicates the duty cycle of phase A, phase B, and phase C in the P state during the sampling period; 、 、 Indicates the duty cycle of phase A, phase B, and phase C in the 0 state during the sampling period; 、 、 Indicates the duty ratio of phases A, B, and C in the N state during the sampling period.

[0064] , which means that the sum of the duty cycles of phases A, B, and C in a complete sampling period is 1, that is, the sum of the duty cycles of all states should be equal to 1. This constraint applies to the duty cycle of each phase.

[0065] To calculate the action time of each state within the sampling period, the action time of each state (P, O, N) can be calculated by multiplying the duty cycle by the sampling period, where yes Phase is in state during the sampling period The action time, Characterizes the duty cycle of phase X in state S during the sampling period is the sampling period.

[0066] In general, the three-phase bridge arm state duty cycle matrix The voltage state of the three-phase bridge arm in each sector is described by representing the duty cycle (P, O, N) of each phase in different states during the sampling period. This matrix helps the control system determine the action time of each state, so that the action time of each state in each sampling period is proportional to its duty cycle, thereby ensuring the balance and stability of the voltage output.

[0067] Furthermore, symmetrically rearranging the state sequence of each phase bridge arm by using the level step constraint includes:

[0068] Generate a state sequence for each phase bridge arm, satisfying the following conditions:

[0069] , ;

[0070] in, Representing time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time The status value of .

[0071] The state sequence is reconstructed into a three-segment structure using a symmetric rearrangement algorithm ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period action time.

[0072] Specifically, a state sequence is generated for each phase bridge arm, satisfying the following conditions:

[0073] , ;

[0074] This condition means that at any time and the moments thereafter Between, status and The difference between the two states (i.e., the amplitude of the state change) should be less than or equal to 1. This constraint ensures the smoothness of the state sequence and avoids excessive changes or jumps. It limits the amplitude of the phase state change, allowing the system to maintain a smooth transition within the sampling period without abrupt state switching. This condition applies to the state sequence generated by each phase bridge arm. The purpose is to ensure a smooth transition of the state sequence throughout the entire time interval. That is, the state change should not exceed one unit step, ensuring a smooth transition of the system and avoiding excessive jumps.

[0075] The state sequence is reconstructed into a three-segment structure using the symmetric rearrangement algorithm, which is expressed as ,in, ,express yes This means that in the entire state sequence, is by The state order in the _ is reversed to achieve mirror symmetry between the beginning and the end of the state. The reverse operation is usually used to optimize the stability of the system, ensure smoother and more symmetrical state switching, and avoid unnecessary fluctuations. The constant state segment means that the phase state remains unchanged in this segment, which helps the system remain stable in this stage and prevents current and voltage fluctuations caused by excessive state switching.

[0076] The duration is determined by and time increments The sum of the calculated express Phase is in state during the sampling period The action time, Represents half of the remaining time of the sampling period, where This increment is the sampling period, which ensures that the time allocation of each state segment is reasonable to avoid excessive state switching and instability.

[0077] Furthermore, the optimization of the symmetric rearrangement result based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered with the preset sampling period includes:

[0078] Apply phase shift to the three-phase bridge arms respectively:

[0079] ;

[0080] in, Characterization Phase timing offset.

[0081] Optimize at the state transition point, and the optimization duration must meet the following requirements:

[0082] ;

[0083] in, Characterization optimization time, Characterizes the dead time of power devices.

[0084] Specifically, phase shifts are applied to the three-phase bridge arms:

[0085] ;

[0086] For each phase, including A, B, and C, there is a time offset , the offset represents the phase The timing offset of phase A is , that is, there is no time offset; for phase B, the time offset , that is, the time of phase B is delayed compared to phase A ; For phase C, the time offset , that is, the time of phase C is delayed compared to phase A This time offset operation is used to adjust the timing relationship between phases to ensure stable operation of the three-phase system. For example, by applying different time offsets to different phases, the switching operation of each phase can be controlled to avoid imbalance or current fluctuations caused by simultaneous switching.

[0087] Optimize at the state transition point, and the optimization duration must meet the following requirements:

[0088] ;

[0089] Specifically, in order to prevent excessive switching or uneven symmetry of power devices during state transition, a dead time is inserted in some cases to optimize the duration. The calculation is done by taking the dead time and The larger value of is used to ensure the minimum time interval, which means that no matter how short the dead time is, the insertion time will be at least 5% of the sampling period. It refers to the time interval between turning off one device and turning on another device to avoid short circuit or current surge. The formula ensures that the inserted dead time is at least the required time to ensure that the switching transition between devices is safe.

[0090] Furthermore, the symmetric rearrangement adopts a centrosymmetric mode.

[0091] Symmetrical rearrangement adopts the central symmetric mode. The central symmetric mode refers to rearrangement or adjustment on the symmetry axis of a reference point. Usually, the position of each state is adjusted symmetrically on the time axis. Specifically, in the central symmetric mode, the change of a state is symmetrically distributed with respect to a center point. In this mode, the center point is usually the middle point of the sampling period or the center of the voltage vector diagram. The state is adjusted symmetrically based on the center. Assuming the sampling period is , then the center point is , the state switching time of each phase is symmetrical with respect to this center point, that is, the switching time of the two phases should be relative to Symmetrical switching is used to avoid switching multiple phases at the same time, thereby reducing voltage or current fluctuations in the system. By symmetrically distributing the switching times between phases, excessive state switching at the same time can be avoided, reducing current surges and maintaining system balance.

[0092] Furthermore, the second optimization of the action sequence after the first optimization includes:

[0093] Small vector combinations that disable specific states, including ; Constrain the state transfer path through the finite state machine and prohibit direct jumps between non-adjacent small vectors.

[0094] Small vector combinations refer to the situation in a three-level converter where a specific combination of states results in small voltage vectors that may not be able to effectively control the motor or load or may cause system instability, e.g. Equal combinations represent combinations of the same voltage direction, but they may result in reduced system efficiency or unbalanced voltage waveforms. Disable small vector combinations of specific states, including ,These small vector combinations may produce undesirable voltage waveforms, or may cause system overheating or damage in some cases. ,Disabling these specific small vector combinations through control strategies aims to ,reduce the nonlinear behavior of the system, avoid the generation of harmonics, and ,improve the reliability and efficiency of the system.

[0095] Finite state machine is a control mechanism based on state transition diagram, which is widely used in digital control systems. It defines each state and the corresponding state transition rules. The state transition path is constrained by the finite state machine to ensure that the transition between states is reasonable and does not violate the stability constraints of the system.

[0096] Adjacent small vectors refer to two voltage vectors in a space vector diagram that can be switched with a small change, without causing significant voltage or current fluctuations. Non-adjacent small vectors refer to voltage vectors with a large gap between them. A direct jump between them could cause system instability or excessive voltage surges. To ensure system stability, a finite state machine (FSM) constrains state transition paths, prohibiting direct jumps between non-adjacent small vectors. Specifically, when the system needs to switch from one voltage vector to another, it must follow the adjacent state switching path and cannot skip intermediate states to transition directly to distant states. Through the control algorithm, the FSM monitors each state transition to ensure that each state transition satisfies the adjacent small vector constraint. For example, if a state is a combination of P and O, the system can only transition within the allowed state range, such as transitioning between P, O, and N, and cannot jump from P to N to avoid large voltage jumps. This constraint helps smooth the switching process and prevents current fluctuations, equipment damage, or additional electromagnetic interference caused by large voltage jumps.

[0097] Furthermore, the three-level converter space vector diagram is divided into six sectors, including:

[0098] The space vector map is divided into 6 sectors at 60° intervals, and each sector is composed of two adjacent large vectors as boundaries and a zero vector as a vertex. The sector numbers are distributed clockwise as follows: .

[0099] A space vector diagram is a planar graph that represents the position of the converter output voltage vector in space. For a three-level converter, the output voltage vector is distributed on a two-dimensional coordinate plane, where each voltage vector represents a specific voltage state, and the direction and magnitude of each voltage vector determine the characteristics of the voltage output.

[0100] The space vector diagram is divided into 6 sectors at 60° intervals, which means that each sector occupies an angular range of 60°. Since the voltage vector of the three-level converter is generally evenly distributed on the space vector diagram, it is balanced to divide it into 6 sectors at 60-degree intervals. The sector division is carried out clockwise. The boundary of each sector is composed of two adjacent large vectors and a zero vector vertex. There is a certain overlapping area between each sector, but the definition of each sector is independent.

[0101] A large vector refers to a voltage vector with a three-phase output state of P or N, typically corresponding to a high voltage level and serving as the primary output state for control. A zero vector represents a neutral state for the three-phase voltage, typically indicating zero output voltage at a specific moment. It is primarily used to adjust the output waveform and balance current and voltage in the system. The boundaries of each sector are determined by adjacent large vectors, with the zero vector serving as a vertex connecting these large vectors, making each sector more clearly defined and independent.

[0102] Sector numbering is carried out in clockwise direction and is distributed as follows: , each sector corresponds to a specific voltage vector combination, which is used to generate control commands, sector From 0° to 60°, sector From 60° to 120°, and so on, the last sector (sector ) from 300° to 360°, completing the division of the space vector diagram. This division method makes the representation of the space vector diagram more systematic, which is helpful for subsequent voltage vector control and optimization.

[0103] In summary, the NPC common-mode voltage suppression method based on SVPWM provided in the embodiments of the present application has the following technical effects:

[0104] The three-level converter's spatial vector diagram is divided into six sectors, and the action time of each output voltage vector is calculated using the volt-second balance principle. This optimizes the time allocation of the output voltage vectors in each sector and optimizes the timing of the three-phase output, resulting in a smoother output voltage waveform and reducing harmonics and other undesirable voltage fluctuations. The output voltage vector action sequence is optimized based on the phase duty cycle method, helping the system achieve the required output voltage while avoiding unnecessary switching, reducing internal converter losses, and improving overall system stability. A secondary optimization is performed on the optimized action sequence, constraining the switching state combinations to eliminate vectors that generate common-mode voltage amplitudes exceeding Udc / 6. This effectively limits the common-mode voltage amplitude, reducing electrical noise, equipment damage, or electromagnetic interference caused by excessive common-mode voltage, thereby improving converter reliability and system stability. Based on the optimized action sequence and action time, precise three-phase bridge arm drive signals are generated, ensuring that each bridge arm switches according to the optimized timing. Precise timing control not only optimizes voltage output but also helps avoid timing overlap between bridge arms, reducing current fluctuations and imbalances, and ensuring smooth operation of the electrical system.

[0105] The second embodiment is based on the same inventive concept as the NPC common mode voltage suppression method based on SVPWM in the above embodiment. Figure 17 As shown, an embodiment of the present application provides an NPC common-mode voltage suppression system based on SVPWM, the system comprising:

[0106] An action sequence establishment module 10 is used to divide the three-level converter space vector diagram into six sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector based on the volt-second balance principle, and synchronously establish the action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector with all three-phase output states being 0, the large vector is a voltage vector with a modulus equal to 2Udc / 3, and Udc is the DC bus voltage; a primary optimization module 20 is used to perform a primary optimization of the action sequence of the output voltage vector based on a phase duty cycle method; a secondary optimization module 30 is used to perform a secondary optimization of the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common-mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; and a drive signal generation module 40 is used to generate a three-phase bridge arm drive signal based on the action sequence and action time after the secondary optimization.

[0107] Furthermore, the system further includes a first optimization module to perform the following operation steps:

[0108] A time-duty cycle mapping table for the PON state is established for each phase bridge arm; a level step constraint is established, and the state sequence of each phase bridge arm is symmetrically rearranged by the level step constraint, wherein the level step constraint is a constraint to confirm that the switching amplitude of adjacent states does not exceed one level step; and the symmetrical rearrangement result is optimized based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered with the preset sampling period.

[0109] Furthermore, the system further includes a duty cycle matrix establishment module to perform the following operation steps:

[0110] A three-phase bridge arm state duty cycle matrix is established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is as follows:

[0111] ;

[0112] in, Characterization sector The three-phase bridge arm state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

[0113] Furthermore, the system further includes a state sequence reconstruction module to perform the following operation steps:

[0114] Generate a state sequence for each phase bridge arm, satisfying the following conditions:

[0115] , ;

[0116] in, Representing time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time Status value.

[0117] The state sequence is reconstructed into a three-segment structure using a symmetric rearrangement algorithm ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period action time.

[0118] Furthermore, the system further includes a second optimization module to perform the following steps:

[0119] Apply phase shift to the three-phase bridge arms respectively:

[0120] ;

[0121] in, Characterization Phase timing offset.

[0122] Optimize at the state transition point, and the optimization duration must meet the following requirements:

[0123] ;

[0124] in, Characterization optimization time, Characterizes the dead time of power devices.

[0125] Furthermore, the symmetric rearrangement adopts a centrosymmetric mode.

[0126] Furthermore, the system further includes a constraint module to perform the following steps:

[0127] Small vector combinations that disable specific states, including ; Constrain the state transfer path through the finite state machine and prohibit direct jumps between non-adjacent small vectors.

[0128] Furthermore, the system further includes a sector division module to perform the following operation steps:

[0129] The space vector map is divided into 6 sectors at 60° intervals, and each sector is composed of two adjacent large vectors as boundaries and a zero vector as a vertex. The sector numbers are distributed clockwise as follows: .

[0130] Through the detailed description of the SVPWM-based NPC common-mode voltage suppression method in the foregoing specification, those skilled in the art can clearly understand the SVPWM-based NPC common-mode voltage suppression system in this embodiment. Since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant details, please refer to the method section.

[0131] In a third embodiment, a storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step of the first embodiment is implemented.

[0132] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The NPC common mode voltage suppression method based on SVPWM is characterized by: The method comprises: The three-level converter space vector diagram is divided into six sectors, and each sector uses a zero vector and two large vectors as basic output voltage vectors. The action time of each vector is calculated using the volt-second balance principle, and the action sequence of the output voltage vector of each sector is simultaneously established. The zero vector is a voltage vector with all three-phase output states 0, the large vector is a voltage vector with a modulus length equal to 2Udc / 3, and Udc is the DC bus voltage. Optimize the action sequence of the output voltage vector based on the phase duty cycle method; Performing a secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; The three-phase bridge arm driving signal is generated according to the action sequence and action time after secondary optimization.

2. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The method of optimizing the action sequence of the output voltage vector based on the phase duty cycle method includes: Establish a time-duty cycle mapping table of the PON state for each phase bridge arm; Establishing a level step constraint, and symmetrically rearranging the state sequence of each phase bridge arm by using the level step constraint, wherein the level step constraint is a constraint for ensuring that the switching amplitude of adjacent states does not exceed one level step; The optimization of the symmetric rearrangement results is performed based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered with the preset sampling period.

3. The NPC common mode voltage suppression method based on SVPWM according to claim 2, characterized in that: The time-duty cycle mapping table of the PON state is established for each phase bridge arm, including: A three-phase bridge arm state duty cycle matrix is established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is as follows: ； in, Characterization sector The three-phase bridge arm state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

4. The NPC common mode voltage suppression method based on SVPWM according to claim 3, characterized in that: The symmetrically rearranging the state sequence of each phase bridge arm by the level step constraint includes: Generate a state sequence for each phase bridge arm, satisfying the following conditions: ， ； in, Representing time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time Status value of The state sequence is reconstructed into a three-segment structure using a symmetric rearrangement algorithm ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period The action time of ,express yes The reverse sequence of is the first half of the state sequence, It is the second half of the state sequence.

5. The NPC common mode voltage suppression method based on SVPWM according to claim 4, characterized in that: The optimization of the symmetric rearrangement result based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered with the preset sampling period includes: Apply phase shift to the three-phase bridge arms respectively: ； in, Characterization Phase timing offset; Optimize at the state transition point, and the optimization duration must meet the following requirements: ； in, Characterization optimization time, Characterize the dead time of power devices, The larger value is taken.

6. The NPC common mode voltage suppression method based on SVPWM according to claim 2, characterized in that: The symmetric rearrangement adopts a centrosymmetric mode.

7. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The second optimization of the action sequence after the first optimization includes: Small vector combinations that disable specific states, including ; The state transfer path is constrained by the finite state machine, and direct jumps between non-adjacent small vectors are prohibited.

8. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The three-level converter space vector diagram is divided into 6 sectors, including: The space vector map is divided into 6 sectors at 60° intervals, and each sector is composed of two adjacent large vectors as boundaries and a zero vector as a vertex. The sector numbers are distributed clockwise as follows: .

9. The NPC common mode voltage suppression system based on SVPWM is characterized by: For implementing the NPC common-mode voltage suppression method based on SVPWM according to any one of claims 1 to 8, the system comprises: an action sequence establishment module, configured to divide the three-level converter space vector diagram into six sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector using the volt-second balance principle, and synchronously establish an action sequence for the output voltage vectors of each sector, wherein the zero vector is a voltage vector with all three-phase output states at 0, the large vector is a voltage vector with a modulus equal to 2Udc / 3, and Udc is the DC bus voltage; A primary optimization module is used to optimize the action sequence of the output voltage vector based on the phase duty cycle method; A secondary optimization module is used to perform secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate common mode voltage amplitudes exceeding Udc / 6 by constraining the switch state combination; The drive signal generation module is used to generate a three-phase bridge arm drive signal according to the action sequence and action time after secondary optimization.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the NPC common-mode voltage suppression method based on SVPWM according to any one of claims 1 to 8 are implemented.

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