Power supply circuit with small size and wide application range

Abstract

The invention relates to the technical field of power supply circuits, in particular to a power supply circuit with a small size and a wide application range. An integrated circuit control chip of the power supply circuit comprises a working frequency control circuit, and after the working frequency control circuit is externally connected with an adjusting resistor or a square wave signal through a pin, the frequency of an output signal can be controlled by setting adjusting resistors with different resistance values, so that the working frequency of the power supply circuit is controlled, and the service life of the power supply circuit is prolonged. Or by accessing square wave signals with different frequencies, the working frequency of the power supply circuit is controlled, so that the size of the power supply circuit is reduced, and the application range of the power supply circuit is enlarged.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a power supply circuit with small volume and wide application range. Background Art

[0002] The power supply circuit in the prior art usually includes an integrated circuit control chip and an external power circuit, and the operating frequency of the power supply circuit is determined by the integrated circuit control chip. When the circuit system contains only one integrated circuit control chip working alone, the operating frequency can be controlled by an external chip adjustment resistor. When the circuit system contains multiple integrated circuit control chips working simultaneously, a square wave signal is usually used to control the multiple integrated circuit control chips simultaneously, so that the operating frequencies of the power supply circuits controlled by the multiple integrated circuit control chips are the same, thereby ensuring the consistency of the operation of each power supply circuit in the circuit system; and the integrated circuit control chip of the power supply circuit in the prior art usually has two pins, which are used to control the operating frequency of the power supply circuit by an external adjustment resistor and a square wave signal respectively, which is obviously not in line with the development trend of integration and miniaturization of power supply circuits. Summary of the invention

[0003] In view of this, the present invention provides a power supply circuit with a small volume and a wide range of applications to solve the technical problem in the prior art that the integrated circuit control chip of the power supply circuit uses two pins to control the operating frequency of the power supply circuit, resulting in a larger volume of the power supply circuit.

[0004] The technical solution provided by the present invention is as follows: In a first aspect, the present invention provides an operating frequency control circuit, comprising: Input pin, used to receive external input square wave signal or connect external adjustment resistor; a first control circuit, a first end of which is connected to the input pin, a second end of which is connected to the external power supply, and a third end of which is grounded, and is used to obtain a signal with the same frequency as the square wave signal or a first low-level signal according to whether the input signal of the input pin is a square wave signal, and output a second low-level signal or a high-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal; a second control circuit, a first end of which is connected to the fourth end of the first control circuit, a second end of which is connected to the input pin, a third end of which is connected to the external power supply, and a fourth end of which is grounded, and is used to output a third low-level signal or a periodic output signal according to the second low-level signal or the high-level signal output by the first control circuit; An output circuit, whose first end is connected to the fifth end of the second control circuit, whose second end is connected to the fourth end of the first control circuit, whose third end is connected to the fifth end of the first control circuit, and whose fourth end is connected to the sixth end of the first control circuit, is used to output an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjusting resistor according to a signal with the same frequency as the square wave signal or a first low level signal, a second low level signal or a high level signal, an inverted signal of the second low level signal or the high level signal and a third low level signal or a periodic output signal.

[0005] In an optional implementation, the first control circuit includes: A signal detection circuit, wherein a first end thereof is connected to an input pin, a second end thereof is connected to an external power supply, a third end thereof is grounded, and a fourth end thereof is connected to a fourth end of an output circuit, and is used to detect an input signal of the input pin, and when the input signal is a square wave signal, output an output signal having the same frequency as the square wave signal, and when the input signal is not a square wave signal, output a first low level signal; A switch control circuit, a first end of which is connected to the fourth end of the signal detection circuit, a second end of which is connected to an external power supply, a third end of which is grounded, a fourth end of which is connected to an input pin, a fifth end of which is connected to the first end of the second control circuit and the second end of the output circuit, and a sixth end of which is connected to the third end of the output circuit, is used to output a second low-level signal when the signal detection circuit outputs an output signal with the same frequency as the square wave signal, and to output a high-level signal when the signal detection circuit outputs a first low-level signal.

[0006] In an optional implementation, the second control circuit includes: a switch circuit, a first end of which is connected to the fourth end of the first control circuit, a second end of which is connected to an external power supply, and a third end of which is connected to the input pin; A voltage control circuit, a first end of which is connected to a first fixed voltage, and a second end and a third end of which are connected to a fourth end of the switch circuit; a first charging circuit, a first end of which is connected to the fourth end of the switch circuit, a second end of which is connected to the external power supply, and a third end of which is grounded; a second charging circuit, wherein a first end of the second charging circuit is connected to the fourth end of the first charging circuit, a second end of the second charging circuit is connected to the second fixed voltage, a third end of the second charging circuit is connected to the external power supply, a fourth end of the second charging circuit is grounded, and a fifth end of the second charging circuit is connected to the fifth end of the first charging circuit and the first end of the output circuit; When the first control circuit outputs a second low-level signal, the switch circuit turns off the first charging circuit, and the second charging circuit outputs a third low-level signal. When the first control circuit outputs a high-level signal, the first charging circuit operates under the control of the switch circuit and the voltage control circuit, and the first charging circuit outputs a periodic output signal. The second charging circuit outputs an output signal with the same period as the periodic output signal.

[0007] In an optional implementation, the signal detection circuit includes a first inverter, a first AND gate, a first switch tube, a second switch tube, a first resistor and a first capacitor, and the switch control circuit includes a third switch tube, a fourth switch tube, a second resistor, a second capacitor, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a third inverter and a fourth inverter; The input end of the first inverter is connected to the input pin, the output end of the first inverter is connected to the first end of the first switch tube, the first input end of the first AND gate and the first end of the second switch tube, the second end of the first switch tube is connected to the external power supply, the third end of the first switch tube is connected to the second input end of the first AND gate, one end of the first capacitor and one end of the first resistor, the other end of the first resistor is connected to the second end of the second switch tube, the third end of the second switch tube is connected to the other end of the first capacitor and is grounded; the output end of the first AND gate is connected to the first end of the third switch tube, the first end of the fourth switch tube and the fourth end of the output circuit; The second end of the third switch tube is connected to the external power supply, the third end of the third switch tube is connected to one end of the second resistor, the other end of the second resistor is connected to the second end of the fourth switch tube, one end of the second capacitor and the input end of the second inverter, the third end of the fourth switch tube is connected to the second end of the second capacitor and is grounded, the output end of the second inverter is connected to the first input end of the first NAND gate and the first input end of the third NAND gate, the second input end of the first NAND gate is connected to the input pin, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the third NAND gate and the input end of the third inverter, the output end of the second NAND gate is connected to the second input end of the third NAND gate, the output end of the third inverter is connected to the input end of the fourth inverter and the third end of the output circuit, and the output end of the fourth inverter is connected to the first end of the second control circuit and the second end of the output circuit.

[0008] In an optional implementation, the switch circuit includes a fifth switch tube and an eighth switch tube, the voltage control circuit includes a first comparator, the first charging circuit includes a sixth switch tube, a seventh switch tube, a ninth switch tube and a third capacitor, and the second charging circuit includes a second comparator, a tenth switch tube, a fourth capacitor, a fifth inverter and a first current source; The first end of the fifth switch tube is connected to the first end of the eighth switch tube, the fourth end of the first control circuit and the second end of the output circuit, the second end of the fifth switch tube is connected to the external power supply, the third end of the fifth switch tube is connected to the first end and the second end of the sixth switch tube, the first end of the seventh switch tube, the output end of the first comparator, the negative input end of the first comparator and the second end of the eighth switch tube, and the third end of the eighth switch tube is connected to the input pin; the positive input end of the first comparator is connected to the first fixed voltage; The third end of the sixth switch tube is connected to the second end of the seventh switch tube and the external power supply, the third end of the seventh switch tube is connected to the positive input end of the second comparator, one end of the third capacitor and the first end of the ninth switch tube, the negative input end of the second comparator is connected to the second fixed voltage, the output end of the second comparator is connected to the first end of the tenth switch tube, the other end of the third capacitor is connected to the second end of the ninth switch tube and is grounded, the second end of the tenth switch tube is connected to the output end of the first current source, the input end of the fifth inverter and one end of the fourth capacitor, the other end of the fourth capacitor is connected to the third end of the tenth switch tube and is grounded, the output end of the fifth inverter is connected to the third end of the ninth switch tube and the first end of the output circuit, and the input end of the first current source is connected to the external power supply.

[0009] In an optional embodiment, the output circuit includes a second AND gate, a third AND gate and a first OR gate, the first input end of the second AND gate is connected to the fifth end of the second control circuit, the second input end of the second AND gate is connected to the fourth end of the first control circuit, the first input end of the third AND gate is connected to the fifth end of the first control circuit, the second input end of the third AND gate is connected to the sixth end of the first control circuit, the output end of the second AND gate is connected to the first input end of the first OR gate, the output end of the third AND gate is connected to the second input end of the first OR gate, and the output end of the first OR gate outputs an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjustment resistor.

[0010] In an optional embodiment, the first fixed voltage is less than the conversion threshold voltage of the first inverter; when the external power supply charges the second capacitor through the third switch tube and the second resistor, within one cycle of the square wave signal, the voltage across the second capacitor is less than the conversion threshold voltage of the second inverter.

[0011] In an optional implementation, the lowest frequency of the output signal of the output circuit is controlled according to parameters of the second resistor and the second capacitor.

[0012] In a second aspect, the present invention provides an integrated circuit control chip, the chip comprising the operating frequency control circuit of the first aspect of the present invention and any one of the first aspects.

[0013] In a third aspect, the present invention provides a power supply circuit with a small volume and a wide range of applications. The power supply circuit includes the integrated circuit control chip of the second aspect of the present invention.

[0014] The technical solution of the present invention has the following advantages: In the present invention, after the operating frequency control circuit realizes an external adjustment resistor or a square wave signal through an input pin, the frequency of the output signal of the operating frequency control circuit can be controlled by setting an adjustment resistor with different resistance values, or by connecting square wave signals with different frequencies to control the frequency of the output signal of the operating frequency control circuit, thereby reducing the use of pins.

[0015] In the present invention, the lowest frequency of the output signal of the operating frequency control circuit is controlled by controlling the parameters of the second resistor and the second capacitor.

[0016] In the present invention, the integrated circuit control chip of the power supply circuit includes an operating frequency control circuit. After the operating frequency control circuit realizes an external adjustment resistor or a square wave signal through a pin, the frequency of the output signal can be controlled by setting adjustment resistors with different resistance values ​​to realize the control of the operating frequency of the power supply circuit, or the operating frequency of the power supply circuit can be controlled by connecting square wave signals of different frequencies, thereby reducing the volume of the power supply circuit and increasing the application scope of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a structural block diagram of an operating frequency control circuit in an embodiment of the present invention; Figure 2 is a structural block diagram of an operating frequency control circuit in another embodiment of the present invention; Figure 3 Schematic diagram of the structure of the operating frequency control circuit in an embodiment of the present invention; Figure 4 is a structural block diagram of an operating frequency control circuit in another embodiment of the present invention; Figure 5 This is a waveform diagram of an output signal when the input pin of the operating frequency control circuit in an embodiment of the present invention is connected to an adjustment resistor; Figure 6 This is a waveform diagram of an output signal when a square wave signal is input to an input pin of the operating frequency control circuit in an embodiment of the present invention; Figure 7 It is a structural block diagram of a power supply circuit with a small volume and a wide application range in an embodiment of the present invention; Figure 8 It is a structural block diagram of a power supply circuit with small volume and wide application range in another embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] An embodiment of the present invention provides an operating frequency control circuit, such as Figure 1As shown, the circuit includes: an input pin G1 / G2, which is used to receive an external square wave signal or connect an external adjustment resistor RL; a first control circuit 1, whose first end is connected to the input pin G1 / G2, whose second end is connected to an external power supply, and whose third end is grounded, and is used to obtain a signal with the same frequency as the square wave signal or a first low-level signal according to whether the input pin G1 / G2 is a square wave signal, and output a second low-level signal or a high-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal; a second control circuit 2, whose first end is connected to the fourth end of the first control circuit 1, whose second end is connected to the input pin G1 / G2, whose third end is connected to the external power supply, and whose fourth end is grounded, and is used to obtain a signal with the same frequency as the square wave signal or a first low-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal. A third low level signal or a periodic output signal is output according to the second low level signal or the high level signal output by the first control circuit 1; an output circuit 3, a first end of which is connected to the fifth end of the second control circuit 2, a second end of which is connected to the fourth end of the first control circuit 1, a third end of which is connected to the fifth end of the first control circuit 1, and a fourth end of which is connected to the sixth end of the first control circuit 1, and is used to output an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjusting resistor according to a signal with the same frequency as the square wave signal or the first low level signal, the second low level signal or the high level signal, the inverted signal of the second low level signal or the high level signal, and the third low level signal or the periodic output signal.

[0024] It should be noted that the input pin G1 / G2 refers to a pin, which can be connected to an adjustment resistor or receive an externally input square wave signal. Thus, the operating frequency control circuit can receive a square wave signal or connect an adjustment resistor through an input pin, wherein, when a square wave signal is received, the first control circuit 1, the second control circuit 2 and the output circuit 3 process the input signal to output an output signal with the same frequency as the square wave signal; when the adjustment resistor is connected, if the resistance of the adjustment resistor changes, the first control circuit 1, the second control circuit 2 and the output circuit 3 process the output signal with a changed frequency. Thus, the operating frequency control circuit can control the frequency of the output signal by inputting square wave signals of different frequencies or connecting adjustment resistors of different resistance values. When the operating frequency control circuit is applied to the integrated circuit control chip of the power supply circuit, the operating frequency of the power supply circuit is controlled.

[0025] In the present invention, after the operating frequency control circuit realizes an external adjustment resistor or a square wave signal through an input pin, the frequency of the output signal of the operating frequency control circuit can be controlled by setting an adjustment resistor with different resistance values, or by connecting square wave signals with different frequencies to control the frequency of the output signal of the operating frequency control circuit, thereby reducing the use of pins.

[0026] In an optional embodiment, if Figure 2 As shown, the first control circuit 1 includes: a signal detection circuit 11, a first end of which is connected to the input pin, a second end of which is connected to the external power supply, a third end of which is grounded, and a fourth end of which is connected to the fourth end of the output circuit. The signal detection circuit 11 is used to detect the input signal of the input pin and output a corresponding output signal. When the input signal is a square wave signal, the output signal is output with the same frequency as the square wave signal, and when the input signal is not a square wave signal, the first low level signal is output; a switch control circuit 12, a first end of which is connected to the fourth end of the signal detection circuit 11, a second end of which is connected to the external power supply, a third end of which is grounded, a fourth end of which is connected to the input pin, a fifth end of which is connected to the first end of the second control circuit and the second end of the output circuit, and a sixth end of which is connected to the third end of the output circuit. The switch control circuit 12 is used to output a second low level signal when the signal detection circuit 11 outputs an output signal with the same frequency as the square wave signal, and output a high level signal when the signal detection circuit 11 outputs the first low level signal.

[0027] Specifically, Figure 3 As shown, the signal detection circuit includes a first inverter NOT1, a first AND gate AND1, a first switch tube M1, a second switch tube M2, a first resistor R1 and a first capacitor C1, and the switch control circuit includes a third switch tube M3, a fourth switch tube M4, a second resistor R2, a second capacitor C2, a second inverter NOT2, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a third inverter NOT3 and a fourth inverter NOT4; The input end of the first inverter NOT1 is connected to the input pin, the output end of the first inverter NOT1 is connected to the first end of the first switch tube M1, the first input end of the first AND gate AND1 and the first end of the second switch tube M2, the second end of the first switch tube M1 is connected to the external power supply, the third end of the first switch tube M1 is connected to the second input end of the first AND gate AND1, one end of the first capacitor C1 and one end of the first resistor R1, the other end of the first resistor R1 is connected to the second end of the second switch tube M2, the third end of the second switch tube M2 is connected to the other end of the first capacitor C1 and grounded; the output end of the first AND gate AND1 is connected to the first end of the third switch tube M3, the first end of the fourth switch tube M4 and the fourth end of the output circuit; The second end of the third switch tube M3 is connected to the external power supply, the third end of the third switch tube M3 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the second end of the fourth switch tube M4, one end of the second capacitor C2 and the input end of the second inverter NOT2, the third end of the fourth switch tube M4 is connected to the second end of the second capacitor C2 and is grounded, the output end of the second inverter NOT2 is connected to the first input end of the first NAND gate NAND1 and the first input end of the third NAND gate NAND3, the second input end of the first NAND gate NAND1 is connected to the input pin, the output end of the first NAND gate NAND1 is connected to the first input end of the second NAND gate NAND2, the second input end of the second NAND gate NAND2 is connected to the output end of the third NAND gate NAND3 and the input end of the third inverter NOT3, the output end of the second NAND gate NAND2 is connected to the second input end of the third NAND gate NAND3, the output end of the third inverter NOT3 is connected to the input end of the fourth inverter NOT4 and the third end of the output circuit, and the output end of the fourth inverter NOT4 is connected to the first end of the second control circuit and the second end of the output circuit.

[0028] Specifically, by setting a signal detection circuit 11 and a switch control circuit 12 in the first control circuit 1, and by setting the above components in the signal detection circuit 11 and the switch control circuit 12, the charging and discharging process of the first capacitor C1 in the signal detection circuit 11 and the coordinated work with other components of the signal detection circuit 11 make it possible to output a level signal of the same frequency when the input is a square wave signal; a second capacitor C2 is set in the switch control circuit 12, and when the external power supply charges the second capacitor C2 through the third switch tube M3 and the second resistor R2, within one cycle of the square wave signal, the voltage across the second capacitor C2 is less than the conversion threshold voltage of the second inverter NOT2, thereby making the output of the switch control circuit unchanged. The specific working methods of the various components in the signal detection circuit and the switch control circuit are described below.

[0029] In an optional embodiment, if Figure 4As shown, the second control circuit 2 includes: a switch circuit 21, a first end of which is connected to the fourth end of the first control circuit 1, a second end of which is connected to the external power supply, and a third end of which is connected to the input pin G1 / G2; a voltage control circuit 22, a first end of which is connected to the first fixed voltage V1, and a second end and a third end of which are connected to the fourth end of the switch circuit 21; a first charging circuit 23, a first end of which is connected to the fourth end of the switch circuit 21, a second end of which is connected to the external power supply, and a third end of which is grounded; a second charging circuit 24, a first end of which is connected to the fourth end of the first charging circuit 23, a second end of which is connected to the second fixed voltage V2, and a third end of which is grounded. The third end is connected to an external power supply, the fourth end is grounded, and the fifth end is connected to the fifth end of the first charging circuit 23 and the first end of the output circuit; when the first control circuit 1 outputs a second low level signal, the switch circuit 21 turns off the first charging circuit 23, and the second charging circuit 24 outputs a third low level signal; when the first control circuit 1 outputs a high level signal, the first charging circuit 23 operates under the control of the switch circuit 21 and the voltage control circuit 22, the first charging circuit 23 outputs a periodic output signal, and the second charging circuit 24 outputs an output signal with the same period as the periodic output signal.

[0030] like Figure 3 As shown, the switch circuit includes a fifth switch tube M5 and an eighth switch tube M8, the voltage control circuit includes a first comparator CMP1, the first charging circuit includes a sixth switch tube M6, a seventh switch tube M7, a ninth switch tube M9 and a third capacitor C3, and the second charging circuit includes a second comparator CMP2, a tenth switch tube M10, a fourth capacitor C4, a fifth inverter NOT5 and a first current source B1; A first end of the fifth switch tube M5 is connected to a first end of the eighth switch tube M8, a fourth end of the first control circuit and a second end of the output circuit; a second end of the fifth switch tube M5 is connected to an external power supply; a third end of the fifth switch tube M5 is connected to a first end and a second end of the sixth switch tube M6, a first end of the seventh switch tube M7, an output end of the first comparator CMP1, a negative input end of the first comparator CMP1 and a second end of the eighth switch tube M8; a third end of the eighth switch tube M8 is connected to an input pin; a positive input end of the first comparator CMP1 is connected to a first fixed voltage V1; The third end of the sixth switch tube M6 is connected to the second end of the seventh switch tube M7 and the external power supply, the third end of the seventh switch tube M7 is connected to the positive input end of the second comparator CMP2, one end of the third capacitor C3 and the first end of the ninth switch tube M9, the negative input end of the second comparator CMP2 is connected to the second fixed voltage, the output end of the second comparator CMP2 is connected to the first end of the tenth switch tube, the other end of the third capacitor C3 is connected to the second end of the ninth switch tube M9 and is grounded, the second end of the tenth switch tube is connected to the output end of the first current source B1, the input end of the fifth inverter NOT5 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is connected to the third end of the tenth switch tube and is grounded, the output end of the fifth inverter NOT5 is connected to the third end of the ninth switch tube M9 and the first end of the output circuit, and the input end of the first current source B1 is connected to the external power supply.

[0031] Specifically, by providing a first charging circuit including a third capacitor and a second charging circuit including a fourth capacitor in the second control circuit, during the circuit operation, the third capacitor and the fourth capacitor are continuously charged and discharged, thereby cooperating with other structures in the second control circuit so that the second control circuit outputs a constant signal when the input pin is connected to a square wave signal, and outputs a periodically changing signal when the input pin is connected to an adjustment resistor. The specific working mode of each component in the second control circuit is described below.

[0032] In an optional embodiment, if Figure 3 As shown, the output circuit 3 includes a second AND gate AND2, a third AND gate AND3 and a first OR gate OR1, a first input end of the second AND gate AND2 is connected to the fifth end of the second control circuit 2, a second input end of the second AND gate AND2 is connected to the fourth end of the first control circuit 1, a first input end of the third AND gate AND3 is connected to the fifth end of the first control circuit 1, a second input end of the third AND gate AND3 is connected to the sixth end of the first control circuit 1, an output end of the second AND gate AND2 is connected to the first input end of the first OR gate OR1, an output end of the third AND gate AND3 is connected to the second input end of the first OR gate OR1, and an output end of the first OR gate OR1 outputs an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjustment resistor.

[0033] Specifically, by setting the second AND gate AND2, the third AND gate AND3 and the first OR gate OR1 in the output circuit, and receiving the output signal of the signal detection circuit 11, the two output signals of the switch control circuit 12 and the output signal of the second charging circuit 24, a periodic output signal can be output. The specific working mode of each component in the output circuit is described below.

[0034] Specifically, Figure 3As shown, the working principle of the operating frequency control circuit is described below when the input pin is connected to the adjustment resistor and a square wave signal is input.

[0035] (i) When the input pin is connected to the regulating resistor, the input pin G1 / G2 is grounded through the regulating resistor RL, that is, the input pin G1 / G2 is at a low level. Therefore, at this time, the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all at a low level. The first inverter NOT1 outputs a high level, the first switch tube M1 is turned off, the second switch tube M2 is turned on, and the first input end of the first AND gate AND1 is pulled low through the first resistor R1 and the second switch tube M2. Therefore, the output signal CL1 of the first AND gate AND1 is always at a low level. At this time, the third switch tube M3 is turned on, and the fourth switch tube M4 is turned on. The input power source VIN is turned off, therefore, the input power source VIN charges the second capacitor C2 through the third switch tube M3 and the second resistor R2. After charging for more than one cycle, the terminal voltage of the second capacitor C2 exceeds the conversion threshold voltage VT of the second inverter NOT2, and the second inverter NOT2 outputs a low level. Since the first input terminal of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level, therefore, the third NAND gate NAND3 outputs a high level, and the second NAND gate NAND2 outputs a low level. Therefore, the output signal P1 of the third inverter NOT3 is at a low level, and the output signal P2 of the fourth inverter NOT4 is at a low level. is high level.

[0036] High level output signal After being input into the fifth switch tube M5 and the eighth switch tube M8, the fifth switch tube M5 is turned off, and the eighth switch tube M8 is turned on. At this time, the control terminal voltages of the sixth switch tube M6 and the seventh switch tube M7 are pulled down through the eighth switch tube M8 and the regulating resistor RL, and the sixth switch tube M6 and the seventh switch tube M7 are turned on, and current flows through the regulating resistor RL. At this time, under the regulation of the first comparator CMP1, the voltage at point D is equal to the first fixed voltage V1. Since the drain-source voltage difference of the eighth switch tube M8 is extremely small, it can be obtained that the voltage of the input pin G1 / G2=the voltage at point D = the first fixed voltage V1. Firstly, since the first fixed voltage V1 is less than the switching threshold voltage VT of the inverter, the first fixed voltage V1 is still at a low level relative to the first inverter NOT1, that is, when the eighth switch tube M8 is turned on and the voltage of the input pin G1 / G2 is equal to the first fixed voltage V1, the output signal of the first control circuit 1 is not affected. Secondly, when the eighth switch tube M8 is turned on and the voltage of the input pin G1 / G2 is equal to the first fixed voltage V1, the current flowing through the adjustment resistor RL = the current flowing through the sixth switch tube M6 = Since the sixth switch tube M6 and the seventh switch tube M7 form a 1:N current mirror, the current flowing through the seventh switch tube M7 is , since there is no electricity in the third capacitor C3 during the first cycle when the circuit is powered on, its terminal voltage VC is less than the second fixed voltage V2, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, the current I1 output by the first current source B1 charges the fourth capacitor C4, and the terminal voltage of the fourth capacitor C4 gradually increases to a high level state, so at this time, the output signal CL2 of the fifth inverter NOT5 is a low level, the ninth switch tube M9 is turned off, the current I2 charges the third capacitor C3, and the terminal voltage VC of the third capacitor C3 gradually increases. After the first time t1, the terminal voltage VC increases to be greater than the second fixed voltage V2, the second comparator CMP2 outputs a high level, the tenth switch tube M10 is turned on, the input end of the fifth inverter NOT5 is instantly pulled down through the tenth switch tube M10, and the output signal of the fifth inverter NOT5 is CL2 switches to a high level, the ninth switch tube M9 is turned on, the terminal voltage VC of the third capacitor C3 is instantly pulled down through the ninth switch tube M9, the output of the second comparator CMP2 switches to a low level, the tenth switch tube M10 is turned off, and the current I1 output by the first current source B1 charges the fourth capacitor C4. After the second time t2, the terminal voltage of the fourth capacitor C4 gradually increases to a high level state. Before the terminal voltage of the fourth capacitor C4 increases to a high level state greater than the conversion threshold voltage VT of the fifth inverter NOT5, the fifth inverter NOT5 always outputs a high level, the ninth switch tube M9 is always in a conducting state, and the terminal voltage VC of the third capacitor C3 is always in a low level state. After the terminal voltage of the fourth capacitor C4 increases to a high level state, the output signal CL2 of the fifth inverter NOT5 switches to a low level again, and the circuit enters the next cycle.

[0037] Afterwards, it can be seen from the structure of the output circuit 3 that when the signal P1 is at a low level, the signal When the signal CL1 is at a high level and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. At this time, the waveform diagram when the adjustment resistor RL is connected can be obtained, as shown in FIG. Figure 5 shown.

[0038] From the above analysis, we can see that the first , the second time Therefore, the second time t2 is a fixed value, and the first time t1 can be controlled by setting the adjustment resistor RL with different resistance values, thereby realizing the control of the operating frequency of the power supply circuit.

[0039] (ii) When the input pin G1 / G2 is connected to a square wave signal, two cases are introduced; (1) The square wave signal is connected to the chip no later than the input power VIN: (i) When the square wave signal is initially at a low level, the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all at a low level, the first inverter NOT1 outputs a high level, the first switch tube M1 is turned off, and the second switch tube M2 is turned on. Since there is no charge in the first capacitor C1 during the first cycle when the circuit is powered on, the first input end of the first AND gate AND1 is instantly pulled down through the first resistor R1 and the second switch tube M2, and the output signal CL1 of the first AND gate AND1 is at a low level. At this time, the third switch tube M3 is turned on, and the fourth switch tube M4 is turned off. Therefore, the input power supply VIN charges the second capacitor C2 through the third switch tube M3 and the second resistor R2. , the second resistor R2 and the second capacitor C2 are designed so that within one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2. Therefore, it can be obtained that the input end of the second inverter NOT2 is at a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input end of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level. At this time, if the third NAND gate NAND3 is at a low level in the initial state, the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at a high level, and the output signal P2 of the fourth inverter NOT4 is at a low level. is low level, therefore, the fifth switch tube M5 is turned on, the eighth switch tube M8 is turned off, the control terminal voltages of the sixth switch tube M6 and the seventh switch tube M7 are pulled up through the fifth switch tube M5, the sixth switch tube M6 and the seventh switch tube M7 are turned off, since in the first cycle when the circuit is powered on, there is no charge in the third capacitor C3, so its terminal voltage VC is less than the second fixed voltage V2, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, the current I1 output by the first current source B1 charges the fourth capacitor C4, and the terminal voltage of the fourth capacitor C4 gradually increases to a high level state, so at this time, the output signal CL2 of the fifth inverter NOT5 is a low level. At this time, it can be seen from the structure of the output circuit 3 that when the signal P1 is a high level, the signal When the signal CL1 is low and the signal CL2 is low, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is low; if the third NAND gate NAND3 is high in the initial state, the second NAND gate NAND2 outputs a low-high level, and the third NAND gate NAND3 still outputs a high level. At this time, the output signal P1 of the third inverter NOT3 is low, and the output signal P2 of the fourth inverter NOT4 is low. is high level, therefore, the fifth switch tube M5 is turned off, and the eighth switch tube M8 is turned on. From the analysis in (I), it can be seen that the output signal CL2 of the fifth inverter NOT5 first outputs a low level, then a high level, and then a low level. At this time, from the structure of the output circuit 3, it can be seen that when the signal P1 is low level, the signal When the signal CL1 is high and the signal CL2 is low, the output signal CL of the first OR gate OR1 (ie, the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5, and finally the output signal CL of the first OR gate OR1 is also low.

[0040] When the square wave signal is switched from a low level to a high level, the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all switched to a high level, the first inverter NOT1 outputs a low level, the first switch tube M1 is turned on, the second switch tube M2 is turned off, and the input power VIN charges the first capacitor C1 through the first switch tube M1. At this time, since the first inverter NOT1 outputs a low level, the output signal CL1 of the first AND gate AND1 is also a low level. At this time, the third switch tube M3 is turned on, and the fourth switch tube M4 is turned off. Therefore, the input power VIN is charged through the third switch tube M3 and the second resistor R 2 charges the second capacitor C2. Since the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal, it can be obtained that the input end of the second inverter NOT2 is still at a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input end of the first NAND gate NAND1 is at a high level, the first NAND gate NAND1 outputs a low level. Therefore, it can be obtained that the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is a high level, and the output signal P2 of the fourth inverter NOT4 is a low level. is low level; therefore, the fifth switch tube M5 is turned on, the sixth switch tube M6 and the seventh switch tube M7 are turned off, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, and the terminal voltage of the fourth capacitor C4 is in a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is low level; at this time, it can be seen from the structure of the output circuit 3 that when the signal P1 is high level, the signal When the signal CL1 is at a low level and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (ie, the output signal of the operating frequency control circuit) is at a low level.

[0041] When the square wave signal is switched from a high level to a low level, the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all switched to a low level, the first inverter NOT1 outputs a high level, the first switch tube M1 is turned off, the second switch tube M2 is turned on, the first capacitor C1 is slowly discharged through the first resistor R1 and the second switch tube M2, and the terminal voltage of the first capacitor C1 is first maintained at a high level for a period of time and then switched to a low level state. Therefore, the first AND gate AND1 outputs a high level for a period of time and then switches to a low level. When the output signal CL1 of the first AND gate AND1 is a high level, the third The switch tube M3 is turned off, and the fourth switch tube M4 is turned on. The second capacitor C2 is discharged to 0 through the fourth switch tube M4, so the input end of the second inverter NOT2 is still at a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input end of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 previously outputs a low level, the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is a high level, and the output signal P2 of the fourth inverter NOT4 is a high level. is low level; then, when the output signal CL1 of the first AND gate AND1 switches to a low level, the third switch tube M3 is turned on, the fourth switch tube M4 is turned off, and the input power supply VIN charges the second capacitor C2 through the third switch tube M3 and the second resistor R2. Since the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal, it can be obtained that the input end of the second inverter NOT2 is still at a low level. At this time, the output signal P1 of the third inverter NOT3 is still at a high level, and the output signal P2 of the fourth inverter NOT4 is still at a high level. is still low level; therefore, the fifth switch tube M5 is turned on, the sixth switch tube M6 and the seventh switch tube M7 are turned off, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, and the terminal voltage of the fourth capacitor C4 is in a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is low level; at this time, it can be seen from the structure of the output circuit 3 that when the signal P1 is high level, the signal When the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (that is, the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. That is, at this time, the output signal CL of the first OR gate OR1 remains at a high level for a period of time and then switches to a low level.

[0042] When the square wave signal switches from low level to high level, it can be seen from the above analysis that signal P1 is high level and signal When the signal CL1 is at a low level and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (ie, the output signal of the operating frequency control circuit) is at a low level.

[0043] After that, the circuit enters the next cycle of stable state. From the record in (i), we can get the waveform diagram of the circuit when it is in stable state and connected to the square wave signal, as shown in Figure 6 shown.

[0044] (ii) When the square wave signal is initially at a high level, as in (i), the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all switched to a high level, the first inverter NOT1 outputs a low level, the first switch tube M1 is turned on, the second switch tube M2 is turned off, and the input power VIN charges the first capacitor C1 through the first switch tube M1. At this time, since the first inverter NOT1 outputs a low level, the output signal CL1 of the first AND gate AND1 is also a low level. At this time, the third switch tube M3 is turned on, and the fourth switch tube M4 is turned off. Therefore, the input power VIN charges the first capacitor C1 through the third switch tube M3 and the fourth switch tube M4. The second resistor R2 charges the second capacitor C2. Since the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal, it can be obtained that the input end of the second inverter NOT2 is still at a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input end of the first NAND gate NAND1 is at a high level, the first NAND gate NAND1 outputs a low level. Therefore, it can be obtained that the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is a high level, and the output signal P2 of the fourth inverter NOT4 is a high level. is low level; therefore, the fifth switch tube M5 is turned on, the sixth switch tube M6 and the seventh switch tube M7 are turned off, and since there is no charge in the third capacitor C3 during the first cycle of the circuit power-on, its terminal voltage VC is less than the second fixed voltage V2, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, the current I1 output by the first current source B1 charges the fourth capacitor C4, and the terminal voltage of the fourth capacitor C4 gradually increases to a high level state, so at this time, the output signal CL2 of the fifth inverter NOT5 is low level; at this time, it can be seen from the structure of the output circuit 3 that when the signal P1 is high level, the signal When the signal CL1 is at a low level and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (ie, the output signal of the operating frequency control circuit) is at a low level.

[0045] When the square wave signal is switched from a high level to a low level, the input end of the first inverter NOT1, the first input end of the first NAND gate NAND1, and the source of the eighth switch tube M8 are all switched to a low level, the first inverter NOT1 outputs a high level, the first switch tube M1 is turned off, the second switch tube M2 is turned on, the first capacitor C1 is slowly discharged through the first resistor R1 and the second switch tube M2, and the terminal voltage of the first capacitor C1 is first maintained at a high level for a period of time and then switched to a low level state. Therefore, the first AND gate AND1 outputs a high level for a period of time and then switches to a low level. When the output signal CL1 of the first AND gate AND1 is a high level, the third The switch tube M3 is turned off, and the fourth switch tube M4 is turned on. The second capacitor C2 is discharged to 0 through the fourth switch tube M4, so the input end of the second inverter NOT2 is still at a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input end of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 previously outputs a low level, the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is a high level, and the output signal P2 of the fourth inverter NOT4 is a high level. is low level; then, when the output signal CL1 of the first AND gate AND1 switches to a low level, the third switch tube M3 is turned on, the fourth switch tube M4 is turned off, and the input power supply VIN charges the second capacitor C2 through the third switch tube M3 and the second resistor R2. Since the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal, it can be obtained that the input end of the second inverter NOT2 is still at a low level. At this time, the output signal P1 of the third inverter NOT3 is still at a high level, and the output signal P2 of the fourth inverter NOT4 is still at a high level. is still low level; therefore, the fifth switch tube M5 is turned on, the sixth switch tube M6 and the seventh switch tube M7 are turned off, the second comparator CMP2 outputs a low level, the tenth switch tube M10 is turned off, and the terminal voltage of the fourth capacitor C4 is in a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is low level; at this time, it can be seen from the structure of the output circuit 3 that when the signal P1 is high level, the signal When the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (that is, the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. That is, at this time, the output signal CL of the first OR gate OR1 remains at a high level for a period of time and then switches to a low level.

[0046] When the square wave signal switches from low level to high level, it can be seen from the above analysis that signal P1 is high level and signal When the signal CL1 is at a low level and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (ie, the output signal of the operating frequency control circuit) is at a low level.

[0047] After that, the circuit enters the next cycle of stable state. According to (ii), when the circuit is in stable state, the waveform diagram when receiving the square wave signal is still as follows: Figure 6 shown.

[0048] (2) The square wave signal is connected to the chip later than the input power VIN: At this time, it can be seen from the analysis in (1) above that when the input power supply VIN is connected to the chip and the square wave signal is not connected to the chip, the input pin G1 / G2 is in an unstable state, but no matter whether the input pin G1 / G2 is at a high level or a low level, at the initial power-on stage, the output signal CL1 of the first AND gate AND1 is at a low level. Therefore, the third switch tube M3 is turned on and the fourth switch tube M4 is turned off. The input power supply VIN charges the terminal voltage of the second capacitor C2 to a high level state through the third switch tube M3 and the second resistor R2. Therefore, at this time, the output of the NOT gate A3 is always at a low level, the output of the first NAND gate NAND1 is always at a high level, the output of the third NAND gate NAND3 is always at a high level, and the output signal P1 of the third inverter NOT3 is always at a low level.

[0049] Afterwards, the square wave signal is connected to the input pin G1 / G2. When the first falling edge of the square wave signal arrives, that is, when the square wave signal switches from a high level to a low level, the first inverter NOT1 outputs a high level, the first switch tube M1 is turned off, the second switch tube M2 is turned on, and the first capacitor C1 is slowly discharged through the first resistor R1 and the second switch tube M2. The terminal voltage of the first capacitor C1 is first kept at a high level for a period of time and then switched to a low level. Therefore, the first AND gate AND1 outputs a high level for a period of time and then switches to a low level. When the output signal CL1 of the first AND gate AND1 is a high level, the third switch tube M3 is turned off, the fourth switch tube M4 is turned on, and the second capacitor C2 is discharged to 0 through the fourth switch tube M4. Therefore, the input end of the second inverter NOT2 is switched to a low level, and the output end of the second inverter NOT2 outputs a high level. Since the first input of the first NAND gate NAND1 The first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 outputs a high level before, the second NAND gate NAND2 outputs a low level, and the third NAND gate NAND3 still outputs a high level. At this time, the output signal P1 of the third inverter NOT3 is still a low level. When the output signal CL1 of the first AND gate AND1 is switched to a low level, the third switch tube M3 is turned on, and the fourth switch tube M4 is turned off. The input power supply VIN charges the second capacitor C2 through the third switch tube M3 and the second resistor R2. Since the voltage of the second capacitor C2 cannot be charged to a voltage greater than the conversion threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal, it can be obtained that the input end of the second inverter NOT2 is still a low level, the output end of the second inverter NOT2 still outputs a high level, and the third NAND gate NAND3 still outputs a high level.

[0050] After the square wave signal switches from low level to high level, the circuit works as in (ii). From the above analysis, although the circuit works differently in (2) than in (1), when the circuit is stable, the waveform when connected to the square wave signal is still as shown in (ii). Figure 6 As shown; from the analysis in (1) and (2), it can be seen that the frequency of the output signal CL of the operating frequency control circuit is the same as the frequency of the square wave signal. By connecting square wave signals of different frequencies, the operating frequency of the power supply circuit can be controlled.

[0051] In addition, it should be noted that when the frequency of the square wave signal is low, the voltage of the second capacitor C2 will be charged to a level greater than the switching threshold voltage VT of the second inverter NOT2. At this time, the output signal P1 of the third inverter NOT3 is always at a low level, and the output signal P2 of the fourth inverter NOT4 is always at a low level. It is always high level, the fifth switch tube M5 is always turned off, when the square wave signal is low level, the eighth switch tube M8 is turned on, the second control circuit 2 works briefly, and the output signal CL of the operating frequency control circuit produces a short high level state, when the square wave signal is high level, the eighth switch tube M8 is turned off, and the output signal CL of the operating frequency control circuit is always low level, therefore, the frequency of the output signal CL of the operating frequency control circuit is the same as the frequency of the square wave signal; however, since a frequency detection circuit is additionally provided inside the chip to detect the frequency of the output signal CL of the operating frequency control circuit, when its frequency is low, the chip is in the off state; therefore, the minimum frequency of the output signal CL of the operating frequency control circuit is controlled by adjusting the parameters of the second resistor R2 and the second capacitor C2.

[0052] This embodiment also provides an integrated circuit control chip, which includes the operating frequency control circuit of the above embodiment.

[0053] This embodiment also provides a power supply circuit with a small volume and a wide range of applications, such as Figure 7 and Figure 8 As shown, the power supply circuit includes the integrated circuit control chip U1 of the above embodiment. Specifically, the power supply circuit also includes an external power circuit.

[0054] Among them, when multiple power supply circuits are set in the circuit system, each power supply circuit includes an integrated circuit control chip, and each integrated circuit control chip includes an operating frequency control circuit. When the same square wave signal is input through the input pin of the operating frequency control circuit, the operating frequency control circuit can output a signal with the same operating frequency, thereby making the operating frequencies of the power supply circuits controlled by the multiple integrated circuit control chips the same, thereby ensuring the consistency of operation of each power supply circuit in the circuit system; when one power supply circuit is set in the circuit system, the operating frequency of the power supply circuit can be controlled by an external adjustment resistor or an input square wave signal.

[0055] Therefore, the power supply circuit with small volume and wide application range provided in this embodiment can control the operating frequency of the power supply circuit after an external adjustment resistor or square wave signal is realized through a pin, thereby reducing the volume of the power supply circuit and increasing the application range of the power supply circuit.

[0056] Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims, and such modifications and variations all fall within the scope defined by the appended claims. For other examples, those of ordinary skill in the art should readily understand that the order of the process steps may be changed while maintaining the scope of protection of the present invention.

[0057] In addition, the scope of application of the present invention is not limited to the processes, mechanisms, manufactures, material compositions, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be easily understood by those skilled in the art that the processes, mechanisms, manufactures, material compositions, means, methods or steps that currently exist or will be developed in the future, which perform substantially the same functions as the corresponding embodiments described in the present invention or obtain substantially the same results, can be applied according to the present invention. Therefore, the claims attached to the present invention are intended to include these processes, mechanisms, manufactures, material compositions, means, methods or steps within their scope of protection.

Claims

1. A working frequency control circuit, characterized in that: include: Input pin, used to receive external input square wave signal or connect external adjustment resistor; a first control circuit, a first end of which is connected to the input pin, a second end of which is connected to the external power supply, and a third end of which is grounded, and is used to obtain a signal with the same frequency as the square wave signal or a first low-level signal according to whether the signal inputted by the input pin is a square wave signal, and output a second low-level signal or a high-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal; a second control circuit, a first end of which is connected to the fourth end of the first control circuit, a second end of which is connected to the input pin, a third end of which is connected to the external power supply, and a fourth end of which is grounded, and is used to output a third low-level signal or a periodic output signal according to the second low-level signal or the high-level signal output by the first control circuit; An output circuit, whose first end is connected to the fifth end of the second control circuit, whose second end is connected to the fourth end of the first control circuit, whose third end is connected to the fifth end of the first control circuit, and whose fourth end is connected to the sixth end of the first control circuit, is used to output an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjusting resistor according to the signal with the same frequency as the square wave signal or the first low level signal, the second low level signal or the high level signal, the inverted signal of the second low level signal or the high level signal and the third low level signal or the periodic output signal.

2. The operating frequency control circuit according to claim 1, characterized in that: The first control circuit comprises: A signal detection circuit, wherein a first end thereof is connected to an input pin, a second end thereof is connected to an external power supply, a third end thereof is grounded, and a fourth end thereof is connected to a fourth end of an output circuit, and is used to detect an input signal of the input pin, and when the input signal is a square wave signal, output an output signal having the same frequency as the square wave signal, and when the input signal is not a square wave signal, output a first low level signal; A switch control circuit, a first end of which is connected to the fourth end of the signal detection circuit, a second end of which is connected to an external power supply, a third end of which is grounded, a fourth end of which is connected to an input pin, a fifth end of which is connected to the first end of the second control circuit and the second end of the output circuit, and a sixth end of which is connected to the third end of the output circuit, is used to output a second low-level signal when the signal detection circuit outputs an output signal with the same frequency as the square wave signal, and to output a high-level signal when the signal detection circuit outputs a first low-level signal.

3. The operating frequency control circuit according to claim 2, characterized in that: The second control circuit comprises: a switch circuit, a first end of which is connected to the fourth end of the first control circuit, a second end of which is connected to an external power supply, and a third end of which is connected to the input pin; A voltage control circuit, a first terminal of which is connected to a first fixed voltage, and a second terminal and a third terminal of which are connected to a fourth terminal of the switch circuit; a first charging circuit, a first end of which is connected to the fourth end of the switch circuit, a second end of which is connected to the external power supply, and a third end of which is grounded; a second charging circuit, wherein a first end of the second charging circuit is connected to the fourth end of the first charging circuit, a second end of the second charging circuit is connected to the second fixed voltage, a third end of the second charging circuit is connected to the external power supply, a fourth end of the second charging circuit is grounded, and a fifth end of the second charging circuit is connected to the fifth end of the first charging circuit and the first end of the output circuit; When the first control circuit outputs a second low-level signal, the switch circuit turns off the first charging circuit, and the second charging circuit outputs a third low-level signal. When the first control circuit outputs a high-level signal, the first charging circuit operates under the control of the switch circuit and the voltage control circuit, and the first charging circuit outputs a periodic output signal. The second charging circuit outputs an output signal with the same period as the periodic output signal according to the periodic output signal.

4. The operating frequency control circuit according to claim 3, characterized in that: The signal detection circuit includes a first inverter, a first AND gate, a first switch tube, a second switch tube, a first resistor and a first capacitor, and the switch control circuit includes a third switch tube, a fourth switch tube, a second resistor, a second capacitor, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a third inverter and a fourth inverter; The input end of the first inverter is connected to the input pin, the output end of the first inverter is connected to the first end of the first switch tube, the first input end of the first AND gate and the first end of the second switch tube, the second end of the first switch tube is connected to the external power supply, the third end of the first switch tube is connected to the second input end of the first AND gate, one end of the first capacitor and one end of the first resistor, the other end of the first resistor is connected to the second end of the second switch tube, and the third end of the second switch tube is connected to the other end of the first capacitor and grounded; the output end of the first AND gate is connected to the first end of the third switch tube, the first end of the fourth switch tube and the fourth end of the output circuit; The second end of the third switch tube is connected to an external power supply, the third end of the third switch tube is connected to one end of the second resistor, the other end of the second resistor is connected to the second end of the fourth switch tube, one end of the second capacitor and the input end of the second inverter, the third end of the fourth switch tube is connected to the second end of the second capacitor and is grounded, the output end of the second inverter is connected to the first input end of the first NAND gate and the first input end of the third NAND gate, the second input end of the first NAND gate is connected to an input pin, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the third NAND gate and the input end of the third inverter, the output end of the second NAND gate is connected to the second input end of the third NAND gate, the output end of the third inverter is connected to the input end of the fourth inverter and the third end of the output circuit, and the output end of the fourth inverter is connected to the first end of the second control circuit and the second end of the output circuit.

5. The operating frequency control circuit according to claim 3, characterized in that: The switch circuit includes a fifth switch tube and an eighth switch tube, the voltage control circuit includes a first comparator, the first charging circuit includes a sixth switch tube, a seventh switch tube, a ninth switch tube and a third capacitor, and the second charging circuit includes a second comparator, a tenth switch tube, a fourth capacitor, a fifth inverter and a first current source; The first end of the fifth switch tube is connected to the first end of the eighth switch tube, the fourth end of the first control circuit and the second end of the output circuit, the second end of the fifth switch tube is connected to an external power supply, the third end of the fifth switch tube is connected to the first end and the second end of the sixth switch tube, the first end of the seventh switch tube, the output end of the first comparator, the negative input end of the first comparator and the second end of the eighth switch tube, the third end of the eighth switch tube is connected to an input pin; the positive input end of the first comparator is connected to a first fixed voltage; The third end of the sixth switch tube is connected to the second end of the seventh switch tube and an external power supply, the third end of the seventh switch tube is connected to the positive input end of the second comparator, one end of the third capacitor and the first end of the ninth switch tube, the negative input end of the second comparator is connected to a second fixed voltage, the output end of the second comparator is connected to the first end of the tenth switch tube, the other end of the third capacitor is connected to the second end of the ninth switch tube and is grounded, the second end of the tenth switch tube is connected to the output end of the first current source, the input end of the fifth inverter and one end of the fourth capacitor, the other end of the fourth capacitor is connected to the third end of the tenth switch tube and is grounded, the output end of the fifth inverter is connected to the third end of the ninth switch tube and the first end of the output circuit, and the input end of the first current source is connected to an external power supply.

6. The operating frequency control circuit according to claim 1, characterized in that: The output circuit includes a second AND gate, a third AND gate and a first OR gate, wherein the first input end of the second AND gate is connected to the fifth end of the second control circuit, the second input end of the second AND gate is connected to the fourth end of the first control circuit, the first input end of the third AND gate is connected to the fifth end of the first control circuit, the second input end of the third AND gate is connected to the sixth end of the first control circuit, the output end of the second AND gate is connected to the first input end of the first OR gate, the output end of the third AND gate is connected to the second input end of the first OR gate, and the output end of the first OR gate outputs an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjustment resistor.

7. The operating frequency control circuit according to claim 4, characterized in that: The first fixed voltage is less than a switching threshold voltage of the first inverter; When the external power source charges the second capacitor through the third switch tube and the second resistor, within one cycle of the square wave signal, the voltage across the second capacitor is less than the switching threshold voltage of the second inverter.

8. The operating frequency control circuit according to claim 4, characterized in that: The lowest frequency of the output signal of the output circuit is controlled according to the parameters of the second resistor and the second capacitor.

9. An integrated circuit control chip, characterized in that: The chip comprises the operating frequency control circuit according to any one of claims 1-8.

10. A power supply circuit with small volume and wide application range, characterized in that: The power supply circuit includes the integrated circuit control chip as claimed in claim 9.

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