PWM signal generation and reduction furnace power supply control method, device, equipment and medium

Abstract

The invention discloses a PWM signal generation method and device, a reduction furnace power supply control method and device, equipment and a medium, and relates to the field of power supply control, and the method comprises the steps: obtaining the count value of each PWM counter; wherein each PWM counter is controlled to be reset at a zero crossing point of a synchronous signal through a soft phase-locked loop; determining a CMPA and a CMPB corresponding to each gear based on the period of the PWM signal and the dead zone angle of each gear; when the count value of the PWM counter is equal to the CMPA, the corresponding PWM signal is set to be 1; and when the count value of the PWM counter is equal to the CMPB, the corresponding PWM signal is reset to generate a PWM signal. And controlling the silicon controlled rectifier of the corresponding gear to operate according to the enable signal corresponding to each gear and the PWM signal. According to the invention, harmonic waves generated in the process can be reduced while a relatively wide voltage regulation range is realized.

Description

Technical Field

[0001] The present invention relates to the field of power supply control, and in particular to a method, device, equipment and medium for PWM signal generation and reduction furnace power supply control. Background Art

[0002] Since the power supply system of the polysilicon reduction furnace needs to adopt a high-power voltage-regulated power supply to achieve a wider voltage regulation range, the thyristor stack control can be realized through a multi-tap transformer to further realize the power supply control.

[0003] In the prior art, two adjacent thyristors are operated simultaneously for superposition operation. However, due to the large cutting area of ​​the final output waveform, the output waveform distortion is also large, which further leads to an increase in the generated harmonics. The increase in harmonics not only increases the operating loss of the system, affects the stable operation of the system, but also increases the cost of reducing harmonics.

[0004] Therefore, how to reduce the harmonics generated in the process is an urgent problem to be solved. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a PWM signal generation and reduction furnace power supply control method, device, equipment and medium to reduce the harmonics generated in the process. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a PWM signal generation method, which is applied to a thyristor voltage regulation system, and the method comprises:

[0007] Obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop;

[0008] Determine the CMPA and CMPB corresponding to each gear position based on the period of the PWM signal and the dead zone angle of each gear position;

[0009] When the count value of the PWM counter is equal to the CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to the CMPB, the corresponding PWM signal is cleared to generate a PWM signal.

[0010] In a second aspect, the present application provides a reduction furnace power supply control method, which is applied to a thyristor voltage regulation system, and the method comprises:

[0011] Obtain the PWM signal of the thyristor corresponding to each gear; wherein the PWM signal of each thyristor is obtained by the following steps: obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal;

[0012] The operation of the thyristor of the corresponding gear is controlled according to the enable signal corresponding to each gear and the PWM signal.

[0013] Optionally, controlling the operation of the thyristor of the corresponding gear according to the enable signal corresponding to each gear and the PWM signal includes:

[0014] When the enable signal corresponding to the gear is at a high level, based on the PWM signal corresponding to the gear, the thyristor corresponding to the PWM signal is controlled to operate; wherein the gear includes a positive thyristor and a negative thyristor;

[0015] When the enable signal corresponding to the gear position is at a low level, the thyristor of the gear position is prohibited from operating.

[0016] Optionally, controlling the operation of the thyristor of the gear based on the PWM signal corresponding to the gear includes:

[0017] When the synchronization signal is in the positive half cycle, based on the PWM signal corresponding to the gear, the forward thyristor of the gear is controlled to operate;

[0018] When the synchronization signal is in the negative half cycle, the negative thyristor of the gear is controlled to operate based on the PWM signal corresponding to the gear.

[0019] Optionally, the thyristor voltage regulation system includes a first gear, a second gear, a third gear, a fourth gear and a fifth gear, and the thyristor operation of the corresponding gear is controlled according to the enable signal corresponding to each gear and the PWM signal; including:

[0020] When the enable signals corresponding to the gears are all at high level, the thyristors of all the gears are controlled to operate based on the PWM signals;

[0021] When the enable signal corresponding to the first gear is at a low level, and the enable signals corresponding to the other gears are all at a high level, the thyristors of the second gear, the third gear, the fourth gear, and the fifth gear are controlled to operate based on the PWM signals;

[0022] When the enable signals corresponding to the first gear and the second gear are both at low levels, and the enable signals corresponding to the remaining gears are all at high levels, the thyristors of the third gear, the fourth gear, and the fifth gear are controlled to operate based on the PWM signals;

[0023] When the enable signals corresponding to the first gear, the second gear and the third gear are all at low levels, and the enable signals corresponding to the remaining gears are all at high levels, the thyristors of the fourth gear and the fifth gear are controlled to operate based on the PWM signals.

[0024] Optionally, determining the CMPA and CMPB corresponding to each gear position based on the PWM signal period and the dead zone angle of each gear position includes:

[0025] The product of the ratio of the dead zone angle of each gear to 180° and the period of the PWM signal is used as the CMPA corresponding to each gear;

[0026] The PWM signal period is used as the CMPB corresponding to each gear position.

[0027] In a third aspect, the present application provides a PWM signal generating device, comprising:

[0028] A count value acquisition module, used to acquire the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control;

[0029] A parameter determination module, used to determine the CMPA and CMPB corresponding to each gear based on the PWM signal period and the dead zone angle of each gear;

[0030] The PWM signal determination module is used to set the corresponding PWM signal to 1 when the count value of the PWM counter is equal to CMPA; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to zero, so as to obtain the PWM signal corresponding to each gear.

[0031] In a fourth aspect, the present application provides a power supply control device, comprising:

[0032] A PWM signal acquisition module is used to acquire the PWM signal of the thyristor corresponding to each gear; wherein, the count value of each PWM counter is acquired; wherein, each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal;

[0033] The gear operation module is used to control the operation of the thyristor of the corresponding gear according to the enable signal corresponding to each gear and the PWM signal.

[0034] In a fifth aspect, the present application provides an electronic device, including:

[0035] Memory, used to store computer programs;

[0036] The processor is used to execute the computer program to implement the above-mentioned reduction furnace power supply control method and PWM signal generation method.

[0037] In a sixth aspect, the present application provides a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the above-mentioned reduction furnace power supply control method and PWM signal generation method are implemented.

[0038] From the above, it can be concluded that the synchronization signal of the grid voltage is introduced into the controller, and a triangular wave is constructed by soft phase locking to achieve zero-crossing capture, so as to provide a reference point for each PWM signal determined based on the cycle of the PWM (Pulse width modulation, multiple pulse width modulation) signal and the dead zone angle corresponding to each gear. In addition, since each gear corresponds to a separate PWM signal, the gear can be controlled to perform different combinations through the enable signal. Among them, when all gears are controlled to work at the same time, the output waveform is close to a sine wave, so that the output waveform distortion is small, so the harmonics of the system output are also reduced accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A flow chart of a PWM signal generating method disclosed in this application;

[0041] Figure 2 A schematic diagram of a thyristor voltage regulation system disclosed in this application;

[0042] Figure 3 A schematic diagram of another thyristor voltage regulation system disclosed in this application;

[0043] Figure 4 A schematic diagram of calculating a soft phase-locked PWM period disclosed in this application;

[0044] Figure 5 A flow chart of a reduction furnace power supply control method disclosed in this application;

[0045] Figure 6 A trigger pulse logic output disclosed in this application;

[0046] Figure 7 A schematic diagram of an output waveform disclosed in this application;

[0047] Figure 8 A schematic diagram of an output waveform disclosed in this application;

[0048] Fig. 9 This is a schematic diagram of the structure of a PWM signal generating device disclosed in this application;

[0049] Fig.10 This is a schematic diagram of the structure of a power supply control device disclosed in this application;

[0050] Fig.11 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Since the power supply system of the polysilicon reduction furnace needs to adopt a high-power voltage-regulated power supply to achieve a wider voltage regulation range, the thyristor stack control can be realized through a multi-tap transformer to further realize the power supply control.

[0053] In the prior art, two adjacent thyristors are operated simultaneously for superposition operation. However, due to the large cutting area of ​​the final output waveform, the output waveform distortion is also large, which further leads to an increase in the generated harmonics. The increase in harmonics not only increases the operating loss of the system, affects the stable operation of the system, but also increases the cost of reducing harmonics.

[0054] To this end, the present application provides a PWM signal generation scheme and a reduction furnace power supply control scheme to reduce the harmonics generated in the process.

[0055] See also Figure 1 , 2 As shown in , 3, an embodiment of the present invention discloses a PWM signal generation method, which is applied to a thyristor voltage regulation system, and the method includes:

[0056] Step S11, obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop;

[0057] In this embodiment, Figure 3 As shown in the figure, the synchronous signal is introduced into the controller after isolation sampling, the zero crossing point of the grid voltage is captured through soft phase locking, and the count value in each PWM counter is cleared at the zero crossing point, so that the waveform corresponding to the count value output by each PWM signal is as follows Figure 3 The triangle wave shown.

[0058] In this embodiment, the relationship between the triangular wave generated by the PWM counter and the synchronization signal is as follows: Figure 3 As shown, the synchronization signal obtained based on the grid voltage through the software phase-locked loop is a sine wave, which can reflect the phase and frequency information of the grid voltage. Since the count value in the PWM counter will be reset at the zero crossing point, the period of the triangular wave generated by the PWM counter at this time is half of the synchronization signal period.

[0059] In this embodiment, Figure 2 , 3 As shown, the thyristor voltage regulation system supplies power to the load, and its thyristor stack control can be achieved by using a multi-tap transformer. Each gear includes a current transformer and a group of thyristors, and each group of thyristors is controlled by the PWM signal output by the PWM controller. Therefore, in order to accurately control the conduction and shutdown of the thyristors in each gear, it is necessary to determine the PWM signal corresponding to each gear based on actual requirements. Figure 2 , 3The thyristor system includes five gears, the AC transformer is a multi-gear transformer, the current transformers corresponding to each gear are T1, T2, T3, T4 and T5, a group of thyristors corresponding to each gear are V1, V2, V3, V4 and V5, and the PWM signal output ports corresponding to each gear are R1, R2, R3, R4 and R5.

[0060] Further, such as Figure 4 As shown, each gear includes a forward thyristor and a reverse thyristor. For example, in the first gear, V1+ is a forward thyristor, V1- is a reverse thyristor, and in the second gear, V2+ is a forward thyristor, and V2- is a reverse thyristor. The forward thyristor and reverse thyristor in each gear control the positive half-cycle and negative half-cycle of the alternating current respectively. Therefore, in order to ensure that the triangular wave can generate a complete control cycle in the positive half-cycle and the negative half-cycle respectively within a complete cycle of the synchronization signal, the synchronization signal cycle needs to be twice the cycle of the triangular wave. By using the PWM signal generated by comparing the triangular wave with the reference signal, the on and off moments of the forward thyristor and the reverse thyristor are independently controlled to achieve precise control of the AC full wave, that is, a positive trigger pulse is generated in the positive half-cycle to control the forward thyristor to turn on, and a negative trigger pulse is generated in the negative half-cycle to control the negative thyristor to turn on, so as to flexibly adjust the output voltage.

[0061] In this embodiment, in order to ensure that the acquired synchronization signal of the grid voltage meets the accuracy requirement of zero-crossing capture, a high-precision voltage sensor or voltage transformer may be selected.

[0062] Step S12, determining CMPA and CMPB corresponding to each gear based on the period of the PWM signal and the dead zone angle of each gear;

[0063] In this embodiment, each gear has its corresponding dead zone angle, so the CMPA and CMPB corresponding to each gear can be calculated through the PWM phase cycle and different time zone angles. The CMPA and CMPB are the above-mentioned reference signals. It should be noted that the dead zone angle refers to the angle interval in which the thyristor is not allowed to trigger conduction within one cycle of the AC signal, so as to avoid the forward thyristor and the reverse thyristor on the same bridge arm from being turned on at the same time. This is because the opening and closing of the thyristor requires a certain amount of time. The dead zone time is set to insert a period of forced blocking time when the control signal switches from controlling one thyristor to controlling another thyristor, ensuring that the previous thyristor is completely turned off before the next thyristor starts to conduct, avoiding the phenomenon of direct conduction. Therefore, setting a suitable dead zone angle can ensure the stability and reliability of the circuit and avoid circuit failures caused by false triggering of thyristors.

[0064] In this embodiment, when determining the PWM signal, CMPA and CMPB are the value of the count comparison register A and the value of the count comparison register B respectively. The count comparison module uses the count value of the PWM counter as input and needs to continuously compare with CMPA and CMPB. When the count value of the PWM counter is equal to CMPA or CMPB, the corresponding event will be triggered.

[0065] It is understandable that when the tap position of a multi-tap transformer is changed, its output voltage and waveform will change, and the same model of thyristor will have certain differences in its triggering characteristics under different voltage, current and other working conditions. Therefore, thyristors of different positions will meet the conditions of conduction or shutdown at different times, resulting in different dead zone angles corresponding to each position.

[0066] In this embodiment, the product of the ratio of the dead zone angle of each gear to 180° and the PWM signal period is used as the CMPA corresponding to each gear; and the PWM signal period is used as the CMPB corresponding to each gear. It can be understood that according to the corresponding relationship between the electrical angle of the system and time, the dead zone angle can be converted into a time length. Since the electrical angle of the system is 180°, the ratio of the dead zone angle corresponding to each gear to 180° is the ratio of the dead zone time corresponding to the gear in the PWM signal period, that is, during the period from when the count value of the PWM counter is equal to 0 to when the count value of the PWM counter is equal to CMPA, the thyristor of the gear can neither be turned on nor turned off, and is in a forced blocking state. In addition, because the period of the PWM signal represents the time required for the PWM signal to complete a complete high-level and low-level cycle. In a PWM signal period, excluding the dead zone time, the remaining time is the effective time for the thyristor to actually turn on and off, that is, during the period from when the count value of the PWM counter is equal to CMPA to when the count value of the PWM counter is equal to CMPB, the thyristor of the gear can be turned on and off normally.

[0067] Step S13: when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal.

[0068] In this embodiment, when the count value of the PWM counter is equal to CMPA, the PWM signal is set to 1, and when the count value of the PWM counter is equal to CMPB, the PWM signal is cleared to 0, so as to achieve adjustable duty cycle of the PWM signal. It can be understood that, at this time, except for the dead time, the thyristor corresponding to the PWM signal is continuously in the on state, that is, within the cycle of the PWM signal, except for the dead time, the PWM signal maintains a high level in the rest of the time.

[0069] In this embodiment, the PWM signal of the current gear can be determined by determining CMPA and CMPB according to the above calculation method. For example, the period of the PWM signal is 10000us, and the dead zone angle of the fifth gear is 10°. According to the above calculation method, the CMPA corresponding to the gear can be obtained as 10000*10° / 180°=555, and CMPB=10000, that is, when the PWM count value = 555 = CMPA, the PWM signal is set to 1, and when the PWM count value = 10000 = CMPB, the PWM signal is cleared to 0, and the PWM signal corresponding to the fifth gear can be obtained.

[0070] From the above, it can be concluded that the dead time corresponding to different gears is determined by the dead time angle and the cycle of the PWM signal. During the dead time, the PWM signal corresponding to the gear is set to a low level, and the PWM signal is set to a high level during the cycle time except the dead time to determine the PWM signal corresponding to each gear. In addition, since each gear corresponds to a separate PWM signal, any combination of gears can be achieved through software control.

[0071] See also Figure 5 As shown, an embodiment of the present invention discloses a reduction furnace power supply control method, which is applied to a thyristor voltage regulation system, and the method includes:

[0072] Step S21, obtaining the PWM signal of the thyristor corresponding to each gear; wherein the PWM signal of each thyristor is obtained by the following steps: obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal;

[0073] In this embodiment, based on the above-mentioned PWM signal generation method, the duty cycle of the PWM signal corresponding to each gear can be accurately adjusted according to the dead zone angle corresponding to each gear and the period of the PWM signal, so as to finally obtain the PWM signal corresponding to each gear.

[0074] Step S22: controlling the operation of the thyristor of the corresponding gear according to the enable signal and PWM signal corresponding to each gear.

[0075] In this embodiment, the working condition of the thyristor in each gear is comprehensively controlled based on the enable signal and the PWM signal corresponding to each gear.

[0076] In this embodiment, when the enable signal corresponding to the gear is at a high level, based on the PWM signal corresponding to the gear, the thyristor corresponding to the PWM signal is controlled to operate; wherein the gear includes a positive thyristor and a negative thyristor; when the enable signal corresponding to the gear is at a low level, the thyristor in the gear is prohibited from operating. The enable signal needs to control different thyristors in the same gear respectively. Only when the enable signal is at a high potential can the PWM signal control the thyristor, that is, the enable signal needs to be combined with the PWM signal corresponding to the gear to generate a trigger pulse corresponding to each thyristor. Figure 6 As shown, Enable is the enable signal corresponding to the thyristor. The PWM signal corresponding to the first gear and the above enable signal are combined to determine the trigger pulse corresponding to the forward thyristor V1+ of the first gear to control the operation of the forward thyristor. Therefore, by outputting 10 groups of enable signals to the controller, the enable output of each group of PWM signals is realized to control the output of any gear combination.

[0077] In this embodiment, when the synchronization signal is in the positive half cycle, the positive thyristor of the gear is controlled to operate based on the PWM signal corresponding to the gear; when the synchronization signal is in the negative half cycle, the negative thyristor of the gear is controlled to operate based on the PWM signal corresponding to the gear. Figure 4 As shown, vt is the acquired synchronization signal. The trigger pulse corresponding to each thyristor can be determined by the above-mentioned enable signal, wherein the trigger pulse corresponding to the positive thyristor of different gears is a positive trigger pulse, that is, each positive thyristor can only be turned on in the positive half cycle of the synchronization signal, and the trigger pulse corresponding to the negative thyristor of different gears is a negative trigger pulse, that is, each negative thyristor can only be turned on in the negative half cycle of the synchronization signal. It can be understood that the positive thyristor needs to add a positive voltage between the anode and the cathode, and the control electrode adds a positive trigger pulse to turn on. Therefore, in the negative half cycle of the synchronization signal, although the control electrode may have a trigger pulse, since the anode and the cathode are reverse voltages, the conduction condition is not met, so the positive thyristor will not be turned on. Similarly, the negative thyristor needs to add a reverse voltage between the anode and the cathode, and the control electrode adds a negative trigger pulse to turn on. Therefore, in the positive half cycle of the synchronization signal, the anode and the cathode are positive voltages, even if the control electrode has a trigger pulse, it does not meet its conduction condition, so the negative thyristor will not be turned on.

[0078] In this embodiment, Figure 3As shown, the thyristor voltage regulation system includes five gears, and each gear corresponds to a PWM signal, namely, the first gear PWM signal, the second gear PWM signal, the third gear PWM signal, the fourth gear PWM signal and the fifth gear PWM signal. However, since the forward thyristor and the reverse thyristor of each gear are not turned on at the same time, the PWM signal corresponding to each gear can be understood as containing two independent PWM signals for controlling different thyristors of the same gear.

[0079] In this embodiment, when the enable signals corresponding to each gear are all high level, the operation of the thyristors of all gears is controlled based on each PWM signal; when the enable signal corresponding to the first gear is low level and the enable signals corresponding to the other gears are high level, the operation of the thyristors of the second gear, the third gear, the fourth gear and the fifth gear is controlled based on each PWM signal; when the enable signals corresponding to the first gear and the second gear are low level and the enable signals corresponding to the other gears are high level, the operation of the thyristors of the third gear, the fourth gear and the fifth gear is controlled based on each PWM signal; when the enable signals corresponding to the first gear, the second gear and the third gear are low level and the enable signals corresponding to the other gears are high level, the operation of the thyristors of the fourth gear and the fifth gear is controlled based on each PWM signal.

[0080] like Figure 7 , 8 As shown, the thyristor voltage regulation system includes five gears, and the dead zone angles of each gear are 50°, 40°, 30°, 40° and 50° from the first gear to the fifth gear.

[0081] Furthermore, Figure 7 The output waveforms generated by the superposition of two adjacent gears of the thyristor voltage regulating system in the prior art are, from top to bottom, the output pulses generated when the thyristors in the first gear and the second gear are superimposed on each other; the output pulses generated when the thyristors in the second gear and the third gear are superimposed on each other; the output pulses generated when the thyristors in the third gear and the fourth gear are superimposed on each other; and the output pulses generated when the thyristors in the fourth gear and the fifth gear are superimposed on each other. Figure 8 The output waveforms generated by the stacked operation of the thyristor voltage regulation system implemented by the above steps are, from top to bottom, the output waveforms generated when the thyristors in the five gears are stacked; the output waveforms generated when the thyristors in the second gear to the fifth gear are stacked; the output waveforms generated when the thyristors in the third gear to the fifth gear are stacked; the output waveforms generated when the thyristors in the fourth gear to the fifth gear are stacked. It can be understood that Figure 8 The shaded area ratio of the power supply output waveform Figure 7 The larger the waveform, the closer it is to a sine wave, thus producing fewer harmonics.

[0082] From the above, it can be concluded that the synchronization signal of the grid voltage is introduced into the controller, and the zero-crossing capture is realized by soft phase locking, so as to provide a reference point for each PWM signal determined based on the period of the PWM signal and the dead zone angle corresponding to each gear. In addition, since the thyristor in each gear corresponds to a PWM signal, the gear can be controlled to perform different combinations through the enable signal. Among them, when all gears are controlled to work at the same time, the output waveform is close to a sine wave, so that the output waveform distortion is small, so the harmonics of the system output are also reduced accordingly.

[0083] Accordingly, see Fig. 9 As shown, the embodiment of the present application also provides a PWM signal generating device, which may include:

[0084] The count value acquisition module 11 is used to acquire the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control;

[0085] A parameter determination module 12, for determining CMPA and CMPB corresponding to each gear position based on a PWM signal period and a dead zone angle of each gear position;

[0086] The PWM signal determination module 13 is used to set the corresponding PWM signal to 1 when the count value of the PWM counter is equal to CMPA; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to zero, so as to obtain the PWM signal corresponding to each gear.

[0087] From the above, it can be concluded that the dead time corresponding to different gears is determined by the dead time angle and the cycle of the PWM signal. During the dead time, the PWM signal corresponding to the gear is set to a low level, and the PWM signal is set to a high level during the cycle time except the dead time to determine the PWM signal corresponding to each gear. In addition, since each gear corresponds to a separate PWM signal, any combination of gears can be achieved through software control.

[0088] In some specific implementations, the parameter determination module 12 includes:

[0089] A first parameter determination unit, configured to take the product of the ratio of the dead zone angle of each gear to 180° and the PWM signal period as the CMPA corresponding to each gear;

[0090] The second parameter determination unit is used to use the PWM signal period as the CMPB corresponding to each gear position.

[0091] Accordingly, see Fig.10 As shown, the embodiment of the present application also provides a reduction furnace power supply control device, which may include:

[0092] The PWM signal acquisition module 21 is used to acquire the PWM signal of the thyristor corresponding to each gear; wherein, the count value of each PWM counter is acquired; wherein, each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal;

[0093] The gear operation module 22 is used to control the operation of the thyristor of the corresponding gear according to the enable signal corresponding to each gear and the PWM signal.

[0094] From the above, it can be concluded that the synchronization signal of the grid voltage is introduced into the controller, and the zero-crossing capture is realized by soft phase locking, so as to provide a reference point for each PWM signal determined based on the period of the PWM signal and the dead zone angle corresponding to each gear. In addition, since the thyristor in each gear corresponds to a PWM signal, the gear can be controlled to perform different combinations through the enable signal. Among them, when all gears are controlled to work at the same time, the output waveform is close to a sine wave, so that the output waveform distortion is small, so the harmonics of the system output are also reduced accordingly.

[0095] In some specific implementations, the gear operation module 22 includes:

[0096] A first thyristor operation unit, configured to control the operation of the thyristor corresponding to the PWM signal based on the PWM signal corresponding to the gear when the enable signal corresponding to the gear is at a high level; wherein the gear includes a positive thyristor and a negative thyristor;

[0097] The second thyristor operation unit is used to prohibit the thyristor of the gear from operating when the enable signal corresponding to the gear is at a low level.

[0098] In some specific embodiments, the first thyristor operation unit is specifically used to control the operation of the positive thyristor of the gear based on the PWM signal corresponding to the gear when the synchronization signal is in the positive half cycle; and control the operation of the negative thyristor of the gear based on the PWM signal corresponding to the gear when the synchronization signal is in the negative half cycle.

[0099] In some specific implementations, the gear operation module 22 includes:

[0100] A third thyristor operation unit, configured to control the operation of thyristors of all the gears based on the PWM signals when the enable signals corresponding to the gears are all at high levels;

[0101] a fourth thyristor operation unit, configured to control the operation of the thyristors of the second gear, the third gear, the fourth gear, and the fifth gear based on the PWM signals when the enable signal corresponding to the first gear is at a low level and the enable signals corresponding to the remaining gears are all at high levels;

[0102] a fifth thyristor operation unit, configured to control the operation of the thyristors of the third gear, the fourth gear, and the fifth gear based on the PWM signals when the enable signals corresponding to the first gear and the second gear are both at low levels and the enable signals corresponding to the remaining gears are all at high levels;

[0103] The sixth thyristor operation unit is used to control the thyristor operation of the fourth gear and the fifth gear based on the PWM signals when the enable signals corresponding to the first gear, the second gear and the third gear are at a low level and the enable signals corresponding to the remaining gears are at a high level.

[0104] Furthermore, the present application also discloses an electronic device. Fig.11 It is a structural diagram of an electronic device 30 shown according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device 30 may specifically include: at least one processor 31, at least one memory 32, a power supply 33, a communication interface 34, an input / output interface 35, and a communication bus 36. Among them, the memory 32 is used to store a computer program, and the computer program is loaded and executed by the processor 31 to implement the relevant steps in the PWM signal generation and reduction furnace power control method disclosed in any of the aforementioned embodiments. In addition, the electronic device 30 in this embodiment may specifically be an electronic computer.

[0105] In this embodiment, the power supply 33 is used to provide working voltage for each hardware device on the electronic device 30; the communication interface 34 can create a data transmission channel between the electronic device 30 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 35 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0106] In addition, the memory 32, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 321, a computer program 322, etc., and the storage method can be temporary storage or permanent storage.

[0107] The operating system 321 is used to manage and control the hardware devices on the electronic device 30 and the computer program 322, which can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the PWM signal generation and reduction furnace power control method performed by the electronic device 30 disclosed in any of the aforementioned embodiments, the computer program 322 can further include computer programs that can be used to complete other specific tasks.

[0108] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed PWM signal generation and reduction furnace power supply control method is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0109] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0110] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0111] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0112] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0113] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A PWM signal generation method, characterized in that: Applied to a thyristor voltage regulation system, the method comprises: Obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop; Determine the CMPA and CMPB corresponding to each gear position based on the period of the PWM signal and the dead zone angle of each gear position; When the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal.

2. A reduction furnace power supply control method, characterized in that: Applied to a thyristor voltage regulation system, the method comprises: Obtain the PWM signal of the thyristor corresponding to each gear; wherein the PWM signal of each thyristor is obtained by the following steps: obtaining the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal by controlling the soft phase-locked loop; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal; The operation of the thyristor of the corresponding gear is controlled according to the enable signal corresponding to each gear and the PWM signal.

3. The reduction furnace power supply control method according to claim 2, characterized in that: The step of controlling the operation of the thyristor of the corresponding gear according to the enable signal corresponding to each gear and the PWM signal comprises: When the enable signal corresponding to the gear is at a high level, based on the PWM signal corresponding to the gear, the thyristor corresponding to the PWM signal is controlled to operate; wherein the gear includes a positive thyristor and a negative thyristor; When the enable signal corresponding to the gear position is at a low level, the thyristor of the gear position is prohibited from operating.

4. The reduction furnace power supply control method according to claim 3, characterized in that: The step of controlling the operation of the thyristor of the gear based on the PWM signal corresponding to the gear comprises: When the synchronization signal is in the positive half cycle, based on the PWM signal corresponding to the gear, the forward thyristor of the gear is controlled to operate; When the synchronization signal is in the negative half cycle, the negative thyristor of the gear is controlled to operate based on the PWM signal corresponding to the gear.

5. The reduction furnace power supply control method according to any one of claims 2 to 4, characterized in that: The thyristor voltage regulation system includes a first gear, a second gear, a third gear, a fourth gear and a fifth gear, and the thyristor operation of the corresponding gear is controlled according to the enable signal corresponding to each gear and the PWM signal; including: When the enable signals corresponding to the gears are all at high level, the thyristors of all the gears are controlled to operate based on the PWM signals; When the enable signal corresponding to the first gear is at a low level, and the enable signals corresponding to the other gears are all at a high level, the thyristors of the second gear, the third gear, the fourth gear, and the fifth gear are controlled to operate based on the PWM signals; When the enable signals corresponding to the first gear and the second gear are both at low levels, and the enable signals corresponding to the remaining gears are all at high levels, the thyristors of the third gear, the fourth gear, and the fifth gear are controlled to operate based on the PWM signals; When the enable signals corresponding to the first gear, the second gear and the third gear are all at low levels, and the enable signals corresponding to the remaining gears are all at high levels, the thyristors of the fourth gear and the fifth gear are controlled to operate based on the PWM signals.

6. The PWM signal generating method according to claim 1, characterized in that: The determining of the CMPA and CMPB corresponding to each gear position based on the PWM signal cycle and the dead zone angle of each gear position includes: The product of the ratio of the dead zone angle of each gear to 180° and the period of the PWM signal is used as the CMPA corresponding to each gear; The PWM signal period is used as the CMPB corresponding to each gear position.

7. A PWM signal generating device, characterized in that: include: A count value acquisition module, used to acquire the count value of each PWM counter; wherein each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control; A parameter determination module, used to determine the CMPA and CMPB corresponding to each gear based on the PWM signal period and the dead zone angle of each gear; The PWM signal determination module is used to set the corresponding PWM signal to 1 when the count value of the PWM counter is equal to CMPA; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to zero, so as to obtain the PWM signal corresponding to each gear.

8. A reduction furnace power supply control device, characterized in that: include: A PWM signal acquisition module is used to acquire the PWM signal of the thyristor corresponding to each gear; wherein, the count value of each PWM counter is acquired; wherein, each PWM counter is cleared at the zero crossing point of the synchronization signal through a soft phase-locked loop control; based on the PWM signal cycle and the dead zone angle of each gear, the CMPA and CMPB corresponding to each gear are determined; when the count value of the PWM counter is equal to CMPA, the corresponding PWM signal is set to 1; when the count value of the PWM counter is equal to CMPB, the corresponding PWM signal is cleared to generate a PWM signal; The gear operation module is used to control the operation of the thyristor of the corresponding gear according to the enable signal corresponding to each gear and the PWM signal.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the reduction furnace power supply control method and PWM signal generation method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the reduction furnace power supply control method and the PWM signal generation method as described in any one of claims 1 to 6 are implemented.

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