Manufacturing method of silicon-based switch filter bank and silicon-based switch filter bank

Abstract

The invention provides a manufacturing method of a silicon-based switch filter bank and the silicon-based switch filter bank. The method comprises an etching step, an isolating layer forming step, a metal layer forming step, a switch chip mounting step and a bonding step. The method sequentially comprises the following steps of: respectively etching through silicon vias on a lower bottom plate, a middle layer and an upper cover plate; forming substrate insulation isolation layers on the upper and lower surfaces of the lower bottom plate, the upper and lower surfaces of the middle layer, the upper and lower surfaces of the upper cover plate and the surface of the side wall of the silicon through hole; forming a metal layer outside the substrate insulation isolation layer; a silicon cavity is formed in the area, close to the lower bottom plate, in the middle layer, a switch chip is arranged on the lower bottom plate, and the switch chip is connected with the metal layer through a gold wire; and bonding the lower bottom plate, the middle layer and the upper cover plate to form a three-layer silicon-based substrate, so that the metal layer is interconnected with the lower bottom plate, the middle layer and the upper cover plate, and the switch chip is positioned in the silicon cavity. The miniaturization of the filter bank can be realized, and the energy consumption of the filter bank is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of filters, and in particular to a manufacturing method of a silicon-based switch filter group and the silicon-based switch filter group. Background Art

[0002] At present, whether in the field of civil communications or military radar, the requirements for the performance, volume, weight, etc. of the receiver are becoming more and more stringent. Since the superheterodyne receiver has a large receiving dynamic range, high adjacent channel selectivity and receiving sensitivity are widely adopted. The RF front end is an important part of the design of the superheterodyne receiver. Its main function is to convert the useful, broadband RF input signal into the required intermediate frequency signal through a series of processing. The excellent performance of the superheterodyne receiver depends largely on the design of the RF front end. The preselection filter mainly preselects the signal of the RF front end, filters out clutter and interference signals, and leaves the useful signal. Whether the filter index is reasonable and whether it can be achieved has an important impact on the various indicators of the entire receiver. The preselection filter generally includes two types: switch filter and tuned filter. For the switch filter, its design only needs to divide the frequency band according to the total index of the system, and then design the filter that meets the index, and finally select the switch for assembly. Therefore, the switch filter form has a wide range of application prospects in engineering due to its very intuitive implementation method and very flexible scheme design.

[0003] Traditional switch filter groups use metal shells as carriers, PCBs to make passive filters, and a large number of discrete electronic components. This makes traditional switch filters bulky, energy-intensive, and with poor manufacturing uniformity. They rely on manual adjustment, which seriously hinders the miniaturization and integration of RF front-end modules. Summary of the invention

[0004] The present invention provides a manufacturing method of a silicon-based switch filter group and a silicon-based switch filter group, which realize the miniaturization of the filter group and reduce the energy consumption of the filter group.

[0005] In a first aspect, the present invention provides a method for manufacturing a silicon-based switch filter group, the method comprising: Etching step, isolation layer forming step, metal layer forming step, switch chip mounting step and bonding step; wherein: The etching step includes: etching through silicon vias 4 on the lower base plate 1, the middle layer 2 and the upper cover plate 3, respectively, and forming a silicon cavity 7 in the middle layer near the lower base plate; The isolation layer forming step includes: forming a substrate insulating isolation layer 5 on the upper and lower surfaces of the lower base plate 1, the upper and lower surfaces of the intermediate layer 2, the upper and lower surfaces of the upper cover plate 3 and the side wall surface of the through silicon via 4; The metal layer forming step comprises: forming a metal layer 6 outside the substrate insulating isolation layer 5; The switch chip installation step includes: forming a silicon cavity 7 in the middle layer in a region close to the lower base plate, placing a switch chip 10 on the lower base plate 1, and connecting the switch chip 10 to the metal layer 6 through a gold wire 11; The bonding step includes: bonding the lower base plate 1, the middle layer 2 and the upper cover plate 3 to form a three-layer silicon-based substrate, so that the metal layer 6 interconnects the lower base plate 1, the middle layer 2 and the upper cover plate 3, and the switch chip 10 is located in the silicon cavity 7 of the middle layer 2.

[0006] In some embodiments, the metal layer 6 is grounded via the through silicon via 4; The first part of the metal layer, the upper cover plate 3 and the middle layer 2 constitute an upper filter 9; the second part of the metal layer, the lower base plate 1 and the middle layer 2 constitute a lower filter group 8; The first portion of the metal layer is the portion of the metal layer 6 located between the upper cover plate 3 and the middle layer 2 , and the second portion of the metal layer is the portion of the metal layer 6 located between the lower base plate 1 and the middle layer 2 .

[0007] In some embodiments, forming a metal layer 6 outside the substrate insulating isolation layer 5 includes: A metal seed layer is formed outside the substrate insulating isolation layer 5 on the surface of the lower base plate 1, the surface of the intermediate layer 2, the surface of the upper cover plate 3 and the side wall surfaces of the through silicon vias 4 of each layer; The metal seed layer is patterned to obtain a metal layer 6 .

[0008] In some embodiments, a metal seed layer is formed outside the substrate insulating isolation layer 5 on the surface of the lower base plate 1, the surface of the intermediate layer 2, the surface of the upper cover plate 3, and the side wall surfaces of the through silicon vias 4 of each layer, including: By magnetron sputtering or electron beam evaporation, a metal seed layer is formed outside the substrate insulating isolation layer 5 on the surface of the lower base plate 1, the surface of the intermediate layer 2, the surface of the upper cover plate 3 and the side wall surfaces of the silicon through vias 4 of each layer.

[0009] In some embodiments, the metal seed layer is patterned to obtain the metal layer 6, including: Photolithography and electroplating are performed on the metal seed layer to obtain thickened signal layer and ground layer metal, and wet etching is performed to obtain a patterned metal layer 6; or The metal seed layer is wet-etched to remove useless seed layers, and a patterned seed layer is obtained, which is then electroplated to form a metal layer.

[0010] In some embodiments, before the switch chip 10 is arranged on the lower base plate 1, the method further includes: A silicon cavity 7 is formed in the intermediate layer 2 near the lower base plate 1 by photolithography and dry etching, or by anisotropic wet etching.

[0011] In some embodiments, after etching the through silicon vias 4 on the lower base plate 1, the intermediate layer 2 and the upper cover plate 3 respectively by photolithography and deep silicon etching, the method further includes: The photoresist and the residual organic matter after etching on the lower base plate 1 , the middle layer 2 and the upper cover plate 3 are removed by a cleaning process.

[0012] In some embodiments, the lower base plate 1 , the middle layer 2 and the upper cover plate 3 are made of N-type doped high-resistance silicon wafers or P-type doped high-resistance silicon wafers.

[0013] In some embodiments, the thickness of any one layer of the three-layer silicon-based substrate is 150um, 250um or 400um; or, the thickness of each layer of the three-layer silicon-based substrate is 150um; or, the thickness of each layer of the three-layer silicon-based substrate is 250um; or, the thickness of each layer of the three-layer silicon-based substrate is 400um.

[0014] In some embodiments, the thickness of the metal layer after being thickened by electroplating should be at least 2 um.

[0015] In a second aspect, the present invention provides a silicon-based switch filter group manufactured by the manufacturing method described in the first aspect, comprising: A three-layer silicon-based substrate formed by bonding a lower base plate 1, an intermediate layer 2 and an upper cover plate 3, wherein each layer is provided with a through silicon via 4, and a silicon cavity 7 exists in a portion of the intermediate layer close to the lower base plate 1; Substrate insulating isolation layer 5; A metal layer 6 for achieving grounding and interconnection between layers via the through silicon via 4; The switch chip 10 is arranged on the surface of the lower base plate 1 and is located in the silicon cavity 7 , and is interconnected with the metal layer 6 through a gold wire 11 .

[0016] According to the present invention, three layers of silicon-based substrates are provided to respectively constitute a lower base plate, an intermediate layer and an upper cover plate, and silicon through holes distributed on each layer are etched to generate a substrate insulating isolation layer, and a metal layer for grounding and interconnection between each layer is formed through the silicon through holes; a lower filter group is formed by electrodes between the lower base plate and the intermediate layer; an upper filter group is formed by electrodes between the intermediate layer and the upper cover plate; a switch chip is arranged in the silicon cavity of the lower base plate and the intermediate layer, and through two bondings of three-layer wafers, a process route of gold wire bonding and gold-gold bonding is adopted to realize the integration of the switch chip and the multi-channel filter group, realize the multi-channel silicon-based switch filter group, realize the miniaturization of the filter group, and reduce the energy consumption of the filter group. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic flow chart of a method for manufacturing a silicon-based switch filter group provided by the present invention; Figure 2 The silicon-based switch filter group provided by the present invention; Figure 3 It is a schematic diagram of the silicon-based substrate provided by the present invention.

[0018] Description of reference numerals: 1: bottom base plate; 2: middle layer; 3: upper cover plate; 4: through silicon via; 5: substrate insulation isolation layer; 6: metal layer; 7: silicon cavity; 8: lower filter group; 9: upper filter; 10: switch chip; 11: gold wire; 12: silicon wafer. DETAILED DESCRIPTION

[0019] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a flow chart of a method for manufacturing a silicon-based switch filter group provided by the present invention, Figure 2 The silicon-based switch filter group provided by the present invention, Figure 2 The silicon-based switch filter bank shown can be composed of Figure 1 It is made by the production method shown.

[0021] like Figure 2 As shown, the silicon-based switch filter group may include: a three-layer silicon-based substrate formed by bonding a lower base plate 1, an intermediate layer 2 and an upper cover plate 3, wherein each layer is respectively distributed with silicon through vias 4, and a silicon cavity 7 exists in the portion of the intermediate layer close to the lower base plate 1; a substrate insulating isolation layer 5; a metal layer 6 that is grounded through the silicon through vias 4 and interconnected between the layers; a switch chip 10, wherein the switch chip 10 is arranged on the surface of the lower base plate 1 and is located in the silicon cavity 7, and is interconnected with the metal layer 6 through a gold wire 11.

[0022] like Figure 1As shown, the method for manufacturing the silicon-based switch filter group may include the following steps: Etching step 100, isolation layer forming step 110, metal layer forming step 120, switch chip mounting step 130 and bonding step 140; wherein: The etching step 100 includes: etching through silicon vias 4 on the lower base plate 1, the middle layer 2 and the upper cover plate 3, respectively, and forming a silicon cavity 7 in the middle layer near the lower base plate; Specifically, an N-type doped high-resistance silicon wafer can be first provided as the lower base plate 1, the middle layer 2 and the upper cover plate 3, or a P-type doped high-resistance silicon wafer can be provided as the lower base plate 1, the middle layer 2 and the upper cover plate 3; then a layer of silicon dioxide is grown on the surface of the lower base plate 1, the middle layer 2 and the upper cover plate 3 by thermal oxidation, and then a certain number of silicon through holes 4 are formed on the lower base plate 1, the middle layer 2 and the upper cover plate 3 according to preset design rules through a scheme of photolithography and deep silicon etching, and then the photoresist and etching residual organic matter can be removed through a cleaning process.

[0023] Figure 3 is a schematic diagram of a silicon-based substrate provided by the present invention, such as Figure 3 As shown, the silicon wafer can be used as a silicon-based substrate; the lower base plate 1, the middle layer 2 and the upper cover plate 3 of the switch filter are arranged in an array on the silicon wafer before bonding. Taking the upper cover plate 3 as an example, its minimum unit array is distributed on the silicon wafer 12, and the through holes 4 thereon are distributed as shown in FIG. Figure 3 As shown. Different filter group designs can adopt different through-hole distributions, which can be specifically set according to user needs, and the present invention does not limit this. Among them, the through hole 4 can be a circular hole with a diameter between 100um and 300um; it can also be a rectangular hole or a square hole with a side length between 100um and 300um. The spacing between the through holes must be greater than half of the characteristic size of the through hole itself. The distance between the boundary of the outermost through hole and the boundary of the layer where it is located (or the boundary of the switching filter) should be greater than or equal to 50um. Among them, for through holes in different layers, according to needs, some through holes can be distributed in completely different positions, that is, some through holes only pass through a single layer; some through holes can be in the same position, that is, some through holes can pass through two layers; very few through holes are distributed in the same position, that is, very few through holes are fully connected to three layers; the specific settings can be set according to the user's performance requirements for the filter, and the present invention does not limit this.

[0024] In one embodiment, a P-type doped high-resistance silicon wafer can be selected as the silicon wafer 12, a layer of silicon dioxide is grown by thermal oxidation, and then a photoresist with a through-hole pattern is prepared on the surface of the silicon wafer by a photolithography process, and then the silicon dioxide layer on the surface of the area corresponding to the through-hole pattern is first etched away by a dry etching method, and then a certain number of silicon through-holes 4 with a specific distribution are etched on the silicon wafer 12 by deep silicon etching, and then the photoresist and etching residual organic matter are removed by a cleaning process. Optionally, the thickness of the N-type doped high-resistance silicon wafer used in the present invention can be selected to be 150um, 250um or 400um, etc., or the thickness of the P-type doped high-resistance silicon wafer used in the present invention can be selected to be 150um, 250um or 400um, etc.

[0025] Optionally, the thickness of any layer of the three-layer silicon-based substrate is 150um, 250um or 400um; or, the thickness of each layer of the three-layer silicon-based substrate is 150um; or, the thickness of each layer of the three-layer silicon-based substrate is 250um; or, the thickness of each layer of the three-layer silicon-based substrate is 400um.

[0026] Optionally, the through silicon via 4 may be a square hole or a round hole.

[0027] After the etching step 100, the isolation layer forming step 110 includes: forming a substrate insulating isolation layer 5 on the upper and lower surfaces of the lower base plate 1, the upper and lower surfaces of the intermediate layer 2, the upper and lower surfaces of the upper cover plate 3 and the side wall surface of the through silicon via 4; Specifically, a layer of silicon dioxide can be grown on the substrate including the side wall surface of the through hole by thermal oxidation as the substrate insulating isolation layer 5, or a layer of silicon nitride can be grown as the substrate insulating isolation layer 5, or a double-layer film structure of silicon dioxide and silicon nitride can be grown as the substrate insulating isolation layer 5.

[0028] After the isolation layer forming step 110, the metal layer forming step 120 includes: forming a metal layer 6 outside the substrate insulating isolation layer 5; Specifically, a metal seed layer can be formed outside the substrate insulating isolation layer 5 on the surface of the lower base plate 1, the surface of the middle layer 2, the surface of the upper cover plate 3 and the side wall surfaces of the silicon through vias 4 of each layer; the metal seed layer is patterned to obtain a metal layer 6, and the metal seed layer is patterned to obtain a metal layer 6.

[0029] For example, a metal seed layer can be formed outside the substrate insulating isolation layer 5 on the surface of the lower base plate 1, the surface of the intermediate layer 2, the surface of the upper cover plate 3 and the side wall surfaces of the silicon through vias 4 of each layer by magnetron sputtering or electron beam evaporation.

[0030] Optionally, when the metal seed layer is patterned, the metal seed layer may be photolithographically processed and electroplated to obtain a thickened signal layer and ground layer metal, and then wet-etched to obtain a patterned metal layer 6; or The metal seed layer is wet-etched to remove useless seed layers, and a patterned seed layer is obtained, which is then electroplated to form a metal layer.

[0031] For example, the lower base plate 1, the middle layer 2 and the upper cover plate 3 formed with the metal seed layer can be immersed in molten gold liquid and molten chromium liquid respectively for wet etching to remove the useless seed layer, obtain the patterned seed layer and then perform electroplating to thicken it to form a metal layer.

[0032] After the metal layer forming step 120, the switch chip mounting step 130 includes: forming a silicon cavity 7 in the area near the lower base plate in the middle layer, placing a switch chip 10 on the lower base plate 1, and connecting the switch chip 10 to the metal layer 6 through a gold wire 11; Specifically, the switch chip 10 can be mounted on the surface of the lower base plate 1, and the switch chip 10 and the metal layer 6 can be interconnected through the gold wire 11; Specifically, a silicon cavity 7 can be formed in the portion of the intermediate layer 2 close to the lower base plate 1 by photolithography and dry etching, or by anisotropic wet etching. It should be noted that the silicon cavity 7 can be formed before or after the switch chip 10 is mounted on the surface of the lower base plate 1, and the present invention is not limited to this.

[0033] The silicon cavity 7 is used to accommodate the switch chip after the middle layer 2 and the upper cover plate 3 are bonded.

[0034] After the switch chip installation step 130, the bonding step 140 includes: bonding the lower base plate 1, the middle layer 2 and the upper cover plate 3 to form a three-layer silicon-based substrate, so that the metal layer 6 interconnects the lower base plate 1, the middle layer 2 and the upper cover plate 3, and the switch chip 10 is located in the silicon cavity 7 of the middle layer 2.

[0035] In some embodiments, the metal layer 6 is grounded via the through silicon via 4; The first part of the metal layer, the upper cover plate 3 and the middle layer 2 constitute an upper filter 9; the second part of the metal layer, the lower base plate 1 and the middle layer 2 constitute a lower filter group 8; The first portion of the metal layer is the portion of the metal layer 6 located between the upper cover plate 3 and the middle layer 2 , and the second portion of the metal layer is the portion of the metal layer 6 located between the lower base plate 1 and the middle layer 2 .

[0036] Specifically, the lower base plate 1, the middle layer 2 and the upper cover plate 3 can be bonded together in sequence by gold-gold hot pressing bonding; the lower base plate 1 and the middle layer 2 and the metal signal lines therebetween together constitute the lower filter group 8; the middle layer 2 and the upper cover plate 3 and the metal signal lines therebetween together constitute the upper filter group 9.

[0037] The present invention provides three layers of silicon-based substrates to respectively form a lower base plate, an intermediate layer and an upper cover plate, etches through silicon vias distributed on each layer to generate a substrate insulating isolation layer, and forms a metal layer for grounding and interconnection between each layer through the through silicon vias; a lower filter group is formed by electrodes between the lower base plate and the intermediate layer; an upper filter group is formed by electrodes between the intermediate layer and the upper cover plate; a switch chip is arranged in the silicon cavity of the lower base plate and the intermediate layer, and through two bondings of three-layer wafers, a gold wire bonding and gold-gold bonding process route is adopted to realize the integration of the switch chip and the multi-channel filter group, realize the multi-channel silicon-based switch filter group, realize the miniaturization of the filter group, and reduce the energy consumption of the filter group.

[0038] In one embodiment, the lower base plate 1 can be firstly manufactured: the silicon substrate adopts N-type doped high-resistance silicon wafer, a layer of silicon dioxide is grown by thermal oxidation, and then a certain number of silicon through holes 4 are formed according to certain design rules by photolithography and silicon etching, and then the photoresist and etching residual organic matter are removed by cleaning process; a layer of silicon dioxide isolation layer 5 is grown on the substrate including the side wall surface of the through hole by thermal oxidation; a metal seed layer is prepared on the front and back sides of the substrate and the side wall of the through hole by magnetron sputtering, and then a thickened signal layer and grounding layer metal are obtained by combining photolithography and electroplating technology, and then a patterned metal layer 6 is obtained by wet etching; then the switch chip 10 is mounted on the surface of the lower base plate 1, and the switch chip 10 and the metal layer 6 are interconnected by gold wire 11. Then the intermediate layer 2 is manufactured: the basic processing flow of the intermediate layer 2 is similar to that of the lower base plate 1, except that after the preparation of the metal layer 6 is completed, the silicon cavity 7 needs to be formed by photolithography and dry etching technology. The upper cover plate 3 is prepared by the same process as the lower base plate 1. Note that the upper cover plate 3 does not have a switch chip. Finally, the lower base plate 1, the middle layer 2 and the upper cover plate 3 are bonded together in turn by gold-gold hot pressing bonding; the lower base plate 1 and the middle layer 2 and the metal signal lines therebetween together form the lower filter group 8; the middle layer 2 and the upper cover plate 3 and the metal signal lines therebetween together form the upper filter group 9.

[0039] In one embodiment, the lower base plate 1 can be firstly manufactured: a P-type doped high-resistance silicon wafer, the thickness of which can also be selected to be 150um, 250um, 400um, etc., a layer of silicon nitride, or a double-layer membrane structure of silicon dioxide plus silicon nitride is grown by thermal oxidation, and then a certain number of silicon through holes 4 are formed according to certain design rules by a scheme of photolithography and deep silicon etching, and the silicon through holes 4 can be square holes or round holes, and then the photoresist and the residual organic matter after etching are removed by a cleaning process; a layer of silicon nitride, or a double-layer membrane structure of silicon dioxide plus silicon nitride is grown on the side wall surface of the substrate including the through hole by thermal oxidation as an isolation layer 5; a metal seed layer is prepared on the front and back surfaces of the substrate and the side wall of the through hole by electron beam evaporation, and then a patterned metal layer 6 is obtained by a subtractive process; then the switch chip 10 is mounted on the surface of the lower base plate 1, and the switch chip 10 and the metal layer 6 are interconnected by gold wires 11. Then make the middle layer 2: the basic processing flow of the middle layer 2 is similar to that of the lower base plate 1. The difference is that after the preparation of the metal layer 6 is completed, the silicon cavity 7 can be formed by an anisotropic wet etching scheme. The upper cover plate 3 is prepared by a process route that is exactly the same as the lower base plate 1. Note that the upper cover plate 3 does not have a switch chip. Finally, the lower base plate 1, the middle layer 2 and the upper cover plate 3 are bonded together in turn by gold-gold hot pressing bonding; the lower base plate 1 and the middle layer 2 and the metal signal lines therebetween together constitute the lower filter group 8; the middle layer 2 and the upper cover plate 3 and the metal signal lines therebetween together constitute the upper filter group 9.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a silicon-based switch filter group, characterized in that: The method comprises: Etching step, isolation layer forming step, metal layer forming step, switch chip mounting step and bonding step; wherein: The etching step comprises: etching through-silicon vias (4) on the lower base plate (1), the middle layer (2) and the upper cover plate (3) respectively; The isolation layer forming step comprises: forming a substrate insulating isolation layer (5) on the upper and lower surfaces of the lower base plate (1), the upper and lower surfaces of the intermediate layer (2), the upper and lower surfaces of the upper cover plate (3) and the side wall surface of the through silicon via (4); The metal layer forming step comprises: forming a metal layer (6) outside the substrate insulating isolation layer (5); The switch chip installation step comprises: forming a silicon cavity (7) in a region close to the lower base plate in the middle layer, arranging a switch chip (10) on the lower base plate (1), and connecting the switch chip (10) to the metal layer (6) via a gold wire (11); The bonding step comprises: bonding the lower base plate (1), the middle layer (2) and the upper cover plate (3) to form a three-layer silicon-based substrate, so that the metal layer (6) interconnects the lower base plate (1), the middle layer (2) and the upper cover plate (3), and the switch chip (10) is located in the silicon cavity (7) of the middle layer (2).

2. The method according to claim 1, characterized in that: The metal layer (6) is grounded via the through silicon via (4); The first metal layer, the upper cover plate (3) and the middle layer (2) constitute an upper filter (9); the second metal layer, the lower base plate (1) and the middle layer (2) constitute a lower filter group (8); The first portion of the metal layer is the portion of the metal layer (6) located between the upper cover plate (3) and the middle layer (2), and the second portion of the metal layer is the portion of the metal layer (6) located between the lower base plate (1) and the middle layer (2).

3. The method according to claim 1, characterized in that: A metal layer (6) is formed outside the substrate insulating isolation layer (5), comprising: Forming a metal seed layer outside the substrate insulating isolation layer (5) on the surface of the lower base plate (1), the surface of the middle layer (2), the surface of the upper cover plate (3) and the side wall surfaces of the through silicon vias (4) of each layer; The metal seed layer is patterned to obtain a metal layer (6).

4. The method according to claim 3, characterized in that: A metal seed layer is formed outside the substrate insulating isolation layer (5) on the surface of the lower base plate (1), the surface of the middle layer (2), the surface of the upper cover plate (3) and the side wall surfaces of the through silicon vias (4) of each layer, comprising: By magnetron sputtering or electron beam evaporation, a metal seed layer is formed outside the substrate insulating isolation layer (5) on the surface of the lower base plate (1), the surface of the middle layer (2), the surface of the upper cover plate (3) and the side wall surfaces of the silicon through holes (4) of each layer.

5. The production method according to claim 3 or 4, characterized in that: The metal seed layer is subjected to a patterning process to obtain a metal layer (6), comprising: Photolithography and electroplating are performed on the metal seed layer to obtain thickened signal layer and ground layer metal, and wet etching is performed to obtain a patterned metal layer (6); or The metal seed layer is wet-etched to remove useless seed layers, and a patterned seed layer is obtained, which is then electroplated to form a metal layer.

6. The production method according to any one of claims 1 to 4, characterized in that: Before arranging the switch chip (10) on the lower base plate (1), the method further comprises: By photolithography and dry etching, or by anisotropic wet etching, a silicon cavity (7) is formed in the portion of the intermediate layer (2) close to the lower base plate (1).

7. The production method according to any one of claims 1 to 4, characterized in that: After etching silicon through-holes (4) on the lower base plate (1), the intermediate layer (2) and the upper cover plate (3) respectively by photolithography and deep silicon etching, the method further comprises: The photoresist and etching residual organic matter on the lower base plate (1), the middle layer (2) and the upper cover plate (3) are removed through a cleaning process.

8. The production method according to any one of claims 1 to 4, characterized in that: The lower base plate (1), the middle layer (2) and the upper cover plate (3) are made of N-type doped high-resistance silicon wafers or P-type doped high-resistance silicon wafers.

9. The silicon-based switch filter group according to any one of claims 1 to 4, characterized in that: The thickness of any one layer of the three-layer silicon-based substrate is 150um, 250um or 400um; or, the thickness of each layer of the three-layer silicon-based substrate is 150um; or, the thickness of each layer of the three-layer silicon-based substrate is 250um; or, the thickness of each layer of the three-layer silicon-based substrate is 400um.

10. A silicon-based switch filter group manufactured by the manufacturing method according to claims 1 to 9, characterized in that: include: A three-layer silicon-based substrate formed by bonding a lower base plate (1), an intermediate layer (2) and an upper cover plate (3), wherein each layer is provided with a through-silicon via (4), and a silicon cavity (7) is present in a portion of the intermediate layer close to the lower base plate (1); Substrate insulating isolation layer (5); A metal layer (6) that is grounded and interconnected between layers via the through silicon via (4); A switch chip (10), wherein the switch chip (10) is arranged on the surface of the lower base plate (1) and is located in the silicon cavity (7), and is interconnected with the metal layer (6) via a gold wire (11).

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