Micro-size three-dimensional integrated filter based on three-port capacitor
By adopting the three-port capacitor and through-silicon array connection design in the three-dimensional integrated filter, the difficulties of size reduction and performance improvement in the prior art are solved, and the effects of high-density interconnection and high-quality signal transmission are achieved.
Patent Information
- Application Number
- CN202411892940.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-25
AI Technical Summary
Existing three-dimensional integrated filters have difficulties in reducing size and improving performance, and the integration of multiple discrete capacitors will result in increased parasitic losses, increased circuit size and increased layout difficulty.
Using a micro-size 3D integrated filter based on three-port capacitors, the three-port interdigit capacitors and spiral inductors at the top and bottom are connected through a through-silicon array, reducing the number of ports and interconnects, improving density and signal quality.
It realizes high-density interconnection, high-quality signal transmission, high capacitance density, compact three-dimensional structure, low dielectric loss and high quality factor, meeting the on-chip integration needs of passive filters.
Smart Images
Figure CN119892004A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of filter design, and in particular relates to a micro-sized three-dimensional integrated filter based on a three-port capacitor. Background Art
[0002] Modern electronic devices have increasingly higher requirements for miniaturization, high performance and low power consumption of RF signal processing devices. In the field of RF and microwave, filters are the core components of signal processing. Their function is to select the frequency and suppress noise of signals. Therefore, they are widely used in communications, radar, wireless sensing and other fields. Existing three-dimensional integrated filters usually use traditional capacitors and inductors, which are limited by materials, manufacturing processes and design methods. It is difficult to further reduce the size and are easily affected by parasitic effects, resulting in performance degradation. Capacitors are very important passive devices in modern communication systems and are widely used in analog, mixed analog, RF and microwave integrated circuits. When multiple discrete capacitors are integrated in a circuit, too many interconnects are often generated. Too many interconnects will introduce additional parasitic losses and affect the performance of the circuit; when multiple discrete capacitors are integrated, they will also face a series of problems such as increased circuit size, reduced space utilization, and increased layout difficulty. Therefore, the use of multiple discrete capacitors to integrate in the circuit can no longer meet the further development of RF and microwave integrated circuits. Summary of the invention
[0003] In order to solve the above problems existing in the prior art, the present invention provides a micro-sized three-dimensional integrated filter based on three-port capacitors.
[0004] The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0005] In a first aspect, the present invention provides a micro-sized three-dimensional integrated filter based on a three-port capacitor, the filter comprising: a top metal layer, a top isolation dielectric layer, a semiconductor substrate layer, a bottom isolation dielectric layer and a bottom metal layer;
[0006] The top metal layer, the top isolation dielectric layer, the semiconductor substrate layer, the bottom isolation dielectric layer and the bottom metal layer are arranged in sequence from top to bottom;
[0007] The top metal layer includes: a first top capacitor, a second top capacitor and a third top capacitor, a first top spiral inductor and a second top spiral inductor; the bottom metal layer includes: a first bottom capacitor, a second bottom capacitor, a third bottom capacitor, a first bottom spiral inductor and a second bottom spiral inductor; a plurality of through silicon via arrays are vertically distributed throughout the semiconductor substrate layer; the first top capacitor and the first bottom capacitor, the second top capacitor and the second bottom capacitor, the third top capacitor and the third bottom capacitor, the first top spiral inductor and the first bottom spiral inductor, and the second top spiral inductor and the second bottom spiral inductor are all connected through the through silicon via array.
[0008] Optionally, the top metal layer also includes: a top capacitor common end; the bottom metal layer also includes: a bottom capacitor common end; the first top capacitor, the second top capacitor and the third top capacitor constitute a top three-port interdigital capacitor through the top capacitor common end; the first bottom capacitor, the second bottom capacitor and the third bottom capacitor constitute a bottom three-port interdigital capacitor through the bottom capacitor common end.
[0009] Optionally, the top capacitor common terminal and the bottom capacitor common terminal are connected through the through silicon via array.
[0010] Optionally, the material of the first top capacitor, the second top capacitor and the third top capacitor, the first top spiral inductor, the second top spiral inductor, the common end of the top capacitor, the first bottom capacitor, the second bottom capacitor and the third bottom capacitor, the first bottom spiral inductor, the second bottom spiral inductor and the common end of the bottom capacitor is metal copper or aluminum.
[0011] Optionally, the top metal layer further includes: a first insulating medium; the bottom metal layer further includes: a second insulating medium; the first insulating medium is an insulating medium for forming the top three-port interdigital capacitor; the second insulating medium is an insulating medium for forming the bottom three-port interdigital capacitor.
[0012] Optionally, the first insulating medium and the second insulating medium are made of hafnium dioxide or other high dielectric constant materials.
[0013] Optionally, the material of the top isolation dielectric layer and the bottom isolation dielectric layer is silicon dioxide, silicon nitride or nitride oxide layer; the top isolation dielectric layer is used to achieve electrical isolation between the top metal layer and the semiconductor substrate layer; the bottom isolation dielectric layer is used to achieve electrical isolation between the bottom metal layer and the semiconductor substrate layer.
[0014] Optionally, the material of the semiconductor substrate layer is high-resistance silicon.
[0015] Optionally, each TSV in the TSV array consists of an isolation dielectric ring and an internal metal column from outside to inside.
[0016] Optionally, the material of the internal metal column is copper or aluminum; the material of the isolation dielectric ring is silicon dioxide, silicon nitride or a nitride oxide layer; and the isolation dielectric ring is used to achieve electrical isolation between the internal metal column and the semiconductor substrate layer.
[0017] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:
[0018] In the above technical solution, the filter uses a silicon through hole array penetrating the semiconductor substrate layer and a metal layer on the semiconductor surface to form a three-port three-dimensional integrated interdigital capacitor and a spiral inductor; the combination of the three-dimensional inductor and the three-port three-dimensional integrated interdigital capacitor forms a micro-sized three-dimensional integrated filter. Compared with the existing three discrete capacitor integration solutions, the six ports originally required for the integrated capacitor can be reduced to three ports, with the advantages of high-density interconnection, high-quality signal transmission, high capacitance density, compact three-dimensional structure, reduced lead-out terminals, low dielectric loss, high quality factor and flexible design size, so as to meet the multi-faceted development needs of on-chip integration of the increasingly developed passive filter.
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a structural schematic diagram of a micro-sized three-dimensional integrated filter based on three-port capacitors provided in an embodiment of the present invention.
[0021] Figure 2 It is a circuit schematic diagram of a micro-sized three-dimensional integrated filter based on three-port capacitors provided in an embodiment of the present invention.
[0022] Figure 3 It is a cross-sectional view of a micro-sized three-dimensional integrated filter based on a three-port capacitor provided in an embodiment of the present invention.
[0023] Figure 4 It is a structural schematic diagram of an isolation dielectric layer provided by an embodiment of the present invention.
[0024] Figure 5 It is a structural schematic diagram of a semiconductor substrate layer provided by an embodiment of the present invention.
[0025] Figure 6 It is a schematic diagram of experimental results of a micro-sized three-dimensional integrated filter based on three-port capacitors provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0026] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0027] Figure 1 is a schematic diagram of the structure of a micro-sized three-dimensional integrated filter based on a three-port capacitor provided by an embodiment of the present invention, such as Figure 1 As shown, the filter includes: a top metal layer, a top isolation dielectric layer, a semiconductor substrate layer, a bottom isolation dielectric layer and a bottom metal layer;
[0028] A top metal layer, a top isolation dielectric layer, a semiconductor substrate layer, a bottom isolation dielectric layer and a bottom metal layer are arranged in sequence from top to bottom;
[0029] The top metal layer includes: a first top capacitor, a second top capacitor and a third top capacitor, a first top spiral inductor and a second top spiral inductor; the bottom metal layer includes: a first bottom capacitor, a second bottom capacitor, a third bottom capacitor, a first bottom spiral inductor and a second bottom spiral inductor; a plurality of through silicon via arrays are vertically distributed throughout the semiconductor substrate layer; the first top capacitor and the first bottom capacitor, the second top capacitor and the second bottom capacitor, the third top capacitor and the third bottom capacitor, the first top spiral inductor and the first bottom spiral inductor, and the second top spiral inductor and the second bottom spiral inductor are all connected through the through silicon via array.
[0030] Optionally, the top metal layer also includes: a top capacitor common end; the bottom metal layer also includes: a bottom capacitor common end; the first top capacitor, the second top capacitor and the third top capacitor constitute a top three-port interdigital capacitor through the top capacitor common end; the first bottom capacitor, the second bottom capacitor and the third bottom capacitor constitute a bottom three-port interdigital capacitor through the bottom capacitor common end.
[0031] Optionally, the top capacitor common terminal and the bottom capacitor common terminal are connected through a through silicon via array.
[0032] It can be understood that the top three-port interdigital capacitor and the bottom three-port interdigital capacitor together form a three-port interdigital capacitor, and port one, port two and port three are as shown in FIG. Figure 1 As shown in . The ports led out by the lateral forks can be used as electrodes 1 and 2 of a micro-sized three-dimensional integrated filter based on a three-port capacitor, and the ports led out by the longitudinal forks can be used as ground terminals of a micro-sized three-dimensional integrated filter based on a three-port capacitor. In addition to the capacitor, the top capacitor common terminal and the bottom capacitor common terminal are also connected through a through-silicon via array.
[0033] It is worth mentioning that since the capacitor used is a three-port three-dimensional integrated finger capacitor based on a through silicon via array, the slow wave effect of the finger capacitor can achieve a smaller size, and compared with the traditional parallel plate capacitor, it has lower dielectric loss, higher quality factor, better harmonic suppression and more flexible size design; since the structural characteristics of the three-port capacitor are consistent with the effect of using three discrete capacitors to interconnect separately, compared with the traditional discrete capacitor interconnection scheme, it has fewer interconnection ports, fewer interconnection lines between devices, higher capacitance density, more uniform field strength distribution, lower loss and smaller size; and, since the number of ports and the interconnection length between devices are reduced, the parasitic parameters in the filter circuit are reduced, the size of the capacitor and the entire circuit is reduced, the complexity of the filter circuit layout and wiring is reduced, and the self-resonance frequency and quality factor are improved.
[0034] In addition, since there are three different ports, it can be used as a three-port capacitor when the circuit needs to connect different ports separately; when only two ports are needed, two of the ports can be combined in pairs, and the circuit is equivalent to two capacitors in parallel and in series with the third capacitor, which can achieve more flexible design solutions and greater capacitance density.
[0035] In one embodiment, the first top capacitor and the first bottom capacitor can form a capacitor C1 through a through silicon via array, the second top capacitor and the second bottom capacitor can form a capacitor C2 through a through silicon via array, the third top capacitor and the third bottom capacitor can form a capacitor C3 through a through silicon via array, the first top spiral inductor and the first bottom spiral inductor can form a spiral inductor L1 through a through silicon via array, and the second top spiral inductor and the second bottom spiral inductor can form a spiral inductor L2 through a through silicon via array. Figure 2 is a circuit schematic diagram of a micro-sized three-dimensional integrated filter based on a three-port capacitor provided by an embodiment of the present invention, such as Figure 1 and Figure 2 As shown, in the circuit principle diagram of the present invention, the upper plate of capacitor C2 is connected to port one and the input end of spiral inductor L1 respectively, and the lower plate of capacitor C2 is connected to the upper plate of capacitor C3, the upper plate of capacitor C1, the output end of spiral inductor L1 and the input end of spiral inductor L2 respectively; the upper plate of capacitor C3 is connected to the lower plate of capacitor C2, the upper plate of capacitor C1, the output end of spiral inductor L1 and the input end of spiral inductor L2 respectively, and the lower plate of capacitor C3 is connected to the output end of spiral inductor L2 and port two; the upper plate of capacitor C1 is connected to the lower plate of capacitor C2, the upper plate of capacitor C3, the output end of inductor L1 and the output end of inductor L2, and the lower plate of capacitor C1 is grounded as port three.
[0036] Optionally, the material of the first top capacitor, the second top capacitor and the third top capacitor, the first top spiral inductor, the second top spiral inductor, the top capacitor common end, the first bottom capacitor, the second bottom capacitor and the third bottom capacitor, the first bottom spiral inductor, the second bottom spiral inductor and the bottom capacitor common end is metal copper or aluminum.
[0037] Optionally, the top metal layer further includes: a first insulating medium; the bottom metal layer further includes: a second insulating medium; the first insulating medium is an insulating medium for forming a top three-port interdigital capacitor; the second insulating medium is an insulating medium for forming a bottom three-port interdigital capacitor.
[0038] It is understood that the first insulating medium and the second insulating medium can be in the form of grooves on the top metal layer and the bottom metal layer, and the top three-port interdigital capacitor and the bottom three-port interdigital capacitor can be placed therein. Using insulating materials as dielectrics can achieve higher capacitance density and reduce the equivalent series resistance of the capacitor.
[0039] Optionally, the materials of the first insulating medium and the second insulating medium are hafnium dioxide or other high dielectric constant materials.
[0040] Optionally, the materials of the top isolation dielectric layer and the bottom isolation dielectric layer are silicon dioxide, silicon nitride or nitride oxide layer; the top isolation dielectric layer is used to achieve electrical isolation between the top metal layer and the semiconductor substrate layer; the bottom isolation dielectric layer is used to achieve electrical isolation between the bottom metal layer and the semiconductor substrate layer.
[0041] Understandably, Figure 3 is a cross-sectional view of a micro-sized three-dimensional integrated filter based on a three-port capacitor provided by an embodiment of the present invention, Figure 4 is a schematic diagram of the structure of an isolation dielectric layer provided by an embodiment of the present invention, such as Figure 3 and Figure 4 As shown, there are multiple holes on the top isolation dielectric layer and the bottom isolation dielectric layer, and the through silicon via array can pass through these holes to connect corresponding devices.
[0042] Optionally, the material of the semiconductor substrate layer is high-resistance silicon.
[0043] Optionally, each through silicon via in the through silicon via array consists of an isolation dielectric ring and an internal metal column from outside to inside.
[0044] Optionally, the material of the internal metal column is copper or aluminum; the material of the isolation dielectric ring is silicon dioxide, silicon nitride or a nitride oxide layer; the isolation dielectric ring is used to achieve electrical isolation between the internal metal column and the semiconductor substrate layer.
[0045] Understandably, Figure 5is a schematic diagram of the structure of a semiconductor substrate layer provided by an embodiment of the present invention, such as Figure 5 As shown, a plurality of channels are vertically distributed in the semiconductor substrate layer as a through silicon via array, an isolation dielectric ring is provided on the inner wall of the through silicon via array, and an internal metal column passes through the isolation dielectric ring and the isolation dielectric layer to connect the devices in the top metal layer and the bottom metal layer.
[0046] In one embodiment, Figure 6 It is a schematic diagram of experimental results of a micro-sized three-dimensional integrated filter based on a three-port capacitor provided by an embodiment of the present invention. In this embodiment, capacitor C1 is set to 1.27pF, capacitor C2 and capacitor C3 are set to 0.1pF, spiral inductor L1 and spiral inductor L2 are set to 1.59nH, and the -3dB bandwidth of the micro-sized three-dimensional integrated filter based on the three-port capacitor is set at 4.75GHz. The S parameter results are obtained through finite element simulation. There is a transmission zero at 12.62GHz, which improves the isolation. The stop band S21 is less than -20dB, and it has good out-of-band characteristics.
[0047] In the above technical solution, the filter uses a silicon through hole array penetrating the semiconductor substrate layer and a metal layer on the semiconductor surface to form a three-port three-dimensional integrated interdigital capacitor and a spiral inductor; the combination of the three-dimensional inductor and the three-port three-dimensional integrated interdigital capacitor forms a micro-sized three-dimensional integrated filter. Compared with the existing three discrete capacitor integration solutions, the six ports originally required for the integrated capacitor can be reduced to three ports, with the advantages of high-density interconnection, high-quality signal transmission, high capacitance density, compact three-dimensional structure, reduced lead-out terminals, low dielectric loss, high quality factor and flexible design size, so as to meet the multi-faceted development needs of on-chip integration of the increasingly developed passive filter.
[0048] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.
[0049] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.
[0050] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.
[0051] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0052] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0053] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. A micro-sized three-dimensional integrated filter based on a three-port capacitor, characterized in that: The filter comprises: a top metal layer, a top isolation dielectric layer, a semiconductor substrate layer, a bottom isolation dielectric layer and a bottom metal layer; The top metal layer, the top isolation dielectric layer, the semiconductor substrate layer, the bottom isolation dielectric layer and the bottom metal layer are arranged in sequence from top to bottom; The top metal layer includes: a first top capacitor, a second top capacitor and a third top capacitor, a first top spiral inductor and a second top spiral inductor; the bottom metal layer includes: a first bottom capacitor, a second bottom capacitor, a third bottom capacitor, a first bottom spiral inductor and a second bottom spiral inductor; a plurality of through silicon via arrays are vertically distributed throughout the semiconductor substrate layer; the first top capacitor and the first bottom capacitor, the second top capacitor and the second bottom capacitor, the third top capacitor and the third bottom capacitor, the first top spiral inductor and the first bottom spiral inductor, and the second top spiral inductor and the second bottom spiral inductor are all connected through the through silicon via array.
2. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 1, characterized in that: The top metal layer also includes: a top capacitor common end; the bottom metal layer also includes: a bottom capacitor common end; the first top capacitor, the second top capacitor and the third top capacitor constitute a top three-port interdigital capacitor through the top capacitor common end; the first bottom capacitor, the second bottom capacitor and the third bottom capacitor constitute a bottom three-port interdigital capacitor through the bottom capacitor common end.
3. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 2, characterized in that: The top capacitor common terminal and the bottom capacitor common terminal are connected through the through silicon via array.
4. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 2, characterized in that: The materials of the first top capacitor, the second top capacitor and the third top capacitor, the first top spiral inductor, the second top spiral inductor, the common end of the top capacitors, the first bottom capacitor, the second bottom capacitor and the third bottom capacitor, the first bottom spiral inductor, the second bottom spiral inductor and the common end of the bottom capacitors are metal copper or aluminum.
5. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 2, characterized in that: The top metal layer further includes: a first insulating medium; the bottom metal layer further includes: a second insulating medium; the first insulating medium is an insulating medium for forming the top three-port interdigital capacitor; the second insulating medium is an insulating medium for forming the bottom three-port interdigital capacitor.
6. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 5, characterized in that: The first insulating medium and the second insulating medium are made of hafnium dioxide or other high dielectric constant materials.
7. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 1, characterized in that: The materials of the top isolation dielectric layer and the bottom isolation dielectric layer are silicon dioxide, silicon nitride or oxynitride layer; the top isolation dielectric layer is used to achieve electrical isolation between the top metal layer and the semiconductor substrate layer; the bottom isolation dielectric layer is used to achieve electrical isolation between the bottom metal layer and the semiconductor substrate layer.
8. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 1, characterized in that: The material of the semiconductor substrate layer is high-resistance silicon.
9. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 1, characterized in that: Each through silicon via in the through silicon via array is composed of an isolation dielectric ring and an internal metal column from outside to inside.
10. The micro-sized three-dimensional integrated filter based on three-port capacitor according to claim 9, characterized in that: The material of the internal metal column is metal copper or aluminum; the material of the isolation dielectric ring is silicon dioxide, silicon nitride or a nitride oxide layer; the isolation dielectric ring is used to achieve electrical isolation between the internal metal column and the semiconductor substrate layer.