Digital beam architecture forming method supporting flexible expansion

Abstract

A digital beam architecture forming method supporting flexible expansion decouples rapid change of market demands and development of a digital processing chip, adopts a single digital processing chip as the basic computing power of a digital beam forming system, and realizes that a system architecture is expanded or cut only through simple hardware in a large-scale chip stacking mode, so that the system architecture is more flexible to form. And different system requirements are quickly adapted with an efficient resource utilization rate, and the quality reliability and consistency of batch production of products are ensured while the period of putting the products into the market is shortened. According to the method, the traditional development thinking and design concept are broken through, the system indexes are used for adapting the chip capacity according to the index requirements of all the systems and the actual functions of the used chips, and flexible expansion of any digital beam forming system is achieved. The architecture design of the system by system designers is accelerated, a general system template can be gradually formed for a large-scale satellite-borne phased array system, and a development framework of the whole satellite system can be rapidly constructed on the basis of the general system template.

Description

Technical Field

[0001] The present invention belongs to the technical field of large-scale satellite-borne digital beamforming, and in particular relates to a digital beamforming architecture forming method supporting flexible expansion. Background Art

[0002] Large-scale satellite-borne phased array systems usually use analog beamforming, digital beamforming or hybrid beamforming. As the market continues to increase satellite communication capacity and flexibility, the market demand for satellite payload products based on digital beamforming technology has increased dramatically. The core indicators of digital beamforming technology mainly include the number of phased array channels, channel bandwidth and system beam capacity. Under the condition of a certain communication system, the beam capacity is proportional to the number of beams.

[0003] The core technical indicators of large-scale satellite-borne phased array digital beamforming systems are chip processing frequency and hardware resources, which are usually implemented using parallel digital processing chips (FPGA or ASIC, etc.). According to the current technological development at home and abroad, the resources of a single digital processing chip are far from meeting system requirements. For digital processing chips, their resource distribution is optimal for system A, but usually not for system B. To achieve the optimal solution for chip resource distribution under system B, it is necessary to redesign the digital processing chip. In the field of satellite payload products, digital processing chips have the characteristics of long development cycle, high software quality standards, and great difficulty in product batch production. The development of digital processing chips cannot be realized quickly in line with market demand. In order to meet different market demands, the design of digital processing chips must be solidified and the chip functions must be decoupled from system requirements.

[0004] Due to the difference in system requirements, the number of chips required for the system ranges from hundreds to thousands. Such large-scale digital processing chips must be built using a reasonable system architecture. Digital beamforming systems based on digital processing chips such as FPGA or ASIC take into account that no matter how the system requirements change, the digital beamforming algorithm has no essential difference, and only the system scale is adjusted. Therefore, it is necessary to propose a system that uses a single digital processing chip as the basic hardware unit, and the system is implemented through large-scale chip stacking and based on a unified system architecture. This has become a technical problem that must be solved. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a method for forming a digital beam architecture that supports flexible expansion, so that the system architecture can be quickly adapted to different system requirements with efficient resource utilization through simple hardware expansion or reduction, shortening the product launch cycle while ensuring the quality reliability and consistency of mass production of products.

[0006] To achieve the above object, the technical solution adopted by the present invention includes:

[0007] A method for forming a digital beam architecture supporting flexible expansion includes the following steps:

[0008] S1, obtain the number of channels N, beam width B, number of beams M and digital signal bit width W;

[0009] S2, define the chip data throughput T, chip hardware resource L and chip processing main frequency F;

[0010] S3, calculate and obtain storage resources C and digital computing resources D;

[0011] Specifically, the storage resource C is calculated by formula (1);

[0012] C=a×C w (1)

[0013] Where a represents the empirical coefficient of storage resource C, C w represents the required amount of resources, which is calculated by formula (2);

[0014]

[0015] Among them, N s Indicates the number of channels implemented by a single chip, M s Indicates the number of beams implemented by a single chip;

[0016] Specifically, the digital computing resource D is calculated by formula (3);

[0017] D=b×D w (3)

[0018] Where b represents the empirical coefficient of digital computing resource D, D w represents the required amount of resources, which is calculated by formula (4);

[0019]

[0020] S4, calculate the channel digital signal Q through equations (5) and (6) c Sum beam digital signal Q b ;

[0021] Q c =N S ×2×B×W (5)

[0022] Q b =M S ×2×B×W (6)

[0023] S5, if the chip resource conditions L>(C+D) and T>(Q c +Q b ), the obtained Ns and M s All are rounded up to get the required number of chips P as shown in formula (7), and finally the digital beam architecture that supports flexible expansion is obtained;

[0024] P=(N / N s )×(M / M s ) (7)

[0025] Otherwise, repeat S3-S5 until the chip resource condition is met.

[0026] Preferably, the value of a is 1.5.

[0027] Preferably, the value of b is 1.25.

[0028] A digital beam architecture supporting flexible expansion is prepared by a method for forming a digital beam architecture supporting flexible expansion disclosed in the present application.

[0029] Compared with the prior art, the advantages of the present invention are:

[0030] (1) The present invention provides a method for forming a digital beamforming architecture that supports flexible expansion, decoupling the rapid changes in market demand from the development of digital processing chips, using a single digital processing chip as the basic computing power of the digital beamforming system, and implementing a system architecture that can be quickly adapted to different system requirements with efficient resource utilization through simple hardware expansion or reduction through large-scale chip stacking. This shortens the product market launch cycle while ensuring the quality reliability and consistency of mass-produced products.

[0031] (2) The present invention provides a method for forming a digital beam architecture that supports flexible expansion. In the field of large-scale satellite-borne phased array digital beamforming systems, it breaks the traditional research and development thinking and design concepts. It no longer independently demonstrates and designs digital processing chips for each system. Instead, it uses system indicators to adapt chip capabilities based on the indicator requirements of each system and the actual functions of the chips used. Then, under a unified system architecture, it realizes the flexible expansion of any digital beamforming system.

[0032] (3) The method for forming a digital beam architecture that supports flexible expansion of the present invention accelerates the system architecture design by system designers. For large-scale satellite-borne phased array systems, a universal system template can be gradually formed, and based on this, a development framework for the entire satellite system can be quickly constructed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0034] Figure 1 Schematic diagram of tree-type cascade beam weighting calculation;

[0035] Figure 2 Schematic diagram of chain cascade beam weighting calculation;

[0036] Figure 3 Schematic diagram of the system architecture for channel and beam dimension expansion. DETAILED DESCRIPTION

[0037] The invention is not limited to the following specific embodiments, and all equivalent changes made on the basis of the technical solution of this application fall within the protection scope of the present invention. All components and devices in the present invention, unless otherwise specified, are all components and devices known in the prior art.

[0038] Example

[0039] This embodiment discloses a method for forming a digital beam architecture that supports flexible expansion, including the following steps:

[0040] S1, obtain the number of channels N, beam width B, number of beams M and digital signal bit width W.

[0041] In this embodiment, the system architecture of digital beamforming is designed according to four core indicators of the digital beamforming system: the number of channels N=100, the beam bandwidth B=2 GHz, the number of beams M=64, and the digital signal bit width W=32 bits. The architecture here mainly refers to the topological connection relationship of large-scale digital chips.

[0042] S2, clarify the chip data throughput T, chip hardware resource L and chip processing main frequency F.

[0043] This embodiment clearly analyzes the performance indicators of digital chips. In the face of different indicator requirements, there is no need to redesign and develop digital chips, and various requirements can be flexibly met by adjusting the system architecture. Digital chips are usually implemented using FPGA or ASIC. The digital beamforming system focuses on a total of three performance indicators: chip data throughput T, chip hardware resource L, and chip processing main frequency F.

[0044] The chip data throughput T disclosed in this embodiment assumes that the number of data interfaces of the system selected chip K=128 and the data interface rate S=25Gpbs, then the chip data throughput T=K×S=3.2Tbps.

[0045] The chip hardware resource amount L disclosed in this embodiment includes storage resources of about 108 Mbit (3000 minimum storage resource blocks, each block has a storage amount of about 36 Kbit), and digital computing resources of about 6400 multiplier resources.

[0046] The chip processing main frequency F disclosed in this embodiment is 400 MHz.

[0047] S3, calculate and obtain storage resources C and digital computing resources D;

[0048] Specifically, the storage resource C is calculated by formula (1);

[0049] C=a×C w (1)

[0050] Wherein, a represents the empirical coefficient of storage resource C, and in this embodiment, the value is 1.5; C w represents the required amount of resources, which is calculated by formula (2);

[0051]

[0052] Among them, N s Indicates the number of channels implemented by a single chip, M s Indicates the number of beams implemented by a single chip;

[0053] Specifically, the digital computing resource D is calculated by formula (3);

[0054] D=b×D w (3)

[0055] Wherein, b represents the empirical coefficient of the digital computing resource D, and in this embodiment, the value is 1.25; D w represents the required amount of resources, which is calculated by formula (4);

[0056]

[0057] The beam weighting algorithm is used to implement digital beamforming. Storage resources C and digital computing resources D are two core requirements. The required amount of resources is related to the three types of system indicators N, B, and M. Usually, a single chip requires sampling of all frequency band signals of the system indicators, that is, the indicator B is not split, and the N and M indicator requirements are achieved through hardware stacking of large-scale chips, defining the number of channels N achieved by a single chip s =10, number of beams M s =8, then the number of chips required P = (N / N s )×(M / M s )=10×8=80.

[0058] The storage resource C disclosed in this embodiment is mainly used to store beam weights. This is because the storage resources required for beam weights usually occupy more than 80% of the total resources. It is generally believed that the beam weights are the same as the beam signal bit width, and the required resource amount C w =2×N s ×M s×(2×B / F)×1=2×10×8×(2×5)×1=1600. Storage resource C=1.5×C w =1.5×1600=2400.

[0059] The digital computing resources D disclosed in this embodiment are mainly used for complex multiplication calculations of digital beam weighting networks. The required resource amount D w =2×N s ×M s ×(2×B / F)×3=2×10×8×(2×5)×3=4800. Digital computing resources D=1.25×D w =1.25×4800=6000.

[0060] S4, calculate the channel digital signal Q through equations (5) and (6) c Sum beam digital signal Q b ;

[0061] Q c =N S ×2×B×W (5)

[0062] Q b =M S ×2×B×W (6)

[0063] The data volume Q of a digital signal is related to the signal bit width, bandwidth, and quantity. For a channel digital signal Q c =N S ×2×B×W=10×2×2×32=1280Gbit, for the beam digital signal Q b =M S ×2×B×W=8×2×2×32=1024Gbit.

[0064] S5, if the chip resource conditions L>(C+D) and T>(Q c +Q b ), the obtained N s and M s All are rounded up to get the required number of chips P as shown in formula (7), and finally the digital beam architecture that supports flexible expansion is obtained;

[0065] P=(N / N s )×(M / M s ) (7)

[0066] Otherwise, repeat S3-S5 until the chip resource condition is met.

[0067] According to the chip resource evaluation of this embodiment, L can meet the requirements of 2400 36Kbit storage resource blocks and 6000 multiplier operation resource blocks, and T can meet the transmission requirements of the total data volume of channel digital signals and beam digital signals, so continue to execute subsequent steps.

[0068] The topological connection relationship between large-scale chips is designed from the two dimensions of channel expansion and beam expansion. In theory, the digital beam weighted network is a process of adding and summing a set of complex weighted signals, such as Figure 1 , 2 As shown in the figure. A single chip receives 10 channel signals, and after the digital beam weighting network operation, it outputs 8 beam signals. The channel received by a single chip is defined as the system subarray channel, and the beam formed by the subarray channel is defined as the system subarray beam. The subarray channel is cascaded through chips to achieve channel dimension expansion until the system indicator of 100 channels is met. The subarray beam is stacked through chips, and the beam dimension is expanded until the system indicator of 64 beams is met. Figure 3 It is a cascaded method, in which each DBF (digital beam forming) extension contains 2 DBF chips. When one extension is added in the row dimension, 20 channels are expanded; when one extension is added in the column dimension, 16 beams are expanded. It should be noted that the example expansion method here is not the only one. The technicians should optimize the expansion method in combination with the system design, such as tree expansion, chain expansion, etc. However, no matter which method is used, the system is expanded with a single chip as the basic component unit.

[0069] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0070] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations. In addition, the various different embodiments disclosed in this solution can also be combined arbitrarily, as long as they do not violate the ideas of this disclosure, they should also be regarded as the contents invented by this disclosure.

Claims

1. A method for forming a digital beam architecture supporting flexible expansion, characterized in that: The steps include: S1, obtain the number of channels N, beam width B, number of beams M and digital signal bit width W; S2, define the chip data throughput T, chip hardware resource L and chip processing main frequency F; S3, calculate and obtain storage resources C and digital computing resources D; Specifically, the storage resource C is calculated by formula (1); C=a×C w (1) Where a represents the empirical coefficient of storage resource C, C w represents the required amount of resources, which is calculated by formula (2); C w =2×N s ×M s ×(2×B / F)×1 [F≤B] C w =2×N s ×M s ×(2×F / B) ×1 [F>B] (2) Among them, N s Indicates the number of channels implemented by a single chip, M s Indicates the number of beams implemented by a single chip; Specifically, the digital computing resource D is calculated by formula (3); D=b×D w (3) Where b represents the empirical coefficient of digital computing resource D, D w represents the required amount of resources, which is calculated by formula (4); D w =2×N s ×M s ×(2×B / F)×3 [F≤B] D w =2×N s ×M s ×(2×F / B) ×3 [F>B] (4) S4, calculate the channel digital signal Q through equations (5) and (6) c Sum beam digital signal Q b ; Q c =N S ×2×B×W (5) Q b =M S ×2×B×W (6) S5, if the chip resource conditions L>(C+D) and T>(Q c +Q b ), the obtained N s and M s All are rounded up to get the required number of chips P as shown in formula (7), and finally the digital beam architecture that supports flexible expansion is obtained; P=(N / N s )×(M / M s ) (7) Otherwise, repeat S3-S5 until the chip resource condition is met.

2. The method for forming a digital beam architecture supporting flexible expansion according to claim 1, characterized in that: The value of a is 1.

5.

3. The method for forming a digital beam architecture supporting flexible expansion according to claim 1, characterized in that: The value of b is 1.

25.

4. A digital beam architecture supporting flexible expansion, characterized in that: The method for forming a digital beam architecture supporting flexible expansion is obtained by any one of claims 1-3.

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