Time Synchronization Method, Device, Management Controller, Medium and Product

Abstract

The present application discloses a time synchronization method, apparatus, management controller, medium and product. A processor, a first clock source and a second clock source are deployed in the management controller. The time accuracy of the first clock source is higher than that of the second clock source. When it is detected that the external Network Time Protocol (NTP) server is in an unavailable state, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source, and continuously monitors the frequency deviation of the first clock source. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the internal phase-locked loop of the second clock source is used to provide the clock signal, and the current time data is updated based on this clock signal. Through the master-slave clock dynamic switching mechanism of the first clock source and the second clock source, it is ensured that accurate time information can still be provided to the server by the management controller when the external NTP server is unavailable.

Description

Technical Field

[0001] This application relates to the technical field of server design, and particularly to a time synchronization method, apparatus, management controller, medium and product. Background Art

[0002] In a computer system, a server is the core of the entire network system and computing platform, and a lot of important data is stored on the server. The Baseboard Management Controller (BMC) is the steward of the server and plays a leading role in the overall management of the server. In data centers, industrial automation, and communication management controllers, the time synchronization accuracy directly affects the consistency of server system logs, the order of transaction processing, and the accuracy of fault diagnosis.

[0003] In related technologies, the BMC mainly performs time synchronization from an external NTP server through the Network Time Protocol (NTP) client mode. However, this method depends on the external network condition, and when the external network fails, it cannot provide accurate time information for the server. Therefore, how to provide accurate time information for the server when the external network fails is an urgent problem to be solved currently. Summary of the Invention

[0004] This application provides a time synchronization method, apparatus, management controller, medium and product to at least solve the problem in related technologies that accurate time information cannot be provided for the server when the external network fails.

[0005] This application provides a time synchronization method, which is applied to a management controller included in a target server. The management controller includes: a processor, a first clock source, and a second clock source, and the time accuracy of the first clock source is higher than that of the second clock source. The method is executed by the processor, and the method includes:

[0006] When it is detected that the external network time protocol server is in an unavailable state, enter the holdover mode;

[0007] In the holdover mode, control the clock signal output by the first clock source to be transmitted to the second clock source;

[0008] Control the second clock source to update the current time data according to the clock signal output by the first clock source;

[0009] When it is detected that the frequency deviation of the first clock source is not within the preset deviation range, control the second clock source to update the current time data by using the clock signal output by the phase-locked loop.

[0010] The present application also provides a time synchronization device, which is applied to a management controller included in a target server. The management controller includes: a processor, a first clock source, and a second clock source. The time accuracy of the first clock source is higher than that of the second clock source. The device is deployed in the processor and includes:

[0011] A monitoring module, configured to enter a timekeeping mode when it is detected that an external Network Time Protocol (NTP) server is in an unavailable state;

[0012] An output module, configured to control the clock signal output by the first clock source to be transmitted to the second clock source in the timekeeping mode;

[0013] A control module, configured to control the second clock source to update the current time data according to the clock signal output by the first clock source;

[0014] An update module, configured to control the second clock source to update the current time data by using the clock signal output by a phase-locked loop when it is detected that the frequency deviation of the first clock source is not within a preset deviation range.

[0015] The present application also provides a management controller, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above time synchronization methods when executing the computer program.

[0016] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above time synchronization methods are implemented.

[0017] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above time synchronization methods are implemented.

[0018] Through the present application, a processor, a first clock source, and a second clock source are deployed in the management controller. The time accuracy of the first clock source is higher than that of the second clock source. When it is detected that an external NTP server is in an unavailable state, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source, and the frequency deviation of the first clock source is monitored in real time. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the internal phase-locked loop of the second clock source is switched to provide a clock signal, and the current time data is updated based on this clock signal. Through the master-slave clock dynamic switching mechanism of the first clock source and the second clock source, it is ensured that when the external NTP server is unavailable, the management controller can still be used as an external NTP server to provide accurate time information for the server. Description of the Drawings

[0019] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the accompanying drawings required for use in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the hardware architecture for the operation of a time synchronization method provided by an embodiment of the present application;

[0021] Figure 2 Schematic diagram of one of the flowcharts of a time synchronization method provided by an embodiment of the present application;

[0022] Figure 3 Schematic diagram of another flowchart of a time synchronization method provided by an embodiment of the present application;

[0023] Figure 4 Schematic diagram of yet another flowchart of a time synchronization method provided by an embodiment of the present application;

[0024] Figure 5 Schematic diagram of still another flowchart of a time synchronization method provided by an embodiment of the present application;

[0025] Figure 6 Schematic diagram of the structure of a time synchronization device provided by an embodiment of the present application. Detailed implementation manners

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some, rather than all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0027] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or management controller including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or management controller. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] To enable those skilled in the art of the present technology to better understand the solution of the present application, the following will further elaborate on the present application in detail with reference to the accompanying drawings and specific implementation manners.

[0029] Glossary of Terms:

[0030] BMC: Baseboard Management Controller, a management controller unique to servers, used to manage and monitor the hardware status and operation of servers. The BMC is usually an independent microcontroller that runs on the server motherboard and is connected to other hardware components of the server (such as the CPU, memory, hard disk, etc.) through dedicated buses (I 2 C, SMBus). It has its own firmware and network interface and can operate independently of the server operating system.

[0031] RTC: Real-Time Clock, used to provide an accurate time reference for the management controller. It usually runs independently of the main processor and can continue to keep time even when the management controller is powered off or in sleep mode.

[0032] TCXO: Temperature Compensated Crystal Oscillator, a crystal oscillator that reduces the impact of temperature changes on the oscillation frequency through a built-in temperature compensation circuit. It can maintain high frequency stability over a wide temperature range and is widely used in fields with high requirements for frequency accuracy. The working principle of the TXCO is as follows: The ambient temperature is monitored by a temperature sensor and the temperature information is converted into a digital signal. These signals are used to adjust the load capacitance in the oscillation circuit, thereby compensating for the frequency offset caused by temperature changes. This compensation mechanism enables the TXCO to provide a stable frequency output under different temperature conditions.

[0033] I 2 C Bus: Inter-Integrated Circuit, a serial communication protocol bus mainly used in low-speed communication scenarios, such as communication between management controllers such as sensors and RTCs and microcontrollers or microprocessors. I 2 C Bus only requires two lines to achieve communication: SDA (data line) and SCL (clock line).

[0034] NTP: Network Time Protocol, a network protocol used to synchronize the clock of computer systems, widely used in the Internet and enterprise networks to ensure time consistency between management controllers. NTP transmits time information through the UDP protocol on port 123, can achieve high-precision time synchronization, and can tolerate network latency and clock drift.

[0035] RDMA: Remote Direct Memory Access, which is a technology that allows direct memory-to-memory data transfer between two management controllers without the intervention of the CPU, cache, and operating system. This technology significantly reduces latency, decreases CPU load, and improves data transfer efficiency, especially applicable to scenarios such as high-performance computing.

[0036] PPS: Pulse Per Second. The PPS alignment mechanism is a high-precision time synchronization technology. The PPS signal is an accurate time synchronization signal, usually generated by a high-precision clock source, which produces one pulse per second, and the rising edge precisely corresponds to the whole second of UTC time. The core of the PPS alignment mechanism is to adjust the local clock to achieve high-precision synchronization by comparing the difference between the PPS signal and the local clock.

[0037] In related technologies, there are mainly two time synchronization schemes. One scheme is that currently, most BMCs use an internal low-precision crystal oscillator as the clock source, whose frequency accuracy range is between ±50 ppm and ±100 ppm, and cooperate with the NTP protocol to synchronize time from an external NTP server. The implementation cost of this scheme is relatively low, but there are significant limitations. First, it is overly dependent on the network, and the NTP synchronization process is greatly affected by network latency, jitter, and interruption. For example, when the network is unstable, the NTP client cannot obtain time updates in a timely manner, resulting in the continuous accumulation of offsets in the local clock due to the inherent errors of the low-precision crystal oscillator, and the synchronization error may exceed 10 milliseconds. In addition, the synchronization interval of the NTP protocol itself is usually at the minute level. During the synchronization gap, the frequency deviation of the crystal oscillator will directly translate into a time error. More seriously, the performance of the low-precision crystal oscillator is easily affected by environmental temperature fluctuations. A temperature change of 10°C may introduce a frequency offset of ±5 ppm. If the server to which the BMC belongs operates in an environment with a large temperature difference, such as the alternating hot and cold channels in a data center, the time error accumulated over a long period will be further amplified, even affecting the reliability of basic functions such as system log recording and task scheduling. For time-sensitive scenarios such as financial transactions and industrial control, such errors are already beyond the acceptable range.

[0038] Another type of solution is to achieve time synchronization through an independent high-precision clock source, such as an oven-controlled crystal oscillator (OCXO) or an atomic clock, in combination with the PTP protocol. The OCXO improves the crystal oscillator frequency stability to below ±0.1 ppm through temperature control. The accuracy of an atomic clock can even reach the nanosecond level. With the PTP protocol, sub-microsecond-level synchronization can be achieved. However, this type of solution faces the dual challenges of hardware integration and cost. The OCXO requires additional circuitry to maintain a constant temperature environment. Its typical power consumption exceeds 1 W, and its physical size is relatively large, making it difficult to embed in space-constrained embedded modules such as BMCs. The cost of an atomic clock is as high as tens of thousands of yuan and is only applicable to special fields such as satellite navigation and quantum communication.

[0039] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the time synchronization method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0040] Embodiments of the present application provide a hardware architecture for running a time synchronization method. Referring to Figure 1 as shown, the hardware architecture includes: a target server cluster 100 composed of a target server 101 and at least one external server (in the embodiments of the present disclosure, the external servers include server 102, ……, server N); the target server 101 includes a management controller 11; the management controller 11 includes a processor 111, a first clock source 112, and a second clock source 113. When the processor 111 detects that the external network time protocol server is unavailable, it enters the timekeeping mode. In the timekeeping mode, the processor 111 controls the clock signal output by the first clock source 112 to be transmitted to the second clock source 113, and controls the second clock source 113 to update the current time data according to the clock signal output by the first clock source 112. When it detects that the frequency deviation of the first clock source 112 is not within the preset deviation range, it controls the second clock source 113 to update the current time data using the clock signal output by the phase-locked loop. Through the master-slave clock dynamic switching mechanism of the first clock source 112 and the second clock source 113, it is ensured that even when the external network time protocol server is unavailable, the management controller 11 can still be used as the external network time protocol server to provide accurate time information for the target server 101.

[0041] Further, referring to Figure 1As shown, the target server 101 further includes at least one internal component (in the embodiments of the present disclosure, taking the target server 101 including internal components 12, 13, and 14 as an example). After enabling the external network time protocol server function of the processor 111, the time data output by the second clock source is synchronized to at least one internal component through the integrated circuit bus. In the embodiments of the present disclosure, by using the processor 111 of the target server 101 as a primary NTP server to provide time synchronization services to other components of the target server 101, the dependence on external NTP requests is reduced, and the internal network time synchronization delay is greatly reduced.

[0042] Furthermore, referring to Figure 1 As shown, the target server cluster 100 includes the target server 101 and at least one external server (in the embodiments of the present disclosure, the external servers include server 102,..., server N). After enabling the external network time protocol server function of the processor, the time data output by the second clock source 113 of the target server 101 is synchronized to other external servers of the target server cluster 100. In the embodiments of the present disclosure, by using the processor 111 of the target server 101 as an NTP server to provide time synchronization services to other servers within the local area network, the problem that it is difficult to accurately synchronize the time of the server cluster in a network isolation environment is solved.

[0043] Based on the above problems, embodiments of the present application provide a time synchronization method, and the method will be described in detail in combination with the execution flow of the time synchronization method.

[0044] The time synchronization method provided by the embodiments of the present disclosure is mainly applied in a management controller, which is a server component with network service functions, including but not limited to BMC, integrated management module, NTP server, network management software, virtualization management module, and security module, etc. These components ensure the efficient operation and management of the server by providing network connection, management functions, time synchronization, storage access, and security functions. The first clock source is a high-precision clock source, including but not limited to temperature-compensated crystal oscillator TCXO and oven-controlled crystal oscillator OCXO. The time accuracy of the second clock source is slightly lower than that of the first clock source, including but not limited to various types of clock units, such as real-time clock RTC.

[0045] In the following disclosed embodiments, taking the management controller as BMC, the first clock source as a temperature-compensated crystal oscillator, and the second clock source as a real-time clock as an example for illustration, wherein, BMC includes: a temperature-compensated crystal oscillator, a real-time clock, and a processor.

[0046] Among them, a temperature-compensated crystal oscillator is a clock source that reduces the influence of frequency variation with temperature through an internal temperature sensor and compensation circuit. Its core principle is to monitor the ambient temperature in real time and dynamically adjust the output frequency of the crystal oscillator according to the pre-stored temperature-frequency characteristic curve, thereby improving the frequency stability to the range of ±0.5 ppm to ±2 ppm. In the BMC, the TCXO provides a highly stable reference clock signal for the system, significantly reducing the cumulative time error caused by temperature fluctuations.

[0047] A real-time clock is an independent timing module, usually powered by a backup battery, ensuring that time data such as year, month, day, hour, minute, and second can still be continuously recorded when the main power supply of the BMC is disconnected. The real-time clock integrates a low-frequency crystal oscillator inside, and its time accuracy depends on the stability of the crystal oscillator.

[0048] The processor is the core processor of the BMC, responsible for running the firmware, managing hardware resources, and executing time synchronization logic.

[0049] Furthermore, the temperature-compensated crystal oscillator and the real-time clock are integrated in the hardware layer of the BMC. Among them, the temperature-compensated crystal oscillator is connected to the processor through the I 2 C bus; the clock unit is connected to the processor through the I 2 C bus, achieving high-precision time synchronization between server components.

[0050] By integrating the clock unit and the temperature-compensated crystal oscillator to work together as a high-precision clock source in the BMC hardware layer, and using the I 2 C high-speed bus to connect to the BMC processor, high-precision time synchronization between server components is achieved.

[0051] Utilize the existing I 2 C bus of the BMC to connect the temperature-compensated crystal oscillator and the clock unit, without the need to additionally add dedicated clock wiring, reducing the single-board transformation cost.

[0052] Refer to Figure 2 As shown, the time synchronization method provided by the embodiment of the present invention includes the following steps:

[0053] S21. When it is detected that the external network time protocol server is in an unavailable state, enter the holdover mode.

[0054] Among them, the external NTP server can be understood as a dedicated time server deployed in the network, providing standard time data following the NTP protocol. Its role is to provide an authoritative time reference for the BMC, usually communicating through UDP port 123. The externality is reflected in its physical location being independent of the local management controller and relying on the network link reachability.

[0055] The unavailable state refers to the state where the NTP server cannot respond to requests normally, which may be caused by network interruptions (such as routing failures, firewall blocks), server outages, high latency (exceeding the protocol tolerance threshold), or configuration errors (such as IP address changes). In the unavailable state, the BMC cannot obtain time updates through the NTP protocol, and the local clock will deviate from the external time reference.

[0056] The timekeeping mode means that when the BMC loses the external high-precision time source (such as GPS or Beidou satellite signals, etc.), it relies on the local high-precision crystal oscillator or RTC (Real-Time Clock) to continue providing time synchronization services. The timekeeping mode is a local time retention mechanism, and its core goal is to reduce the error accumulation caused by external synchronization interruptions. It can also be understood that the generation of time data is achieved through the cooperation of the hardware and software integrated within the BMC. Among them, the hardware includes: using TCXO or OCXO to provide a low-drift clock signal, and the software algorithm includes drift prediction and real-time compensation based on historical synchronization data.

[0057] Optionally, detecting that the external NTP server is in an unavailable state includes: the BMC periodically sends time query requests (NTP packets) to the NTP server. If no valid response is received or the response times out continuously for multiple times, it is determined that the external NTP server is in an unavailable state.

[0058] Optionally, detecting that the external NTP server is in an unavailable state includes: the BMC detects the physical link connection status through the underlying network interface. If the physical connection of the network interface is disconnected (such as the network cable being unplugged), it is determined that the external NTP server is in an unavailable state, without the need for upper-layer protocol detection.

[0059] Specifically, when the external NTP server is in an available state, obtain the time data provided by the external NTP server. When the external NTP server is in an unavailable state, enter the timekeeping mode, execute the subsequent process, and obtain accurate time data.

[0060] In some embodiments, the BMC network configuration and NTP synchronization can be achieved in the following ways:

[0061] Enable the BMC network interface, select static IP address binding or DHCP dynamic acquisition according to actual needs, and specify the external NTP server address in the BMC system settings, so that the BMC's own time is accurately synchronized with the standard time, and at the same time write the standard time into the clock unit.

[0062] Through the above steps, it can be ensured that the BMC network interface works properly, and high-precision time synchronization is achieved through an external authoritative NTP server. At the same time, the standard time is written into the clock unit to ensure the accuracy and reliability of the server time.

[0063] In some embodiments, before performing the above step S21 (when it is detected that the external network time protocol server is in an unavailable state, enter the timekeeping mode), the following steps may also be performed:

[0064] After detecting that the target server is powered on, obtain a timestamp from the second clock source;

[0065] Transmit the timestamp to the first clock source, and control the first clock source to generate and output a clock signal with the timestamp as the initial time reference.

[0066] Specifically, before using the temperature-compensated crystal oscillator and the clock unit to provide high-precision time data, when the server is powered on, it is necessary to initialize the temperature-compensated crystal oscillator and the clock unit. That is, after detecting that the target server is powered on, obtain a timestamp from the clock unit and transmit it to the temperature-compensated crystal oscillator, so that the temperature-compensated crystal oscillator generates and outputs a clock signal with the timestamp as the initial time reference. Among them, the clock unit has an internal independent power supply and can continuously maintain a 32.768 kHz clock signal during system power-off, and its error can normally be controlled within ±5 ppm.

[0067] Among them, the target server refers to the server to which the baseboard management controller belongs, and can be a computer, a network management controller, or other electronic systems. Server power-on refers to the process of the server being powered on, which is a physical condition for triggering subsequent operations and belongs to the initial stage of system startup.

[0068] The timestamp is the precise time data generated by the clock unit, reflecting the absolute time value at the moment when the management controller is powered on, and serving as the time reference for system synchronization.

[0069] Specifically, after the server is powered on, the temperature-compensated crystal oscillator starts to work first. When the temperature-compensated crystal oscillator works, the internal crystal oscillator generates an oscillation signal. Due to the physical characteristics of the crystal being affected by temperature, its frequency will drift with the change of temperature. The temperature-compensated crystal oscillator is built with a temperature compensation circuit, which will monitor the ambient temperature in real time and adjust the oscillation frequency according to the pre-stored temperature-frequency characteristic curve, so that the output frequency remains relatively stable within a wide temperature range, and the frequency stability is ≤±0.5 ppm.

[0070] While the temperature-compensated crystal oscillator is powered on and working, the BMC reads the initial time reference stored in the real-time clock through the I 2 C bus. Among them, the real-time clock provides a second-level timestamp to the BMC through the I 2 C interface as the initial time reference before the frequency of the temperature-compensated crystal oscillator is stabilized, to ensure the time continuity during the cold start phase. The temperature-compensated crystal oscillator will pass the stabilized clock signal through the I2 The SCL line of the I2C bus is transmitted to the BMC processor, providing a high-precision reference clock signal for the BMC.

[0071] S22. In the timekeeping mode, control the clock signal output by the first clock source to be transmitted to the second clock source.

[0072] Among them, the first clock source is a temperature-compensated crystal oscillator, and the second clock source is a clock unit.

[0073] The timekeeping mode refers to the operating state in which the system autonomously maintains time accuracy relying on the local clock source when the external NTP server fails. In this mode, the BMC stops requesting time synchronization from the external server and instead continuously measures time through internal high-stability hardware such as TCXO and algorithm compensation mechanisms.

[0074] Among them, the clock signal refers to the periodic electrical signal generated by the TCXO. It can be a square wave or a sine wave and serves as the time reference for the BMC.

[0075] In the timekeeping mode, the clock signal output by the temperature-compensated crystal oscillator is sent to the clock input pin of the clock unit through a buffer, driving the internal counter of the clock unit to increment to generate accurate time data.

[0076] Controlling the clock signal output by the temperature-compensated crystal oscillator to be transmitted to the clock unit may include outputting a control instruction to the temperature-compensated crystal oscillator, and this control instruction is used to instruct the temperature-compensated crystal oscillator to act as the main clock source and transmit its output clock signal to the clock unit.

[0077] Optionally, a temperature compensation circuit is set in the temperature-compensated crystal oscillator, and the temperature compensation circuit is used to detect the ambient temperature in real time and compensate the frequency of the temperature-compensated crystal oscillator based on the ambient temperature and the pre-stored temperature-frequency specific curve.

[0078] The temperature-compensated crystal oscillator is an electronic component that maintains frequency stability through temperature compensation technology. Its internal components include a crystal oscillator and a temperature compensation circuit. The crystal oscillator generates an oscillation signal based on the piezoelectric effect, but its frequency will drift with changes in the ambient temperature. The temperature compensation circuit, as a key compensation module, includes a temperature detection unit, a storage unit, and a compensation signal generation unit.

[0079] The ambient temperature refers to the real-time temperature value of the working environment where the oscillator is located and is the main external variable affecting frequency stability. The temperature detection unit collects ambient temperature data in real time through an integrated temperature sensor to form a temperature detection signal. The pre-stored temperature-frequency specific curve is a set of calibrated compensation parameters, usually solidified in the memory in the form of a data table or a function, reflecting the compensation amount required by this type of crystal oscillator at different temperature points.

[0080] Specifically, first, the temperature detection unit obtains the ambient temperature parameter as the input of the compensation system. Second, the compensation algorithm calls the stored temperature-frequency correspondence data to calculate the compensation coefficient corresponding to the current temperature. Finally, a compensation signal is generated through digital-to-analog conversion or a variable capacitance network and superimposed on the oscillation circuit to cancel the temperature drift. The entire system forms a closed-loop control, and the oscillation frequency is corrected in real time through the feedforward compensation mechanism, so that the output frequency is stabilized near the nominal value. Each functional module realizes the timing coordination of data acquisition, parameter matching, and physical quantity adjustment through the signal chain to ensure that the temperature change and the compensation action are kept in real-time synchronization.

[0081] Due to the fact that the physical characteristics of the crystal are affected by temperature, its frequency will drift with the change of temperature. The temperature-compensated crystal oscillator is built-in with a temperature compensation circuit, which will monitor the ambient temperature in real time and adjust the oscillation frequency according to the pre-stored temperature-frequency characteristic curve, so that the output frequency remains relatively stable within a wide temperature range, and the frequency stability is ≤±0.5ppm.

[0082] The high-stability clock source of the temperature-compensated crystal oscillator is calibrated in real time through the temperature compensation circuit, and the local clock frequency stability is controlled within ±0.5ppm, so that the timing accuracy of the NTP server is improved from the millisecond level to the sub-millisecond level, meeting the microsecond-level time synchronization requirements of scenarios such as financial transactions and scientific calculations.

[0083] S23. Control the second clock source to update the current time data according to the clock signal output by the first clock source.

[0084] Among them, the clock unit is an independent timing module, usually integrated with a 32.768kHz low-frequency crystal oscillator and a backup power supply, and is used to continuously record time data when the system is powered off, such as: year, month, day, hour, minute, and second.

[0085] The clock unit saves the current time value through the internal timing register; the clock unit receives the periodic clock signal output by the external temperature-compensated crystal oscillator and drives the timing register to increment to realize the update of time data.

[0086] Updating the time data refers to the operation of the clock unit using the periodic clock signal output by the temperature-compensated crystal oscillator to correct the internal timing value. The specific process is as follows: The periodic clock signal output by the temperature-compensated crystal oscillator is divided into low-frequency pulses, and each pulse triggers the internal timing register of the clock unit to increase. In other words, the TCXO provides a high-stability clock signal to drive the counter of the clock unit to increment at a fixed frequency.

[0087] The control clock unit updates the time data according to the clock signal output by the temperature-compensated crystal oscillator, which may include outputting a control instruction to the clock unit. The control instruction is used to instruct the clock unit to use the clock signal output by the temperature-compensated crystal oscillator as the input clock signal, and drive the timing register of the clock unit to increment at a fixed frequency.

[0088] S24. When it is monitored that the frequency deviation of the first clock source is not within the preset deviation range, control the second clock source to update the current time data by using the clock signal output by the phase-locked loop.

[0089] Among them, the frequency deviation can be understood as the difference between the actual output frequency of the TCXO and the nominal frequency (such as 26 MHz), usually quantified in ppm (parts per million). For example, if the nominal frequency is 26,000,000 Hz and the actual output is 25,999,948 Hz, the deviation is -62 Hz, that is, -2 ppm.

[0090] The preset deviation range refers to the predefined acceptable frequency error threshold, which can be determined according to actual needs and is not specifically limited here. For example, if the allowable deviation is set to ±5 ppm, when it is detected that the TCXO frequency deviation reaches ±7 ppm, the abnormal handling process is triggered.

[0091] The phase-locked loop refers to a circuit or module that synchronizes the phase of the input signal with the reference signal through a feedback mechanism and outputs a stable clock signal. In the clock unit, the PLL may be used to multiply the frequency of a low-frequency reference signal (such as 32.768 kHz) to a higher frequency (such as 1 MHz) to improve the timing resolution; filter out the phase noise of the input clock signal to ensure that the counting pulse intervals are uniform.

[0092] Optionally, controlling the clock unit to update the time data by using the clock signal output by its phase-locked loop may include: sending an instruction to the clock unit through the processor I²C bus to adjust its working mode or input clock source. For example, sending a configuration command to make the clock unit switch to the clock signal generated by the phase-locked loop (PLL).

[0093] An embodiment of the present application provides a time synchronization method. A processor, a first clock source, and a second clock source are deployed in a management controller. The time accuracy of the first clock source is higher than that of the second clock source. When it is detected that an external Network Time Protocol (NTP) server is unavailable, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source, and continuously monitors the frequency deviation of the first clock source. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the internal phase-locked loop of the second clock source is switched to provide the clock signal, and the current time data is updated based on this clock signal. Through the master-slave clock dynamic switching mechanism of the first clock source and the second clock source, it is ensured that even when the external NTP server is unavailable, the management controller can still be used as an external NTP server to provide accurate time information for the server.

[0094] Based on the above embodiment, an embodiment of the present application provides a time synchronization example. Referring to Figure 3 as shown, the process of the time synchronization example of the present application mainly includes steps S301 - 309.

[0095] S301. When the server is powered on, initialize the temperature-compensated crystal oscillator and the clock unit.

[0096] S302. Determine whether the external NTP server is available. If it is, execute S309; otherwise, execute S303.

[0097] S303. Enter the holdover mode.

[0098] S304. Set the temperature-compensated crystal oscillator as the master clock source and output a clock signal.

[0099] S305. Determine whether the frequency deviation of the temperature-compensated crystal oscillator is within the set deviation range. If not, execute S306; if so, execute S307 - S308.

[0100] S306. Control the clock unit to update the time data according to the clock signal output by the temperature-compensated crystal oscillator.

[0101] S307. Control the clock unit to take over the clock distribution function and generate an alarm signal.

[0102] S308. Control the clock unit to update the time data using the clock signal output by its phase-locked loop.

[0103] S309. The BMC obtains the time data provided by the external NTP server.

[0104] The specific processes in S301 - S309 can be referred to the descriptions in the above - mentioned embodiments, and will not be elaborated in detail in the embodiments of the present application.

[0105] In the embodiments of the present application, a dual - redundant timing mechanism is provided. When the temperature - compensated crystal oscillator has a frequency deviation exceeding ±5ppm due to environmental mutations (such as a sudden temperature change of ±20°C), it automatically switches to the compensated clock of the clock unit and generates an alternative signal through a phase - locked loop to ensure clock continuity. This mechanism shortens the critical service interruption time to within 50ms.

[0106] The time - synchronization method in the embodiments of the present application can also extend the autonomous timing period. The temperature - compensated crystal oscillator provides high - precision timing for 24 hours (error < 1ms), and the clock unit maintains basic timing for 7 days (error < ±2ppm) through an independent power supply. The combined time - synchronization scheme of the two enables the system to have a monthly cumulative error of no more than ±1 second in a completely disconnected network scenario, which has better stability than a single RTC scheme.

[0107] In some embodiments, on the basis of Figure 2 and with reference to Figure 4 as shown, after performing the above - mentioned step S24 (when it is monitored that the frequency deviation of the first clock source is not within the preset deviation range, controlling the second clock source to update the current time data by using the clock signal output by the phase - locked loop), the following steps can also be performed:

[0108] S25. Enable the external network time - protocol server function of the processor.

[0109] Among them, the external network time - protocol server function is used to provide time - synchronization services for the target server cluster.

[0110] Implement the NTP server function at the BMC firmware layer, that is, store the software program for implementing the NTP server function in the BMC firmware layer, and start the software program when the external NTP server is unavailable to implement the NTP server function of the processor.

[0111] After starting the NTP server function of the processor, use the processor, i.e., BMC, as an NTP server to synchronize time data to the target nodes.

[0112] The target nodes include but are not limited to other servers in the target server cluster, other internal components in the target server, and other internal components such as a central processing unit, a graphics processing unit, a switch, a storage node, etc.

[0113] Optionally, the above - mentioned step S25 (enable the external network time - protocol server function of the processor) can be implemented in the following manner:

[0114] (1)Activate the external Network Time Protocol (NTP) service process built into the processor through a preset command.

[0115] Among them, the NTP service process is implemented by the software of the Network Time Protocol (NTP) and runs in the firmware of the processor. It is used to receive or send time synchronization requests and maintain the synchronization between the management controller clock and the standard time. The setting command refers to the configuration instruction input through a specific interface (such as serial port, SSH or API) and is used to activate, modify or disable the function modules of the processor.

[0116] Specifically, activate the built-in NTP service process through the systemctl command.

[0117] (2)Enable the access permission of the preset network port in the processor.

[0118] Among them, the preset port refers to the network port listened by the NTP server (BMC), usually the UDP port 123. It is necessary to control external access through the firewall or permission policy to prevent unauthorized management controllers from accessing. The access permission is the definition of the open rule for the port, including the allowed IP address range, protocol type (such as only UDP) and operation permission (such as read-only or read-write).

[0119] Specifically, lift the blockade of the UDP port 123 by the firewall or system policy to allow the external management controller to communicate with the processor through this port.

[0120] (3)Configure the access control list of the processor and enable the Network Time Protocol.

[0121] Among them, the access control list is used to manage the time synchronization access permission of at least one external server in the target server cluster to the target server.

[0122] The Network Time Protocol is a standard protocol for synchronizing the time of each management controller in the computer network and realizes high-precision time synchronization through the stratum structure and clock source selection algorithm.

[0123] Specifically, as the internal time distribution node in the target server cluster, the BMC needs to configure the access control list to limit that only the server nodes within the specified IP address range in the same network segment are allowed to initiate time synchronization requests. Further, based on the rule set network filtering mechanism, restrict which servers can send time synchronization requests to the processor through the whitelist / blacklist to improve security. Only allow the server nodes within the specified IP address range in the same network segment to initiate time synchronization requests to the processor to prevent illegal access.

[0124] After completing the above configuration, officially start the NTP service process in the BMC, and start responding to legitimate requests and participating in the time synchronization network. The operating systems of other servers in the cluster need to modify the / etc / ntp.conf configuration file and use the IP address of this BMC as the primary time source. At this time, the BMC will act as a primary time server and broadcast accurate time signals to all registered nodes through the local area network, and the synchronization accuracy can be controlled at the millisecond level.

[0125] S26. Synchronize the time data output by the second clock source to the target server cluster.

[0126] Among them, the target server cluster includes the target server and at least one external server. That is, the target server cluster is a collaborative system composed of multiple servers, sharing resources and working together to improve computing power, reliability or load balancing. At least one external server is all member nodes in the cluster except the target server, and needs to maintain communication and data synchronization with the master node or management unit.

[0127] Through the cooperation of the BMC integrated TCXO module and the clock unit, combined with the hierarchical NTP service architecture, relying on the cross-layer cooperation of physical layer clock distribution and protocol layer time synchronization in the BMC embedded system at limited cost, full-stack high-precision time synchronization and autonomous timekeeping capabilities within the server cluster are achieved.

[0128] Furthermore, at least one external server in the target server cluster is connected to the management controller of the target server through the local area network. The above step S26 (synchronizing the time data output by the second clock source to the target server cluster) can be implemented in the following manner:

[0129] Synchronize the time data output by the second clock source to the target server cluster through the local area network.

[0130] Among them, the local area network refers to a private network within a local range, connecting all member nodes in the cluster, providing a communication channel with low latency and high bandwidth for internal data exchange.

[0131] Specifically, all servers (including BMC) in the target server cluster are interconnected through the local area network to form a unified communication environment to ensure direct communication between management controllers. The BMC serves as the management core of the cluster, sharing the same network with the servers, facilitating centralized monitoring and control. The clock unit serves as the time reference of the cluster, providing high-precision time data. The BMC broadcasts or unicasts the time data in the clock unit to other servers in the cluster through the local area network, possibly using NTP (Network Time Protocol) or a private protocol. After all servers receive the time data, they adjust their local clocks to ensure the time consistency of the entire cluster.

[0132] In the embodiments of the present disclosure, the BMC is used as an NTP server to provide time synchronization services to other servers within the local area network, solving the problem that it is difficult to accurately synchronize the time of the server cluster in a network isolation environment.

[0133] In some embodiments, when the number of servers in the target server cluster is greater than a first preset value, the external network time protocol logging function of the processor is enabled; various events during the time data synchronization process are recorded.

[0134] Among them, the number of servers refers to the total number of physical or virtual server nodes currently running in the target server cluster, which is the core indicator for measuring the scale of the cluster.

[0135] The first preset value is a preset threshold parameter (such as 50 units) used to determine whether the cluster scale meets the condition for enabling a specific function (such as NTP logging).

[0136] The NTP logging function refers to the log generation and storage module of the Network Time Protocol (NTP), which records event details such as time synchronization requests, responses, and deviation adjustments (such as timestamps, source IPs, synchronization results).

[0137] The process of time data synchronization is the process by which servers within the cluster calibrate their clocks with the time source of the processor through the NTP protocol, including steps such as request sending, response receiving, and local clock correction.

[0138] Various events refer to key behaviors or state changes during the synchronization process, such as synchronization success / failure, clock offset exceeding the limit, network latency anomaly, master-slave switch, etc.

[0139] Specifically, in a large-scale cluster environment, enabling the NTP service logging function of the BMC to track and alarm time synchronization exception events is a key measure to ensure the high availability and stability of cluster time synchronization. When the number of servers exceeds the first preset value, it is determined that the time synchronization complexity and failure risk of the large-scale cluster increase significantly, and enhanced monitoring needs to be enabled. The NTP log module of the processor switches from the disabled or low-priority state to the active recording mode and starts capturing synchronization events.

[0140] The recorded content covers the entire process of time synchronization, including but not limited to: the frequency and time points of the server initiating synchronization requests. The processor response delay and clock deviation compensation value. The reasons for synchronization failure (such as network packet loss, clock source unreachable).

[0141] Locate the root cause of synchronization anomalies (such as clock drift of specific servers, network congestion) through log backtracking, and optimize the synchronization strategy or expand the cluster management resources.

[0142] Further, in some embodiments, obtain the number of pulses per second of the first clock source and the second clock source's second interrupt signal;

[0143] When the difference between the number of pulses per second of the first clock source and the second clock source's second interrupt signal is greater than a second preset value, send a switching instruction to any server in the target server cluster other than the target server.

[0144] Wherein, the switching instruction is used to indicate that the object for which time synchronization operation is to be performed is switched from the target server to any server in the target server cluster other than the target server.

[0145] Specifically, while synchronizing the time data of the clock unit to other servers in the cluster through the local area network, it further includes: obtaining the number of pulses per second of the temperature-compensated crystal oscillator and the second interrupt signal of the clock unit; when the number of pulses per second and the second interrupt signal are greater than a second preset value, send a switching instruction to any other server in the cluster.

[0146] Among them, the temperature-compensated crystal oscillator is a clock source that stabilizes the output frequency through a temperature compensation circuit. Its accuracy is less affected by the ambient temperature and is usually used in systems that require high-precision timing. The number of pulses per second is a quantization index of the frequency of the periodic electrical signal output by the temperature-compensated crystal oscillator, with the unit of Hz (Hertz). For example, 32.768 kHz means generating 32768 pulses per second and is the basis of the system timing.

[0147] The second interrupt signal of the clock unit refers to a hardware interrupt signal generated by the clock unit once per second, which is used to trigger the system to update the time or execute periodic tasks and has a strict time reference characteristic. Among them, the TCXO provides the number of pulses per second to reflect the clock frequency stability, and the RTC provides the second interrupt signal to reflect the time reference reliability.

[0148] The second preset value is a preset threshold parameter used to determine that the absolute value of the time difference between the PPS pulse of the TCXO and the rising edge of the RTC second interrupt signal exceeds the second preset value, and it is determined that the clock source is abnormal. Optionally, the second preset value is 1 millisecond.

[0149] Any other server in the cluster refers to other nodes in the same cluster except the current server, which needs to have redundancy capabilities to receive instructions and take over tasks to ensure the high availability of the system.

[0150] The switching instruction refers to a control command sent through the cluster internal communication protocol (such as TCP / IP or custom message), indicating that the target server starts a specific operation (such as indicating the object for switching the time synchronization operation).

[0151] Record the rising edge timestamps of the PPS pulse and the second interrupt signal through a dedicated internal timer or an external clock source, and calculate the difference between the two. The driver periodically reads the status registers of the two signals and judges the deviation based on the timestamp difference. When the deviation is detected to exceed 1 ms continuously for multiple times, or a single overlimit triggers an alarm. The processor turns off the clock source output of the current BMC and enables other servers in the cluster as NTP servers. After the switch, broadcast a clock source change notice to other nodes in the cluster and force the start of the time synchronization protocol to eliminate the residual deviation.

[0152] After detecting an anomaly, the current server sends a switch instruction to any available node in the cluster, preferentially selecting a server with a lower load or a higher priority. The switch instruction includes the synchronization request type, the time source identifier (such as the main RTC address), and the synchronization protocol parameters. The server receiving the instruction starts the time synchronization process, which may include steps such as pausing the current task, obtaining the latest time data from the specified time source, adjusting the local clock, and resuming the service. The synchronization process depends on the low-latency communication of the cluster network and the credibility of the time source. If the synchronization fails, it may trigger a retry or an alarm.

[0153] To ensure service reliability, a primary and standby NTP service architecture can be built with dual BMC nodes to achieve automatic failure switching. The BMC simultaneously monitors the 10 MHz high-frequency signal of the temperature-compensated crystal oscillator and the second-level interrupt signal of the clock unit. Through the PPS alignment mechanism, the deviation detection sensitivity between clock sources is increased to 1 ms. Compared with the single clock source scheme, the time jump alarm response speed is higher.

[0154] In some embodiments, the target server includes at least one internal component; the first clock source is connected to the at least one internal component through an integrated circuit bus; on Figure 2 this basis, with reference to Figure 5 shown, after performing the above step S25, the following step S27 can also be performed:

[0155] S27. Synchronize the time data output by the second clock source to the at least one internal component through the integrated circuit bus.

[0156] Specifically, the target node further includes internal components in the target server. The BMC broadcasts or unicasts the time data in the clock unit to the internal components in the target server through the local area network, and may use the NTP (Network Time Protocol) or a private protocol. After all internal components receive the time data, they adjust their local clocks to ensure the time consistency of the entire cluster. Among them, the internal components include a central processing unit, a graphics processing unit, a switch, a storage node, etc.

[0157] Through the temperature-compensated crystal oscillator and the dynamic switching mechanism of the RTC master-slave clock, it is ensured that even when the external NTP service is unavailable, the BMC can still be used as the NTP server to provide accurate time information for the server cluster and components. The dual-redundancy timekeeping mechanism formed by the real-time clock and the temperature-compensated crystal oscillator ensures the full-stack clock consistency between the BMC and each component, realizing high-precision time transfer.

[0158] Taking the BMC as the NTP server to send time synchronization information between the server cluster and each component, other server components with network service functions can also consider implementing this function. At the same time, in the scenario where satellite navigation signals are available, the temperature-compensated crystal oscillator can integrate a GPS / Beidou receiving module and be assisted and calibrated through the PPS signal to further improve the timekeeping accuracy.

[0159] In the embodiment of the present application, a hierarchical time synchronization architecture is provided. The BMC serves as the system-level time source, and a high-precision temperature-compensated crystal oscillator is carried as the core clock reference to construct a hierarchical time synchronization architecture. That is, when communicating with the internal components in the target server through the local area network, the temperature-compensated crystal oscillator is connected to the internal components in the target server through the I 2 C bus; the target server is the server to which the baseboard management controller belongs, and the temperature-compensated crystal oscillator synchronizes the clock signal to the internal components in the target server through the I 2 C bus.

[0160] Optionally, when the at least one internal component is a central processing unit, the above step S27 (synchronizing the time data output by the second clock source to the at least one internal component through the integrated circuit bus) can be implemented in the following manner:

[0161] Synchronize the time data output by the second clock source to the at least one central processing unit through the integrated circuit bus, so that the digital phase-locked loop in the at least one central processing unit calibrates the internal clock counter based on the time data output by the second clock source.

[0162] Among them, the central processing unit refers to the core computing unit of the server, which is responsible for executing instructions, processing data, and coordinating other components, and its operation depends on accurate clock signals.

[0163] In the internal components of the target server, the CPU is the core computing unit and the TCXO is the high-precision clock source, and the two are connected through the I 2 C bus. The TCXO transmits the clock signal to the CPU through the I 2 C bus, supporting two-way communication (such as configuring TCXO parameters or reading status).

[0164] The TCXO generates a clock signal and passes it through the I2 The clock signal is sent to the CPU via the I²C bus. The DPLL module inside the CPU receives the clock signal, compares it with the local oscillator frequency, calculates the deviation, and adjusts the frequency and phase of the clock counter. The calibrated clock counter provides an accurate timing reference for the CPU, ensuring the accuracy of instruction execution, interrupt handling, and task scheduling.

[0165] Optionally, when the at least one internal component is a graphics processor, the above step S27 (synchronizing the time data output by the second clock source to the at least one internal component via the integrated circuit bus) can be implemented in the following manner:

[0166] Synchronize the time data output by the second clock source to the at least one graphics processor via the integrated circuit bus, so that the at least one graphics processor performs time alignment based on the time data output by the second clock source in a remote direct memory access network operation.

[0167] Among them, the graphics processor is a hardware accelerator for parallel computing or graphics processing in the target server, usually configured with multiple cards such as 4-way or 8-way GPUs, and supports large-scale data parallel tasks.

[0168] The GPU of the target server is a computing acceleration unit, and the TCXO is a high-precision clock source. The two are connected via the I²C bus. 2 The TCXO transmits the clock signal to multiple GPUs via the I²C bus, supporting two-way communication. 2 The TCXO generates a clock signal and broadcasts it to multiple GPUs via the I²C bus. The signal frequency and phase need to meet the input requirements of the GPUs (such as high-frequency clocks for computing task scheduling). Multiple GPUs adjust their local timers based on the received clock signal to ensure that data transmission and task execution in the RDMA network are synchronized, avoiding calculation errors or data inconsistencies caused by clock deviations.

[0169] The TCXO generates a clock signal and broadcasts it to multiple GPUs via the I²C bus. 2 The signal frequency and phase need to meet the input requirements of the GPUs (such as high-frequency clocks for computing task scheduling). Multiple GPUs adjust their local timers based on the received clock signal to ensure that data transmission and task execution in the RDMA network are synchronized, avoiding calculation errors or data inconsistencies caused by clock deviations.

[0170] Through the technical solution of the embodiments of the present application, the time alignment of multiple GPUs in the RDMA network is ensured, improving the parallel computing efficiency and data transmission reliability.

[0171] In the embodiments of the present application, clock alignment for heterogeneous hardware such as CPUs and GPUs is supported, and the clock alignment function adaptation rate reaches 99%, significantly reducing the development workload of cross-platform time synchronization.

[0172] Optionally, when the at least one internal component is a switch or a storage node, the above step S27 (synchronizing the time data output by the second clock source to the at least one internal component via the integrated circuit bus) can be implemented in the following manner:

[0173] Synchronize the time data output by the second clock source to the at least one switch or storage node through the integrated circuit bus, so that the at least one switch or storage node performs time synchronization based on the time data output by the second clock source.

[0174] Among them, a switch is a network management controller for data exchange inside a server, responsible for forwarding data packets between different components to ensure efficient communication. A storage node is a hardware module for data storage in a server, which may be a hard disk drive, a solid-state drive, or a storage controller, supporting data reading, writing, and persistence.

[0175] I 2 The I²C bus is a serial communication bus protocol that supports a multi-master and slave architecture and is used to connect low-speed peripherals (such as switches and storage nodes) to the processor of the baseboard management controller to transmit control commands and data. A bridge is a hardware or software module used to connect different buses or protocols to achieve signal conversion and data transmission. The clock bus is a high-precision clock signal transmission channel provided by the BMC, used to distribute a unified clock signal to the internal components of the server to ensure timing consistency.

[0176] The switch or storage node of the target server is connected to the BMC through the I²C bus and a bridge. 2 The switch or storage node sends a request through the I²C bus, and the bridge converts the signal into the clock bus protocol, and the BMC responds and distributes the clock signal. 2 Specifically, the switch or storage node initiates a clock signal request to the BMC through the I²C bus, which may include the management controller identifier and clock parameters. The bridge converts the I²C bus signal into the clock bus protocol to ensure that the signal format and electrical characteristics are compatible. The BMC transmits the clock signal to the switch or storage node through the clock bus to ensure that its local clock is consistent with the server's global time reference.

[0177] Specifically, the switch or storage node initiates a clock signal request to the BMC through the I²C bus, which may include the management controller identifier and clock parameters. The bridge converts the I²C bus signal into the clock bus protocol to ensure that the signal format and electrical characteristics are compatible. The BMC transmits the clock signal to the switch or storage node through the clock bus to ensure that its local clock is consistent with the server's global time reference. 2 C bus signals into the clock bus protocol to ensure signal format and electrical characteristic compatibility. The BMC transmits the clock signal to the switch or storage node through the clock bus to ensure that its local clock is consistent with the server's global time reference. 2 C bus signals into the clock bus protocol to ensure signal format and electrical characteristic compatibility. The BMC transmits the clock signal to the switch or storage node through the clock bus to ensure that its local clock is consistent with the server's global time reference.

[0178] Furthermore, the timekeeping ability of the temperature-compensated crystal oscillator is used to ensure continuous high-precision timekeeping when the external authoritative clock source is interrupted. When it is detected that the frequency deviation of the temperature-compensated crystal oscillator exceeds the ±5ppm threshold, it automatically switches to the compensation clock of the clock unit, and generates an alternative clock signal through the PLL, and uses a dual-redundancy timekeeping mechanism to ensure the accuracy of the clock signal.

[0179] In the embodiment of the present application, physical layer - protocol layer dual protection is achieved. The temperature-compensated crystal oscillator passes through the I²C bus 2The C bus realizes hardware-level clock distribution, avoiding the time delay jitter of the software protocol stack; at the same time, the NTPv4 protocol supports encrypted time service, through the dual protection mechanism of C hardware-level distribution and NTPv4 encryption protocol, effectively preventing man-in-the-middle attacks. 2 The dual protection mechanism of C hardware-level distribution and NTPv4 encryption protocol effectively prevents man-in-the-middle attacks.

[0180] In the time synchronization method provided by the embodiments of the present disclosure, a processor, a first clock source, and a second clock source are deployed in the management controller. The time accuracy of the first clock source is higher than that of the second clock source. When it is detected that the external network time protocol server is in an unavailable state, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source, and continuously monitors the frequency deviation of the first clock source. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the internal phase-locked loop of the second clock source is switched to provide the clock signal, and the current time data is updated based on this clock signal. Through the master-slave clock dynamic switching mechanism of the first clock source and the second clock source, it is ensured that when the external network time protocol server is unavailable, the management controller can still be used as the external network time protocol server to provide accurate time information for the server.

[0181] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0182] The embodiments of the present application also provide a time synchronization device. The content of the virtual device claims omitted in the specification should be described in detail and corresponds to the method claims one by one.

[0183] Figure 6 The structure diagram of a time synchronization device 600 provided by the present disclosure is as Figure 6 shown. The device of this embodiment includes: a monitoring module 610, an output module 620, a control module 630, and an update module 640, where,

[0184] The monitoring module 610 is configured to enter the timekeeping mode when it is detected that the external network time protocol server is in an unavailable state;

[0185] The output module 620 is configured to control the clock signal output by the first clock source to be transmitted to the second clock source in the timekeeping mode;

[0186] The control module 630 is configured to control the second clock source to update the current time data according to the clock signal output by the first clock source;

[0187] An update module 640, configured to control the second clock source to update the current time data by using the clock signal output by the phase-locked loop when it is detected that the frequency deviation of the first clock source is not within the preset deviation range.

[0188] As an optional implementation manner of an embodiment of the present disclosure, the first clock source is connected to the processor through an integrated circuit bus, and the second clock source is connected to the processor through an integrated circuit bus.

[0189] As an optional implementation manner of an embodiment of the present disclosure, the device further includes an initialization module, and the initialization module is specifically configured to:

[0190] After detecting that the target server is powered on, obtain a time stamp from the second clock source;

[0191] Transmit the time stamp to the first clock source, and control the first clock source to generate and output a clock signal with the time stamp as the initial time reference.

[0192] As an optional implementation manner of an embodiment of the present disclosure, the device further includes:

[0193] A first function enabling module, configured to enable the external network time protocol server function of the processor;

[0194] A first synchronization module, configured to synchronize the time data output by the second clock source to a target server cluster;

[0195] Wherein, the external network time protocol server function is used to provide a time synchronization service for the target server cluster; the target server cluster includes the target server and at least one external server.

[0196] As an optional implementation manner of an embodiment of the present disclosure, the first function enabling module is specifically configured to:

[0197] Activate the external network time protocol service process built in the processor through a preset command;

[0198] Enable the access permission of a preset network port in the processor;

[0199] Configure the access control list of the processor, and enable the network time protocol; the access control list is used to manage the time synchronization access permission of at least one external server in the target server cluster to the target server.

[0200] As an optional implementation manner of an embodiment of the present disclosure, at least one external server in the target server cluster is connected to the management controller of the target server through a local area network; the first synchronization module is specifically configured to:

[0201] Synchronize the time data output by the second clock source to the target server cluster through the local area network.

[0202] As an optional implementation manner of the embodiment of the present disclosure, the apparatus further includes:

[0203] A second function enabling module, configured to enable the external network time protocol logging function of the processor when the number of servers in the target server cluster is greater than a first preset value;

[0204] A recording module, configured to record various events during the time data synchronization process.

[0205] As an optional implementation manner of the embodiment of the present disclosure, the apparatus further includes a switching module, configured to:

[0206] Obtain the pulses per second of the first clock source and the second interrupt signal of the second clock source;

[0207] When the difference between the pulses per second of the first clock source and the second interrupt signal of the second clock source is greater than a second preset value, send a switching instruction to any server in the target server cluster except the target server; the switching instruction is used to indicate that the object for which the time synchronization operation is to be performed is switched from the target server to any server in the target server cluster except the target server.

[0208] As an optional implementation manner of the embodiment of the present disclosure, the target server includes at least one internal component; the first clock source is connected to the at least one internal component through an integrated circuit bus; the apparatus further includes a second synchronization module, configured to:

[0209] Synchronize the time data output by the second clock source to the at least one internal component through the integrated circuit bus.

[0210] As an optional implementation manner of the embodiment of the present disclosure, when the at least one internal component is a central processing unit, the second synchronization module is specifically configured to:

[0211] Synchronize the time data output by the second clock source to the at least one central processing unit through the integrated circuit bus, so that the digital phase-locked loop in the at least one central processing unit calibrates the internal clock counter based on the time data output by the second clock source.

[0212] As an optional implementation manner of the embodiment of the present disclosure, when the at least one internal component is a graphics processing unit, the second synchronization module is specifically configured to:

[0213] Synchronize the time data output by the second clock source to the at least one graphics processor through the integrated circuit bus, so that the at least one graphics processor performs time alignment based on the time data output by the second clock source in a remote direct memory access network operation.

[0214] For the description of the features in the corresponding embodiment of the time synchronization device 600, reference can be made to the relevant description of the corresponding embodiment of the time synchronization method, which will not be elaborated here one by one.

[0215] In the time synchronization device provided by the embodiments of the present disclosure, a processor, a first clock source, and a second clock source are deployed in the management controller. The time accuracy of the first clock source is higher than that of the second clock source. When it is detected that the external network time protocol server is in an unavailable state, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source, and continuously monitors the frequency deviation of the first clock source. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the internal phase-locked loop of the second clock source is used to provide the clock signal, and the current time data is updated based on this clock signal. Through the master-slave clock dynamic switching mechanism of the first clock source and the second clock source, it is ensured that even when the external network time protocol server is unavailable, the management controller can still be used as the external network time protocol server to provide accurate time information for the server.

[0216] The embodiments of the present application further provide a management controller, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above-described embodiments of the time synchronization method.

[0217] The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the time synchronization method when running.

[0218] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk, or optical disc, etc., various media that can store computer programs.

[0219] The embodiments of the present application further provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the time synchronization method.

[0220] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-described time synchronization method embodiments are implemented.

[0221] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0222] The above has introduced in detail a time synchronization method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A time synchronization method, characterized in that: The method is applied to a management controller included in a target server, the management controller including: a processor, a first clock source and a second clock source, the time accuracy of the first clock source is higher than that of the second clock source, and the method is executed by the processor, and the method includes: When the external network time protocol server is detected to be unavailable, it enters the timekeeping mode; In the punctual mode, controlling the clock signal output by the first clock source to be transmitted to the second clock source; Controlling the second clock source to update current time data according to the clock signal output by the first clock source; When it is monitored that the frequency deviation of the first clock source is not within a preset deviation range, the second clock source is controlled to update the current time data using a clock signal output by a phase-locked loop.

2. The time synchronization method according to claim 1, characterized in that: The first clock source is connected to the processor via an integrated circuit bus, and the second clock source is connected to the processor via an integrated circuit bus.

3. The time synchronization method according to claim 1, characterized in that: When it is detected that the external network time protocol server is in an unavailable state, before entering the timekeeping mode, the method further includes: After detecting that the target server is powered on, obtaining a timestamp from the second clock source; The timestamp is transmitted to the first clock source, and the first clock source is controlled to generate and output a clock signal using the timestamp as an initial time reference.

4. The time synchronization method according to claim 1, characterized in that: After controlling the second clock source to update the current time data using the clock signal output by the phase-locked loop, the method further includes: enabling an external network time protocol server function of the processor; Synchronize the time data output by the second clock source to the target server cluster; The external network time protocol server function is used to provide time synchronization service for the target server cluster; the target server cluster includes the target server and at least one external server.

5. The time synchronization method according to claim 4, characterized in that: The enabling of the external network time protocol server function of the processor comprises: activating an external network time protocol service process built into the processor through a preset command; Enabling access rights to a preset network port in the processor; An access control list of the processor is configured, and a network time protocol is enabled; the access control list is used to manage the time synchronization access rights of at least one external server in the target server cluster to the target server.

6. The time synchronization method according to claim 4, characterized in that: At least one external server in the target server cluster is connected to the management controller of the target server via a local area network; The step of synchronizing the time data output by the second clock source to the target server cluster includes: The time data output by the second clock source is synchronized to the target server cluster via the local area network.

7. The time synchronization method according to claim 6, characterized in that: The method further comprises: When the number of servers in the target server cluster is greater than a first preset value, enabling an external network time protocol logging function of the processor; Record various events during the time data synchronization process.

8. The time synchronization method according to claim 7, characterized in that: The method further comprises: Obtaining a rising edge timestamp of a pulse-per-second signal of the first clock source and a rising edge timestamp of a second interrupt signal of the second clock source; When the difference between the rising edge timestamp of the second pulse signal of the first clock source and the rising edge timestamp of the second interrupt signal of the second clock source is greater than a second preset value, a switching instruction is sent to any server in the target server cluster except the target server; the switching instruction is used to instruct the object of the time synchronization operation to be switched from the target server to any server in the target server cluster except the target server.

9. The time synchronization method according to claim 4, characterized in that: The target server includes at least one internal component; the first clock source is connected to the at least one internal component via an integrated circuit bus; After enabling the external network time protocol server function of the processor, the method further includes: The time data output by the second clock source is synchronized to the at least one internal component through the integrated circuit bus.

10. The time synchronization method according to claim 9, characterized in that: When the at least one internal component is a central processing unit, synchronizing the time data output by the second clock source to the at least one internal component through the integrated circuit bus includes: The time data output by the second clock source is synchronized to the at least one central processor via the integrated circuit bus, so that the digital phase-locked loop in the at least one central processor calibrates the internal clock counter based on the time data output by the second clock source.

11. The time synchronization method according to claim 9, characterized in that: When the at least one internal component is a graphics processor, synchronizing the time data output by the second clock source to the at least one internal component through the integrated circuit bus includes: The time data output by the second clock source is synchronized to the at least one graphics processor through the integrated circuit bus, so that the at least one graphics processor performs time alignment based on the time data output by the second clock source in remote direct memory access network operations.

12. A time synchronization device, characterized in that: The management controller included in the target server is applied, the management controller includes: a processor, a first clock source and a second clock source, the time accuracy of the first clock source is higher than that of the second clock source, the device is deployed in the processor, and the device includes: A monitoring module, used for entering a timekeeping mode when detecting that an external network time protocol server is unavailable; An output module, configured to control the clock signal output by the first clock source to be transmitted to the second clock source in the punctual mode; A control module, used for controlling the second clock source to update current time data according to the clock signal output by the first clock source; The updating module is used to control the second clock source to update the current time data using the clock signal output by the phase-locked loop when it is detected that the frequency deviation of the first clock source is not within a preset deviation range.

13. A management controller, characterized in that: The management controller comprises: a processor, a first clock source and a second clock source, wherein the time accuracy of the first clock source is higher than that of the second clock source; Memory for storing computer programs; A processor, configured to implement the steps of the time synchronization method as claimed in any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the time synchronization method according to any one of claims 1 to 11.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the time synchronization method according to any one of claims 1 to 11 are implemented.

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