Load detection device for audio amplifier system

Abstract

The invention provides a load detection device for an audio amplifier system, comprising: a signal output circuit outputting a forced current and generating a bias signal, a first output signal, a second output signal and a feedback signal dependent on the forced current; a comparison circuit comparing the reference signal output and the first output signal with the second output signal to generate a precise comparison output indicative of a load condition; the induction circuit generates an induction signal according to the feedback signal; the detection circuit is used for generating rough detection output for indicating the load state according to the sensing signal, the first output signal and the second output signal; the logic circuit obtains a load state according to the accurate comparison output and the rough detection output; and a control circuit, an enable signal output circuit, a comparison circuit, an induction circuit and a logic circuit. Therefore, the load detection device can solve the problem of large circuit area.

Description

Technical Field

[0001] The present invention relates to a detection device, in particular to a load detection device for an audio amplifier system. Background Art

[0002] An existing audio amplifier system includes an amplifier, a speaker, and a load detection device. The amplifier is configured to generate an amplified audio signal and output it to the speaker, so that the speaker emits sound according to the amplified audio signal. The load detection device is used to detect whether the speaker is damaged, for example, short-circuited or open-circuited, before the audio system enters the operation mode for use, so as to avoid failure of the speaker load. Summary of the invention

[0003] However, the conventional load detection device includes an analog-to-digital converter and / or a digital-to-analog converter, which results in the conventional load detection device having a larger circuit area.

[0004] Therefore, an object of the present invention is to provide a load detection device with a smaller circuit area to solve the problem that the existing load detection device has a larger circuit area and is difficult to form an integrated circuit with an amplifier.

[0005] Therefore, the present invention is used for a load detection device of an audio amplifier system, the audio amplifier system includes a first load terminal and a second load terminal coupled to a speaker, and the load detection device includes a signal output circuit, a reference voltage generating circuit, a comparison circuit, a sensing circuit, a detection circuit, a logic circuit, and a control circuit.

[0006] The signal output circuit is coupled to the first load terminal and the second load terminal, and is used to generate and output a forced current to the first load terminal, and to generate a bias signal, a first output signal related to the level of the first load terminal, a second output signal related to the level of the second load terminal, and a feedback signal depending on the forced current.

[0007] The reference voltage generating circuit is coupled to the signal output circuit to receive the bias signal and generates a reference signal output according to the bias signal.

[0008] The comparison circuit is coupled to the signal output circuit to receive the first output signal and the second output signal, and is coupled to the reference voltage generation circuit to receive the reference signal output, and compares the reference signal output and the first output signal with the second output signal to generate an accurate comparison output for indicating the speaker load status.

[0009] The sensing circuit is coupled to the signal output circuit to receive the feedback signal and generate a sensing signal according to the feedback signal.

[0010] The detection circuit is coupled to the sensing circuit to receive the sensing signal and coupled to the signal output circuit to receive the first output signal and the second output signal, and generates a rough detection output indicating the speaker load state according to the sensing signal and the first output signal and the second output signal.

[0011] The logic circuit is coupled to the comparison circuit and the detection circuit to receive the precise comparison output and the rough detection output respectively, and obtains the speaker load state according to the precise comparison output and the rough detection output to generate a detection result.

[0012] The control circuit is used for generating an enable signal and outputting the enable signal to the signal output circuit, the comparison circuit, the sensing circuit and the logic circuit to enable the signal output circuit, the comparison circuit, the sensing circuit and the logic circuit.

[0013] In some embodiments, the sensing circuit includes: a first resistor having a first end coupled to a signal output circuit to receive a feedback signal, and a second end; a first transistor having a first end coupled to the second end of the first resistor, a second end coupled to a first reference voltage end, and a control end coupled to its own first end and providing a sensing signal; and a current limiting unit for limiting the current flowing into the first transistor. The current limiting unit includes: a buffer for receiving an enable signal from a control circuit and generating a common-phase signal according to the enable signal; a second resistor having a first end coupled to the buffer for receiving the common-phase signal, and a second end, the level of the second end of the second resistor being used to limit the current flowing into the first transistor; a third resistor having a first end coupled to the second end of the second resistor, and a second end; and a switch coupled between the second end of the third resistor and the first reference voltage end, and controlled by a switching signal to be turned on or off.

[0014] In some embodiments, the signal output circuit includes: a current generator, which is used to generate and output a forced current according to an input current, and to generate a bias signal; and a signal outputter, which is enabled by an enable signal from a control circuit, and is coupled to a first load terminal and a second load terminal, and is coupled to the current generator to receive the forced current and output it to the first load terminal, and the signal outputter generates and outputs a first output signal, a second output signal, and a feedback signal.

[0015] In some embodiments, the current generator includes: a second transistor having a first end, a second end for receiving an input current, and a control end coupled to its own second end; and a third transistor having a first end coupled to the first end of the second transistor, a second end for outputting a forced current, and a control end coupled to the control end of the second transistor.

[0016] In some embodiments, the signal outputter includes: a fourth transistor having a first end coupled to the current generator to receive a forced current, a second end coupled to the first load end, and a control end for receiving an enable signal; a fifth transistor having a first end coupled to the first load end, a second end providing a first output signal, and a control end; a sixth transistor having a first end coupled to the second load end, a second end providing a second output signal, and a control end; and a seventh transistor having a first end coupled to the second load end, a second end providing a feedback signal, and a control end.

[0017] In some embodiments, the reference signal output includes a first reference voltage, a second reference voltage, a third reference voltage and a fourth reference voltage, the speaker load state includes a short circuit to ground state, a short circuit to power state, a short circuit state and an open circuit state, the precise comparison output includes a first comparison signal, a second comparison signal, a third comparison signal and a fourth comparison signal, and the comparison circuit includes: a first comparison unit, comparing one of the first output signal and the second output signal with the first reference voltage to generate a first comparison signal, the first comparison signal is used to indicate whether the speaker load state is a short circuit to ground state; a second comparison unit, comparing one of the first output signal and the second output signal with the second reference voltage to generate a second comparison signal, the second comparison signal is used to indicate whether the speaker load state is a short circuit to power state; a third comparison unit, comparing the first output signal with the third reference voltage to generate a third comparison signal, the third comparison signal is used to indicate whether the speaker load state is an open circuit state; and a fourth comparison unit, comparing the first output signal with the fourth reference voltage to generate a fourth comparison signal, the fourth comparison signal is used to indicate whether the speaker load state is a short circuit state.

[0018] In some embodiments, the second comparison unit includes: an eighth transistor having a first end for receiving one of the first output signal and the second output signal, a second end, and a control end; a comparator having a non-inverting input end coupled to the second end of the eighth transistor to receive one of the first output signal and the second output signal, an inverting input end for receiving a second reference voltage, and an output end, the output end providing a comparison result obtained by comparing one of the first output signal and the second output signal with the second reference voltage; a level converter coupled to the output end of the comparator to receive the comparison result, and based on the comparison result, generates and outputs a conversion signal, the voltage swing of the comparison result is different from the voltage swing of the conversion signal; and a first SR latch coupled to the level converter to receive the conversion signal, and generates a second comparison signal based on the conversion signal.

[0019] In some embodiments, the speaker load state includes a short circuit to ground state, a short circuit to power state and an open circuit state, the rough detection output includes a first detection signal, a second detection signal and a third detection signal, and the detection circuit includes: a first detection unit, coupled to the sensing circuit to receive the sensing signal, and generate a first detection signal based on the sensing signal, the first detection signal is used to indicate whether the speaker load state is a short circuit to power state; a second detection unit, coupled to the sensing circuit to receive the sensing signal, and generate a second detection signal based on the sensing signal, the second detection signal is used to indicate whether the speaker load state is a short circuit to ground state; and a third detection unit, coupled to the signal output circuit to receive the first output signal and the second output signal, and coupled to the second detection unit to receive the second detection signal, and generate a third detection signal based on the second detection signal and the first output signal and the second output signal, the third detection signal is used to indicate whether the speaker load state is an open circuit state.

[0020] In some embodiments, the first detection unit includes: a ninth transistor having a first end, a second end coupled to the first reference voltage end, and a control end coupled to the sensing circuit to receive a sensing signal; a first current source coupled between the second reference voltage end and the first end of the ninth transistor to provide a first current; an inverter coupled to the first end of the ninth transistor and generating an inverted signal according to the level of the first end of the ninth transistor; and a second SR latch coupled to the inverter to receive the inverted signal and generate a first detection signal according to the inverted signal.

[0021] In some embodiments, the second detection unit includes: a tenth transistor having a first end providing a second detection signal, a second end coupled to the first reference voltage end, and a control end coupled to the sensing circuit to receive the sensing signal; and a second current source coupled between the second reference voltage end and the first end of the tenth transistor to provide a second current.

[0022] In some embodiments, the third detection unit includes: an eleventh transistor having a first end, a second end coupled to the signal output circuit to receive the second output signal, and a control end coupled to the signal output circuit to receive the first output signal; a third current source coupled between the second reference voltage end and the first end of the eleventh transistor to provide a third current; a twelfth transistor having a first end coupled to the second reference voltage end, a second end providing the third detection signal, and a control end coupled to the first end of the eleventh transistor; a fourth current source coupled between the second end of the twelfth transistor and the third reference voltage end; and a thirteenth transistor having a first end coupled to the second detection unit to receive the second detection signal, a second end coupled to the third reference voltage end, and a control end coupled to the second end of the twelfth transistor.

[0023] Thus, the present invention utilizes a signal output circuit to generate a forced current, and a comparison circuit compares a reference signal output and a first output signal with a second output signal to generate a precise comparison output, and a sensing circuit generates a sensing signal for detection by a detection circuit to generate a rough detection output. In this way, the logic circuit can obtain the speaker load status according to the precise comparison output and the rough detection output. Therefore, the present invention does not need to be configured with an analog-to-digital converter and / or a digital-to-analog converter as in the existing load detection device, and thus the load detection device of the present invention has a smaller circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit block diagram illustrating an embodiment of a load detection device for an audio amplifier system according to the present invention.

[0025] Figure 2 is a circuit block diagram illustrating a signal output circuit, a reference voltage generating circuit, and a comparison circuit of the embodiment.

[0026] Figure 3 is a circuit block diagram illustrating the sensing circuit and the detection circuit of the embodiment.

[0027] Figure 4 1 is a waveform diagram illustrating an enable signal, first to fourth comparison signals, and first to third detection signals of the embodiment.

[0028] Reference numerals

[0029] 1 Audio Amplifier System

[0030] 11 Audio Amplifier

[0031] 12 Speakers

[0032] 2 Load detection device

[0033] 3 Signal output circuit

[0034] 31 Current Generator

[0035] 311 Second Transistor

[0036] 312 Third transistor

[0037] 32 signal output

[0038] 321-324 fourth transistor to seventh transistor

[0039] 4 Reference voltage generation circuit

[0040] 5 Comparison circuit

[0041] 51 First comparison unit

[0042] 511 Comparator

[0043] 52 Second comparison unit

[0044] 521 Eighth Transistor

[0045] 522 Comparator

[0046] 523 Level Converter

[0047] 524 First SR Latch

[0048] 53 Third comparison unit

[0049] 531 Comparator

[0050] 54 Fourth comparison unit

[0051] 541 Comparator

[0052] 542 Error Corrector

[0053] 6 Induction circuit

[0054] 61 First resistor

[0055] 62 First Transistor

[0056] 63 Current limiting unit

[0057] 631 Buffer

[0058] 632 Second resistor

[0059] 633 Third resistor

[0060] 634 Switch

[0061] 7 Detection circuit

[0062] 71 First detection unit

[0063] 711 Ninth Transistor

[0064] 712 first current source

[0065] 713 Inverter

[0066] 714 Second SR Latch

[0067] 72 Second detection unit

[0068] 721 The Tenth Transistor

[0069] 722 Second current source

[0070] 73 Third Detection Unit

[0071] 731 The Eleventh Transistor

[0072] 732 Third current source

[0073] 733 12th Transistor

[0074] 734 Fourth current source

[0075] 735 Thirteenth Transistor

[0076] 8 Logic Circuit

[0077] 9 Control circuit

[0078] Bs bias signal

[0079] C1 control signal

[0080] Co Precision comparison output

[0081] Cr comparison results

[0082] Co1~Co4 The first comparison signal to the fourth comparison signal

[0083] CCo coarse detection output

[0084] CCo1~CCo3 The first detection signal to the third detection signal

[0085] En Enable signal

[0086] Fs feedback signal

[0087] Ii Input current

[0088] Io forced current

[0089] Ls conversion signal

[0090] N1 First load terminal

[0091] N2 Second load terminal

[0092] NV1~NV3 The first reference voltage terminal to the third reference voltage terminal

[0093] Os1 First output signal

[0094] Os2 Second output signal

[0095] R Resistance

[0096] Ro reference signal output

[0097] Ro1~Ro4 The first reference voltage to the fourth reference voltage

[0098] So Sensing Signal

[0099] Tr test results DETAILED DESCRIPTION

[0100] The present invention will be described in detail by the following embodiments and drawings to help those skilled in the art understand the purpose, features and effects of the present invention. It should be noted that certain terms are used throughout the specification to refer to specific components. As recognized by those skilled in the art, manufacturers can refer to components by different names. In the following description and patent scope, the terms "including" and "comprising" are used in an open manner and should not be interpreted as closed terms such as "consisting of..." In addition, the term "coupled" is intended to represent an indirect or direct electrical connection. Therefore, if one device is coupled to another device, this connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. In addition, in the content described in the present invention, terms such as "first", "second" and "third" are used to distinguish between components, rather than to limit the components themselves or to represent a specific order of components.

[0101] See also Figure 1 , an embodiment of a load detection device 2 for an audio amplifier system 1 of the present invention is described. The audio amplifier system 1 includes an audio amplifier 11, a speaker 12, a first load terminal N1 and a second load terminal N2. The speaker 12 is coupled between the first load terminal N1 and the second load terminal N2. When the audio amplifier system 1 enters the operation mode, the audio amplifier 11 is configured to generate an amplified audio signal and output it to the speaker 12, so that the speaker 12 emits a sound according to the amplified audio signal. Before the audio amplifier system 1 enters the operation mode (i.e., during the load detection period), the load detection device 2 detects whether a fault occurs in the speaker 12, for example, the load state of the speaker 12 is a short circuit to ground state, a short circuit to power state, a short circuit state or an open circuit state. The load detection device 2 includes a signal output circuit 3, a reference voltage generation circuit 4, a comparison circuit 5, a sensing circuit 6, a detection circuit 7, a logic circuit 8, and a control circuit 9.

[0102] The control circuit 9 is used to generate an enable signal En and output it to the signal output circuit 3, the comparison circuit 5, the sensing circuit 6 and the logic circuit 8, so as to enable the signal output circuit 3, the comparison circuit 5, the sensing circuit 6 and the logic circuit 8. The control circuit 9 is a controller, which may be a finished product known to those skilled in the art.

[0103] The signal output circuit 3 is coupled to the first load terminal N1 and the second load terminal N2, and is used to generate and output the forced current Io to the first load terminal N1, and to generate a bias signal Bs, a first output signal Os1 related to the level of the first load terminal N1, a second output signal Os2 related to the level of the second load terminal N2, and a feedback signal Fs depending on the forced current Io.

[0104] The reference voltage generating circuit 4 is coupled to the signal output circuit 3 to receive the bias signal Bs, and generates a reference signal output Ro according to the bias signal Bs.

[0105] The comparison circuit 5 is coupled to the signal output circuit 3 to receive the first output signal Os1 and the second output signal Os2, and is coupled to the reference voltage generating circuit 4 to receive the reference signal output Ro, and compares the reference signal output Ro with the first output signal Os1 and the second output signal Os2 to generate an accurate comparison output Co for indicating the load status of the speaker 12.

[0106] The sensing circuit 6 is coupled to the signal output circuit 3 to receive the feedback signal Fs, and generates a sensing signal So according to the feedback signal Fs.

[0107] The detection circuit 7 is coupled to the sensing circuit 6 to receive the sensing signal So, and is coupled to the signal output circuit 3 to receive the first output signal Os1 and the second output signal Os2, and generates a rough detection output CCo for indicating the load state of the speaker 12 according to the sensing signal So, the first output signal Os1 and the second output signal Os2.

[0108] The logic circuit 8 is coupled to the comparison circuit 5 and the detection circuit 7 to receive the precise comparison output Co and the rough detection output CCo respectively, and obtains the load state of the speaker 12 according to the precise comparison output Co and the rough detection output CCo to generate the detection result Tr. The logic circuit 8 is mainly composed of basic logic gates and input / output variables, which can be a finished product known to those skilled in the art.

[0109] Further reading Figure 2 , is a detailed circuit diagram of the signal output circuit 3, the reference voltage generating circuit 4 and the comparison circuit 5 according to an embodiment of the present invention.

[0110] The signal output circuit 3 includes a current generator 31 and a signal outputter 32 .

[0111] The current generator 31 is used to generate and output a forced current Io according to an input current Ii, and to generate a bias signal Bs. The current generator 31 includes a second transistor 311 and a third transistor 312 .

[0112] The second transistor 311 has a first end, a second end for receiving an input current Ii, and a control end coupled to the second end thereof. The third transistor 312 has a first end coupled to the first end of the second transistor 311, a second end for outputting a forced current Io, and a control end coupled to the control end of the second transistor 311. The potential between the first end and the control end of the third transistor 312 is used as a bias signal Bs. The second transistor 311 and the third transistor 312 are each a P-type metal oxide semi-conductor field effect transistor, wherein the source, the drain and the gate are respectively the first end, the second end and the control end of each of the second transistor 311 and the third transistor 312. The second transistor 311 and the third transistor 312 are combined into a current mirror. The input current Ii is, for example, 10 microamperes (uA), and the forced current Io is, for example, 1 milliampere (mA).

[0113] The signal outputter 32 is enabled by the enable signal En from the control circuit 9, and is coupled to the first load terminal N1 and the second load terminal N2, and is coupled to the second end of the third transistor 312 of the current generator 31 to receive the forced current Io and output it to the first load terminal N1. The signal outputter 32 generates and outputs the first output signal Os1 and the second output signal Os2, and the feedback signal Fs. The signal outputter 32 includes a fourth transistor 321, a fifth transistor 322, a sixth transistor 323, and a seventh transistor 324.

[0114] The fourth transistor 321 has a first end coupled to the second end of the third transistor 312 to receive the forced current Io, a second end coupled to the first load end N1, and a control end receiving the enable signal En. The fourth transistor 321 is controlled to be turned on or off by the enable signal En. The fifth transistor 322 has a first end coupled to the first load end N1, a second end providing the first output signal Os1, and a control end. The sixth transistor 323 has a first end coupled to the second load end N2, a second end providing the second output signal Os2, and a control end. The seventh transistor 324 has a first end coupled to the second load end N2, a second end providing the feedback signal Fs, and a control end receiving the control signal C1. The seventh transistor 324 is controlled to be turned on or off by the control signal C1. The fifth transistor 322 and the sixth transistor 323 are controlled to be turned on or off by the control circuit 9. The resistor R is a schematic diagram of the equivalent circuit of the speaker 42. Each of the fourth transistor 321 to the seventh transistor 324 is an N-type metal oxide semiconductor field effect transistor, wherein the drain, the source and the gate are the first end, the second end and the control end of each of the fourth transistor 321 to the seventh transistor 324 respectively.

[0115] The reference signal output Ro generated by the reference voltage generating circuit 4 includes a first reference voltage Ro1, a second reference voltage Ro2, a third reference voltage Ro3 and a fourth reference voltage Ro4. It should be noted that the configuration of the reference voltage generating circuit 4 is as follows: Figure 2 As shown, transistors 41, 42 and 43 are controlled by control circuit 9 to be turned on or off. How to generate the first reference voltage Ro1, the second reference voltage Ro2, the third reference voltage Ro3 and the fourth reference voltage Ro4 is well known to those skilled in the art and will not be elaborated here for the sake of brevity.

[0116] The precise comparison output Co generated by the comparison circuit 5 includes a first comparison signal Co1, a second comparison signal Co2, a third comparison signal Co3 and a fourth comparison signal Co4. The comparison circuit 5 includes a first comparison unit 51, a second comparison unit 52, a third comparison unit 53 and a fourth comparison unit 54.

[0117] The first comparison unit 51 compares one of the first output signal Os1 and the second output signal Os2 with the first reference voltage Ro1 to generate a first comparison signal Co1. The first comparison signal Co1 is used to indicate whether the load state of the speaker 12 is a short-circuit to ground state. The first comparison unit 51 includes a comparator 511, and the comparator 511 has a non-inverting input terminal coupled to the reference voltage generation circuit 4 to receive the first reference voltage Ro1, an inverting input terminal coupled to the signal output circuit 3 to receive one of the first output signal Os1 and the second output signal Os2, and an output terminal that outputs the first comparison signal Co1. For example, when the logic level of the first comparison signal Co1 is a high logic level "1", it indicates that the load state of the speaker 12 is a short-circuit to ground state.

[0118] The second comparison unit 52 compares one of the first output signal Os1 and the second output signal Os2 with the second reference voltage Ro2 to generate a second comparison signal Co2. The second comparison signal Co2 is used to indicate whether the load state of the speaker 12 is a short circuit to a power state. For example, when the logic level of the second comparison signal Co2 is a high logic level "1", it indicates that the load state of the speaker 12 is a short circuit to a power state. The second comparison unit 52 includes an eighth transistor 521, a comparator 522, a level shifter 523, and a first SR latch 524.

[0119] The eighth transistor 521 has a first terminal for receiving one of the first output signal Os1 and the second output signal Os2, a second terminal, and a control terminal that is turned on or off by the control circuit 9. The eighth transistor 521 is a P-type metal oxide semiconductor field effect transistor, wherein the source, the drain and the gate are the first terminal, the second terminal and the control terminal of the eighth transistor 521 respectively.

[0120] The comparator 522 has a non-inverting input terminal coupled to the second terminal of the eighth transistor 521 to receive one of the first output signal Os1 and the second output signal Os2, an inverting input terminal receiving the second reference voltage Ro2, and an output terminal. The output terminal of the comparator 522 provides a comparison result Cr, which is obtained by comparing one of the first output signal Os1 and the second output signal Os2 with the second reference voltage Ro2. The voltage values ​​received by the positive power supply terminal and the negative power supply terminal of the comparator 522 are 24V and 5V respectively.

[0121] The level converter 523 is coupled to the output terminal of the comparator 522 to receive the comparison result Cr, and generates and outputs a conversion signal Ls according to the comparison result Cr. The voltage swing of the comparison result Cr is different from the voltage swing of the conversion signal Ls. The level converter 523 is a circuit for converting a signal from one logic level or voltage domain to another logic level or voltage domain, and can be a finished product known to those skilled in the art.

[0122] The first SR latch 524 is coupled to the level converter 523 to receive the conversion signal Ls, and generates a second comparison signal Co2 according to the conversion signal Ls. The first SR latch 524 is composed of a plurality of logic gates, which may be products known to those skilled in the art.

[0123] The third comparison unit 53 compares the first output signal Os1 with the third reference voltage Ro3 (e.g., 95 mV) to generate a third comparison signal Co3. The third comparison signal Co3 is used to indicate whether the load state of the speaker 12 is an open circuit state. The third comparison unit 53 includes a comparator 531, which has a non-inverting input terminal coupled to the signal output circuit 3 to receive the first output signal Os1, an inverting input terminal coupled to the reference voltage generating circuit 4 to receive the third reference voltage Ro3, and an output terminal for outputting the third comparison signal Co3. For example, when the logic level of the third comparison signal Co3 is a high logic level "1", it indicates that the load state of the speaker 12 is an open circuit state.

[0124] The fourth comparison unit 54 compares the first output signal Os1 with the fourth reference voltage Ro4 (e.g., 1 mV) to generate a fourth comparison signal Co4. The fourth comparison signal Co4 is used to indicate whether the load state of the speaker 12 is a short circuit state. For example, when the logic level of the fourth comparison signal Co4 is a high logic level "1", it indicates that the load state of the speaker 12 is a short circuit state. The fourth comparison unit 54 includes a comparator 541 and an error corrector 542. The comparator 541 has a non-inverting input terminal coupled to the reference voltage generating circuit 4 to receive the fourth reference voltage Ro4, an inverting input terminal coupled to the signal output circuit 3 to receive the first output signal Os1, and an output terminal for outputting the fourth comparison signal Co4. The error corrector 542 is enabled by the enable signal En from the control circuit 9 and can be used to perform error calibration on the comparator 541. The error corrector 542 can be a finished product known to those skilled in the art.

[0125] Further reading Figure 3 , is a detailed circuit diagram of the signal output device 32, the sensing circuit 6, and the detection circuit 7 according to an embodiment of the present invention.

[0126] The sensing circuit 6 includes a first resistor 61 , a first transistor 62 and a current limiting unit 63 .

[0127] The first resistor 61 has a first end and a second end. The first end of the first resistor 61 is coupled to the second end of the seventh transistor 324 of the signal output device 32 to receive the feedback signal Fs. The first transistor 62 has a first end coupled to the second end of the first resistor 61, a second end coupled to the first reference voltage terminal NV1, and a control end coupled to its own first end and providing the sensing signal So. The first transistor 62 is a diode-connected transistor. The first transistor 62 is an N-type metal oxide semi-field effect transistor, wherein the drain, source and gate are respectively the first end, the second end and the control end of the first transistor 62. The current limiting unit 63 is used to limit the current flowing into the first transistor 62 to prevent the first transistor 62 from burning. The current limiting unit 63 includes a buffer 631, a second resistor 632, a third resistor 633 and a switch 634.

[0128] The buffer 631 receives an enable signal En from the control circuit 9, and generates an in-phase signal according to the enable signal En. The second resistor 632 has a first end coupled to the buffer 631 to receive the in-phase signal, and a second end coupled to the control end of the seventh transistor 324. The level of the second end of the second resistor 632 (i.e., the control signal C1) is used to control the channel size when the seventh transistor 324 is turned on, so as to limit the current flowing into the first transistor 62. The third resistor 633 has a first end coupled to the second end of the second resistor 632, and a second end. The switch 634 is coupled between the second end of the third resistor 633 and the first reference voltage terminal NV1, and is controlled by the switching signal (i.e., the second comparison signal Co2) to be turned on or off.

[0129] The rough detection output CCo generated by the detection circuit 7 includes a first detection signal CCo1, a second detection signal CCo2 and a third detection signal CCo3. The detection circuit 7 includes a first detection unit 71, a second detection unit 72 and a third detection unit 73. The first detection unit 71 is coupled to the control end of the first transistor 62 of the sensing circuit 6 to receive the sensing signal So, and generates a first detection signal CCo1 according to the sensing signal So. The first detection signal CCo1 is used to indicate whether the load state of the speaker 12 is short-circuited to the power state. For example, when the logic level of the first detection signal CCo1 is a high logic level "1", the load state of the speaker 12 is short-circuited to the power state. The first detection unit 71 includes a ninth transistor 711, a first current source 712, an inverter 713 and a second SR latch 714.

[0130] The ninth transistor 711 has a first end, a second end coupled to the first reference voltage end NV1, and a control end coupled to the first transistor 62 to receive the sensing signal So. The first current source 712 is coupled between the second reference voltage end NV2 and the first end of the ninth transistor 711 to provide a first current (e.g., 15 microamperes (uA)). The inverter 713 is coupled to the first end of the ninth transistor 711, and generates an inverted signal according to the level of the first end of the ninth transistor 711. The second SR latch 714 is coupled to the inverter 713 to receive the inverted signal, and generates a first detection signal CCo1 according to the inverted signal. The ninth transistor 711 is an N-type metal oxide semi-conductor field effect transistor, wherein the drain, source and gate are the first end, the second end and the control end of the ninth transistor 711 respectively. The first transistor 62 and the ninth transistor 711 are combined into a current mirror, and the current ratio of the current flowing through the first end and the second end of the first transistor 62 to the current flowing through the first end and the second end of the ninth transistor 711 is 100 to 1.

[0131] The second detection unit 72 is coupled to the control terminal of the first transistor 62 of the sensing circuit 6 to receive the sensing signal So, and generates a second detection signal CCo2 according to the sensing signal So. The second detection signal CCo2 is used to indicate whether the load state of the speaker 12 is short-circuited to the ground state. For example, when the logic level of the second detection signal CCo2 is a high logic level "1", it indicates that the load state of the speaker 12 is short-circuited to the ground state. The second detection unit 72 includes a tenth transistor 721 and a second current source 722.

[0132] The tenth transistor 721 has a first end for providing a second detection signal CCo2, a second end coupled to the first reference voltage end NV1, and a control end coupled to the first transistor 62 to receive the sensing signal So. The second current source 722 is coupled between the second reference voltage end NV2 and the first end of the tenth transistor 721 to provide a second current (e.g., 1 microampere (uA)). The tenth transistor 721 is an N-type metal oxide semi-conductor field effect transistor, wherein the drain, source and gate are respectively the first end, the second end and the control end of the tenth transistor 721. The ninth transistor 711 and the tenth transistor 721 are combined into a current mirror, and the current flowing through the first end and the second end of the ninth transistor 711 and the current flowing through the first end and the second end of the tenth transistor 721 have a current ratio of 1:1.

[0133] The third detection unit 73 is coupled to the signal output device 32 to receive the first output signal Os1 and the second output signal Os2, and is coupled to the second detection unit 72 to receive the second detection signal CCo2, and generates a third detection signal CCo3 according to the second detection signal CCo2 and the first output signal Os1 and the second output signal Os2. The third detection signal CCo3 is used to indicate whether the load state of the speaker 12 is an open circuit state. For example, when the logic level of the third detection signal CCo3 is a high logic level "1", it indicates that the load state of the speaker 12 is an open circuit state. The third detection unit 73 includes an eleventh transistor 731, a third current source 732, a twelfth transistor 733, a fourth current source 734, and a thirteenth transistor 735.

[0134] The eleventh transistor 731 has a first end, a second end coupled to the signal outputter 32 to receive the second output signal Os2, and a control end coupled to the signal outputter 32 to receive the first output signal Os1. The third current source 732 is coupled between the second reference voltage terminal NV2 and the first end of the eleventh transistor 731 to provide a third current (e.g., 1 microampere (uA)). The twelfth transistor 733 has a first end coupled to the second reference voltage terminal NV2, a second end providing the third detection signal CCo3, and a control end coupled to the first end of the eleventh transistor 731. The fourth current source 734 is coupled between the second end of the twelfth transistor 733 and the third reference voltage terminal NV3. The thirteenth transistor 735 has a first end coupled to the second detection unit 72 to receive the second detection signal CCo2, a second end coupled to the third reference voltage terminal NV3, and a control end coupled to the second end of the twelfth transistor 733. The eleventh transistor 731 and the thirteenth transistor 735 are each an N-type metal oxide semi-conductor field effect transistor, wherein the drain, source and gate are respectively the first end, the second end and the control end of each of the eleventh transistor 731 and the thirteenth transistor 735. The twelfth transistor 733 is a P-type metal oxide semi-conductor field effect transistor, wherein the source, drain and gate are respectively the first end, the second end and the control end of the twelfth transistor 733.

[0135] See also Figure 4 , for example, when the load state of the speaker 12 is short-circuited to the ground, during a detection cycle T, the waveform diagram of the enable signal En, the first comparison signal Co1, the second comparison signal Co2, the third comparison signal Co3, the fourth comparison signal Co4, the first detection signal CCo1, the second detection signal CCo2 and the third detection signal CCo3 of the embodiment of the present invention are described. Figure 4 It can be seen that at this time, only the logic levels of the first comparison signal Co1 and the second detection signal CCo2 are the high logic level "1". Therefore, the detection result Tr generated by the logic circuit 8 according to the first comparison signal Co1, the second comparison signal Co2, the third comparison signal Co3, the fourth comparison signal Co4, the first detection signal CCo1, the second detection signal CCo2 and the third detection signal CCo3 indicates that the load state of the speaker 12 is short-circuited to the ground.

[0136] In summary, since the load detection device 2 of the present invention utilizes the signal output circuit 3 to generate the forced current Io, and the comparison circuit 5 compares the reference signal output Ro and the first output signal Os1 with the second output signal Os2, a precise comparison output Co can be generated, and the sensing circuit 6 generates the sensing signal So for the detection circuit 7 to detect, and a rough detection output CCo can be generated. In this way, the logic circuit 8 can obtain the load state of the speaker 12 according to the precise comparison output Co and the rough detection output CCo. Therefore, the present invention does not need to be configured with an analog-to-digital converter and / or a digital-to-analog converter like the existing load detection device, and thus the load detection device 2 of the present invention has a smaller circuit area and a compact design, so that the load detection device 2 is easier to manufacture and form an integrated circuit with the audio amplifier 11.

[0137] The present invention has been disclosed above with preferred embodiments, but those skilled in the art should understand that the embodiments are only used to describe the present invention and should not be interpreted as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to the embodiments should be considered to be within the scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the content defined in the claims.

Claims

1. A load detection device for an audio amplifier system, the audio amplifier system comprising a first load terminal and a second load terminal coupled to a speaker, characterized in that: The load detection device comprises: a signal output circuit, coupled to the first load terminal and the second load terminal, for generating and outputting a forced current to the first load terminal, and generating a bias signal, a first output signal related to a level of the first load terminal, a second output signal related to a level of the second load terminal, and a feedback signal depending on the forced current; A reference voltage generating circuit, coupled to the signal output circuit to receive the bias signal, and generating a reference signal output according to the bias signal; a comparison circuit coupled to the signal output circuit to receive the first output signal and the second output signal, and coupled to the reference voltage generating circuit to receive the reference signal output, and compare the reference signal output and the first output signal with the second output signal to generate an accurate comparison output for indicating the load status of the speaker; a sensing circuit, coupled to the signal output circuit to receive the feedback signal, and to generate a sensing signal according to the feedback signal; a detection circuit coupled to the sensing circuit to receive the sensing signal, coupled to the signal output circuit to receive the first output signal and the second output signal, and generating a rough detection output indicating a load state of the speaker according to the sensing signal and the first output signal and the second output signal; a logic circuit coupled to the comparison circuit and the detection circuit to receive the precise comparison output and the rough detection output respectively, and obtain the speaker load state according to the precise comparison output and the rough detection output to generate a detection result; and The control circuit is used for generating an enable signal and outputting the enable signal to the signal output circuit, the comparison circuit, the sensing circuit and the logic circuit to enable the signal output circuit, the comparison circuit, the sensing circuit and the logic circuit.

2. The load detection device for an audio amplifier system according to claim 1, characterized in that: The induction circuit comprises: A first resistor having a first end coupled to the signal output circuit to receive the feedback signal, and a second end; A first transistor having a first end coupled to the second end of the first resistor, a second end coupled to a first reference voltage end, and a control end coupled to the first end thereof and providing the sensing signal; and A current limiting unit, used to limit the current flowing into the first transistor, the current limiting unit comprising: a buffer, receiving the enable signal from the control circuit and generating an in-phase signal according to the enable signal, a second resistor having a first end coupled to the buffer to receive the in-phase signal and a second end, wherein the level of the second end of the second resistor is used to limit the current flowing into the first transistor, a third resistor having a first end coupled to the second end of the second resistor and a second end, and The switch is coupled between the second end of the third resistor and the first reference voltage end, and is controlled by a switching signal to be turned on or off.

3. The load detection device for an audio amplifier system according to claim 1, characterized in that: The signal output circuit comprises: a current generator, configured to generate and output the forced current according to an input current, and to generate the bias signal; and A signal outputter is enabled by the enable signal from the control circuit, coupled to the first load terminal and the second load terminal, and coupled to the current generator to receive the forced current and output it to the first load terminal. The signal outputter generates and outputs the first output signal, the second output signal, and the feedback signal.

4. The load detection device for an audio amplifier system according to claim 3, characterized in that: The current generator comprises: A second transistor has a first terminal, a second terminal receiving the input current, and a control terminal coupled to the second terminal; and The third transistor has a first end coupled to the first end of the second transistor, a second end outputting the forced current, and a control end coupled to the control end of the second transistor.

5. The load detection device for an audio amplifier system according to claim 3, characterized in that: The signal output device comprises: a fourth transistor having a first terminal coupled to the current generator to receive the forced current, a second terminal coupled to the first load terminal, and a control terminal receiving the enable signal; a fifth transistor having a first terminal coupled to the first load terminal, a second terminal providing the first output signal, and a control terminal; a sixth transistor having a first terminal coupled to the second load terminal, a second terminal providing the second output signal, and a control terminal; and The seventh transistor has a first terminal coupled to the second load terminal, a second terminal providing the feedback signal, and a control terminal.

6. The load detection device for an audio amplifier system according to claim 1, characterized in that: The reference signal output includes a first reference voltage, a second reference voltage, a third reference voltage and a fourth reference voltage, the speaker load state includes a short circuit to ground state, a short circuit to power state, a short circuit state and an open circuit state, the precise comparison output includes a first comparison signal, a second comparison signal, a third comparison signal and a fourth comparison signal, and the comparison circuit includes: a first comparison unit, for comparing one of the first output signal and the second output signal with the first reference voltage to generate the first comparison signal, wherein the first comparison signal is used to indicate whether the speaker load state is the short-circuit to ground state; a second comparison unit, for comparing one of the first output signal and the second output signal with the second reference voltage to generate the second comparison signal, wherein the second comparison signal is used to indicate whether the speaker load state is the short-circuit-to-power state; a third comparing unit, which compares the first output signal with the third reference voltage to generate the third comparison signal, wherein the third comparison signal is used to indicate whether the speaker load state is the open circuit state; and The fourth comparison unit compares the first output signal with the fourth reference voltage to generate the fourth comparison signal, wherein the fourth comparison signal is used to indicate whether the speaker load state is the short circuit state.

7. The load detection device for an audio amplifier system according to claim 6, characterized in that: The second comparison unit comprises: an eighth transistor having a first terminal for receiving one of the first output signal and the second output signal, a second terminal, and a control terminal; a comparator having a non-inverting input terminal coupled to the second terminal of the eighth transistor to receive one of the first output signal and the second output signal, an inverting input terminal to receive the second reference voltage, and an output terminal, the output terminal providing a comparison result obtained by comparing one of the first output signal and the second output signal with the second reference voltage; a level converter coupled to the output terminal of the comparator to receive the comparison result, and to generate and output a conversion signal according to the comparison result, wherein a voltage swing of the comparison result is different from a voltage swing of the conversion signal; and The first SR latch is coupled to the level converter to receive the conversion signal and generates the second comparison signal according to the conversion signal.

8. The load detection device for an audio amplifier system according to claim 1, characterized in that: The speaker load state includes a short circuit to ground state, a short circuit to power state and an open circuit state, the rough detection output includes a first detection signal, a second detection signal and a third detection signal, and the detection circuit includes: a first detection unit, coupled to the sensing circuit to receive the sensing signal, and generating the first detection signal according to the sensing signal, wherein the first detection signal is used to indicate whether the speaker load state is the short-circuit to power state; a second detection unit, coupled to the sensing circuit to receive the sensing signal, and generating a second detection signal according to the sensing signal, wherein the second detection signal is used to indicate whether the speaker load state is the short-circuit to ground state; and A third detection unit is coupled to the signal output circuit to receive the first output signal and the second output signal, and is coupled to the second detection unit to receive the second detection signal, and generates the third detection signal according to the second detection signal and the first output signal and the second output signal, wherein the third detection signal is used to indicate whether the speaker load state is the open circuit state.

9. The load detection device for an audio amplifier system according to claim 8, characterized in that: The first detection unit comprises: a ninth transistor having a first terminal, a second terminal coupled to the first reference voltage terminal, and a control terminal coupled to the sensing circuit to receive the sensing signal; A first current source, coupled between a second reference voltage terminal and the first terminal of the ninth transistor, for providing a first current; an inverter coupled to the first end of the ninth transistor and generating an inverted signal according to a level of the first end of the ninth transistor; and The second SR latch is coupled to the inverter to receive the inverted signal and generates the first detection signal according to the inverted signal.

10. The load detection device for an audio amplifier system according to claim 8, characterized in that: The second detection unit comprises: a tenth transistor having a first terminal for providing the second detection signal, a second terminal coupled to the first reference voltage terminal, and a control terminal coupled to the sensing circuit to receive the sensing signal; and The second current source is coupled between a second reference voltage terminal and the first terminal of the tenth transistor to provide a second current.

11. The load detection device for an audio amplifier system according to claim 8, characterized in that: The third detection unit comprises: an eleventh transistor having a first terminal, a second terminal coupled to the signal output circuit to receive the second output signal, and a control terminal coupled to the signal output circuit to receive the first output signal; a third current source, coupled between a second reference voltage terminal and the first terminal of the eleventh transistor, for providing a third current; A twelfth transistor having a first terminal coupled to the second reference voltage terminal, a second terminal for providing the third detection signal, and a control terminal coupled to the first terminal of the eleventh transistor; a fourth current source coupled between the second terminal of the twelfth transistor and a third reference voltage terminal; and The thirteenth transistor has a first end coupled to the second detection unit to receive the second detection signal, a second end coupled to the third reference voltage end, and a control end coupled to the second end of the twelfth transistor.

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