Etching analysis system and etching analysis method

Abstract

The invention provides an etching analysis system and an etching analysis method. The etching analysis system comprises a measuring device and a processing device. The measuring device is configured to measure a substrate and obtain image information of a first area of the substrate. The processing device is electrically connected with the measuring device. The processing device is configured to generate a plurality of pieces of control point information corresponding to the first area according to the image information so as to generate measurement line information, and is configured to adjust an operation parameter or a line layout parameter of an etching device according to the measurement line information. The ratio of the number of the plurality of control points corresponding to the control point information to the number of all the measurement points in the first area is greater than 80%. According to the etching analysis system and the etching analysis method, non-contact detection can be carried out by using the image, the detection accuracy and convenience are not influenced by the size of the electronic component, and a large-scale, rapid and high-precision detection effect is achieved.

Description

Technical Field

[0001] The present invention relates to etching analysis technology, in particular to a non-contact etching analysis system and an etching analysis method. Background Art

[0002] Etching processes are widely used to form complex circuit patterns on various substrates to form electronic components such as printed circuit boards, flexible circuit boards, etc. As the size of electronic components is gradually miniaturized, the size of circuit patterns has become more refined. However, the miniaturization of size has brought challenges to the etching process. For example, during the etching process, some locations of the substrate may have unexpected etching rates, resulting in the circuit pattern not meeting expectations or even causing the circuit pattern to fail.

[0003] In the prior art, the process of wet etching process is usually to immerse a substrate provided with a patterned mask and a conductive layer into an etching solution to form an electronic component with a specific circuit pattern. Ideally, the formed circuit pattern has a stable line width (for example, upper line width and lower line width) and line height. However, in actual conditions, different positions of a single substrate may exhibit different etching rates, resulting in uneven line widths of the formed circuit pattern. In some cases, different substrates produced in the same batch may also exhibit different etching rates at corresponding positions (for example, the central area). As a result, the electronic components may not meet the design requirements.

[0004] Therefore, how to effectively analyze the etching process and improve the possible problems mentioned above has become an urgent issue to be solved in this field. Summary of the invention

[0005] In some embodiments, an etching analysis system is provided. The etching analysis system includes a measuring device and a processing device. The measuring device is configured to measure a substrate and obtain image information of a first area of ​​the substrate. The processing device is electrically connected to the measuring device. The processing device is configured to generate a plurality of control point information corresponding to the first area according to the image information, and then generate a measurement circuit information, and is configured to adjust an operating parameter or a circuit layout parameter of an etching device according to the measurement circuit information. The ratio of the number of the plurality of control points corresponding to the control point information to the number of all measurement points in the first area is greater than 80%.

[0006] In some embodiments, an etching analysis method is provided. The etching analysis method includes: measuring a substrate by a measuring device to obtain image information of a first area of ​​the substrate; generating a plurality of control point information corresponding to the first area according to the image information by a processing device, and then generating a measurement circuit information, wherein the ratio of the number of the plurality of control points corresponding to the control point information to the number of all measurement points in the first area is greater than 80%; and adjusting an operation parameter or a circuit layout parameter of an etching device according to the measurement circuit information by the processing device.

[0007] The etching analysis system and etching analysis method of the present invention can use images for non-contact detection, and the detection accuracy and convenience are not affected by the size of the electronic components, so as to achieve large-scale, fast, and high-precision detection effects. It can also use control point, fluorescence and other detection technologies to be applied to the etching process of various electronic components, and has a high application field and wide range of detection methods. In order to make the features and advantages of the present invention more obvious and easy to understand, various embodiments are specifically cited below, and are described in detail as follows in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description is combined with the accompanying drawings to better understand the viewpoints of the embodiments of the present invention. It is worth noting that, according to standard practices in the industry, some components (features) may not be drawn to scale. In fact, the sizes of different components may be increased or reduced in order to clearly describe.

[0009] Figure 1 is a block diagram showing an etching analysis system according to some embodiments of the present invention;

[0010] Figure 2 is a schematic diagram showing an etching analysis system according to some embodiments of the present invention;

[0011] Figure 3 is a three-dimensional schematic diagram showing an electronic component according to some embodiments of the present invention;

[0012] Figure 4 is a three-dimensional schematic diagram showing electronic components according to some other embodiments of the present invention;

[0013] Figure 5 is a fluorescent schematic diagram showing an electronic component according to some other embodiments of the present invention;

[0014] Figure 6 is a flow chart showing an etching analysis method according to some embodiments of the present invention;

[0015] Figure 7 is a schematic top view showing an electronic component according to some embodiments of the present invention;

[0016] Figure 8 is a schematic side view of an electronic component according to some embodiments of the present invention;

[0017] Fig. 9 is a schematic cross-sectional view showing an electronic component according to some embodiments of the present invention;

[0018] Fig.10 is a schematic diagram showing the distribution of control points according to some embodiments of the present invention;

[0019] Fig.11 is a schematic diagram of setting control points by partition according to some other embodiments of the present invention;

[0020] Fig.12 is a schematic diagram of setting distribution of control points based on feature importance according to some other embodiments of the present invention;

[0021] Fig.13 According to some other embodiments of the present invention, a distribution diagram of control points is focused on and set based on past measurement results;

[0022] Fig.14 is a schematic diagram showing the partitioning of electronic components according to some embodiments of the present invention;

[0023] Fig.15 is a schematic diagram showing abnormal marking of an electronic component according to some embodiments of the present invention;

[0024] Fig.16 is a schematic diagram showing an analysis of an electronic component according to some embodiments of the present invention;

[0025] Fig.17 According to some other embodiments of the present invention, a schematic diagram showing the partitioning of multiple electronic components; and

[0026] Fig.18 2 is a schematic diagram showing analysis of electronic components according to some other embodiments of the present invention.

[0027] The following are marked in the figure:

[0028] 1: Etching analysis system

[0029] 11: Measuring device

[0030] 11a: First image capturing device

[0031] 11b: Second image capturing device

[0032] 11c: Third Image Capturing Device

[0033] 11d: Dispersive confocal displacement sensing device

[0034] 11e: Fourth image capturing device

[0035] 12: Processing device

[0036] 13: Carrying device

[0037] 14: Mobile Devices

[0038] 15: Light source device

[0039] 15a: Excitation light generating device

[0040] Ld1: Excitation light

[0041] BD1: Line

[0042] BD2: Organic layer

[0043] J1: Diffuse fluorescence

[0044] A1: First Area

[0045] A2: Second Area

[0046] A3: The third area

[0047] A20: Area 20

[0048] C: Circuit pattern

[0049] C10: Side surface

[0050] D: Side wall width when viewed from above

[0051] E: Abnormal mark

[0052] H: Line height

[0053] M1(X1,Y1,Z1), Mn(Xn,Yn,Zn), MN(XN,YN,ZN): coordinates

[0054] S:Substrate

[0055] S1: First substrate

[0056] S2: Second substrate

[0057] S3: The third substrate

[0058] S20: twentieth substrate

[0059] SA1, SA2, SA3, SA8, SA26, SAn: First sub-area

[0060] W1: Upper line width

[0061] W2: Lower line width

[0062] W3: Side wall width

[0063] θ: Angle

[0064] AR1~AR64: Area

[0065] Y1~Y64: control point

[0066] RG1~RG16: Sub-area

[0067] AT1~AT64: Area

[0068] Z1~Z64: Control point

[0069] RH1: Straight wire

[0070] RH2: Turning Line

[0071] RH3: Round hole

[0072] RH4: pad area

[0073] P1~P4: Control points

[0074] IM1: Substrate Image

[0075] RK1: Straight wire

[0076] IM2: Standard film

[0077] RK2: Straight wire

[0078] IM3: Substrate Image

[0079] U1: Control point

[0080] U2: Control point DETAILED DESCRIPTION

[0081] The following invention provides many different embodiments or examples for implementing the provided etching analysis system and etching analysis method. Specific examples of each component and its configuration are described below to simplify the embodiments of the present invention, but are certainly not intended to limit the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present invention may repeat component symbols and / or characters in different embodiments or examples. Such repetition is for simplicity and clarity, and is not used to indicate the relationship between the different embodiments and / or examples discussed.

[0082] Directional terms mentioned herein, such as "up", "down", "left", "right" and the like, are with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate rather than to limit the present invention.

[0083] In some embodiments of the present invention, terms such as "disposed", "connected" and the like, unless otherwise defined, may refer to two components being in direct contact, or may refer to two components not being in direct contact, wherein an additional component is located between the two structures. Terms such as "disposed", "connected" and the like may also include situations where both structures are movable or both structures are fixed.

[0084] In addition, the terms "first", "second" and similar terms mentioned in this specification or the scope of the patent application are used to name different components or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor are they used to limit the manufacturing order or setting order of the components.

[0085] Hereinafter, "approximately", "substantially" or similar terms mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range of values. The given number is an approximate number, that is, in the absence of a specific description of "approximately" or "substantially", the meaning of "approximately" or "substantially" can still be implied.

[0086] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those having ordinary knowledge in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0087] The present invention provides an etching analysis system and an etching analysis method, which can effectively adjust the operating parameters of the etching process or the circuit layout parameters by analyzing the image of the circuit pattern, thereby improving the problems described in the prior art. It is worth mentioning that although the prior art takes the electronic components that have undergone the wet etching process as an example, the present invention is not limited to this. In some embodiments, the etching analysis system and the etching analysis method of the present invention can also be used for electronic components that have undergone the dry etching process, or for electronic components that have undergone a mixed process including the wet etching process and the dry etching process, to improve the problems described in the prior art.

[0088] In some embodiments, the substrate of the electronic component may be or may include a polymer material, a fiber material, or other suitable materials, but the present invention is not limited thereto. For example, the polymer material may be or may include epoxy resin, polyimide (PI), polypropylene (PP), other suitable polymer materials, or a combination thereof. For example, the fiber material may be or may include carbon fiber, glass fiber, other suitable fiber materials, or a combination thereof. In some embodiments, the substrate of the electronic component may be a printed circuit board (PCB), a flexible printed circuit (FPC), a ceramic substrate, or other types of boards on which various conductive circuits can be etched on the surface. In addition, the substrate of the electronic component may also be a wafer, but the present invention is not limited thereto.

[0089] In some embodiments, the circuit pattern of the electronic component may be or may include a conductive material. For example, the conductive material may be or may include a metal, a metal compound, other suitable conductive materials or a combination thereof, but the present invention is not limited thereto. For example, the metal may be or may include tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), germanium (Ge), or an alloy thereof. For example, the metal compound may be or may include tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi2), indium tin oxide (ITO), etc.

[0090] Next, we will refer to Figures 1 to 3 To describe some embodiments of the etching analysis system and etching analysis method of the present invention, so as to make the present invention clearer and easier to understand. Figure 1 and Figure 2 are the block diagram and schematic diagram of the etching analysis system, and Figure 3 It is a three-dimensional schematic diagram of an electronic component.

[0091] like Figure 1 As shown, the etching analysis system 1 includes a measuring device 11, a processing device 12, a carrying device 13, a moving device 14 and a light source device 15. The processing device 12 is electrically connected to the measuring device 11, the carrying device 13, the moving device 14 and the light source device 15 to control the above devices to perform etching analysis on the circuit pattern of an electronic component. Figure 2 and Figure 3 A substrate S and a circuit pattern C thereon are shown as examples of etching analysis. The circuit pattern C is the remaining conductive layer after the etching process, which protrudes from the surface of the substrate S. In some embodiments, the cross-section of the circuit pattern C may have a trapezoidal shape. In other words, the width of the upper surface of the circuit pattern C (i.e., the upper line width) may be smaller than the width of the lower surface (i.e., the lower line width).

[0092] like Figure 2 As shown, in some embodiments, the measuring device 11 includes a first image capturing device 11a and a second image capturing device 11b. The first image capturing device 11a is configured to measure a first area A1 of the substrate S to obtain a first top view image corresponding to the first area A1. For example, the first image capturing device 11a can be disposed directly above the substrate S, and the first top view image can be obtained by vertically photographing the first area A1 of the substrate S. It is worth mentioning that the term "directly above" used herein includes an error range that does not affect the accuracy of the image, or includes an error range that can be corrected by image processing.

[0093] like Figure 3 As shown, in some embodiments, the size (e.g., area) of the first area A1 may be the same as the size (e.g., area of ​​the upper surface) of the substrate S. In other words, in these embodiments, the first image capture device 11a may capture the entire surface of the substrate S to obtain a first top view image corresponding to the full version of the substrate S. However, the present invention is not limited thereto. In other embodiments, the size of the first area A1 may be smaller than the size of the substrate S. In other words, in these embodiments, the first image capture device 11a may only capture a local area (e.g., a central area) of the substrate S where the circuit pattern C is provided, and avoid other areas (e.g., a peripheral area) where the circuit pattern is not provided, to obtain a first top view image corresponding to a partial surface of the substrate S. In this case, the amount of information (e.g., the number of bits) of the first top view image may be reduced, thereby improving the efficiency of subsequent image processing.

[0094] In some embodiments, the first image capture device 11a may include an optical lens and a photosensitive element coupled to the optical lens. For example, the optical lens may be or may include a telecentric lens, which can make the captured image not affected by lens parallax within a certain physical distance and obtain a wide depth of field effect at the same time. Alternatively, the optical lens may also be a general lens, a wide-angle lens, a telephoto lens, a combination thereof, or other suitable lenses, but the present invention is not limited thereto. For example, the photosensitive element may be a charge-coupled device or a complementary metal-oxide-semiconductor (CMOS), a combination thereof, or other suitable photosensitive elements, but the present invention is not limited thereto.

[0095] like Figure 2 As shown, the second image capture device 11b is configured to measure the first area A1 of the substrate S at an inclined side to obtain a first side view image corresponding to the substrate S. For example, the second image capture device 11b can be disposed obliquely above the substrate S (for example, on one side of the first image capture device 11a), and the first area A1 of the substrate S is photographed at an inclined angle to obtain the first side view image. In some embodiments, an angle θ is formed between the optical axis of the second image capture device 11b and the normal direction of the substrate S, wherein the angle θ may be greater than 0 degrees and less than or equal to 90 degrees. For example, the angle θ may be 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 90 degrees, or any value or any range therebetween. In some embodiments, the optical axis of the second image capture device 11b may be substantially parallel to the normal direction of the side surface of the circuit pattern C, but the present invention is not limited thereto.

[0096] In some embodiments, the second image capture device 11b may include a plurality of second sub-image capture devices (not shown in the figure), and each of these second sub-image capture devices may measure the first area A1 at different angles (e.g., different included angles θ) to obtain a plurality of first side-view images. For example, a second sub-image capture device may be disposed on each side of the first image capture device 11a, or two second sub-image capture devices may be disposed on the same side of the first image capture device 11a to obtain a plurality of first side-view images with different viewing angles. By obtaining a plurality of first side-view images with different viewing angles, subsequent image processing and etching analysis may be made more accurate.

[0097] In some embodiments, the second image capture device 11b or the second sub-image capture device may include an optical lens and a photosensitive element coupled to the optical lens. For example, the optical lens may be or may include a telecentric lens, a general lens, a wide-angle lens, a telephoto lens, a combination thereof, or other suitable lenses, but the present invention is not limited thereto. For example, the photosensitive element may be a photoelectric coupling element or a complementary metal oxide semiconductor, a combination thereof, or other suitable photosensitive element, but the present invention is not limited thereto. In some embodiments, the first image capture device 11a may be similar to or the same as the second image capture device 11b (or its second sub-image capture device), but the present invention is not limited thereto. For example, different optical lenses or photosensitive elements may be used for the first image capture device 11a and the second image capture device 11b, respectively, according to the image requirements of the first overhead view image and the second overhead view image.

[0098] It is worth noting that the specific configuration of the measuring device 11 described above is only an example, and the present invention is not limited thereto. Any electronic device that can be used to measure electronic components can be applied to the present invention. Figure 4 , which is a three-dimensional schematic diagram showing an electronic component according to some other embodiments of the present invention. As shown in the figure, in some embodiments, the measuring device 11 includes a third image capturing device 11c and a dispersive confocal displacement sensing device 11d. The third image capturing device 11c is configured to measure the first area A1 of the substrate S to obtain a top view image corresponding to the first area A1. Since the third image capturing device 11c may be similar or identical to the first image capturing device 11a or the second image capturing device 11b described above, it will not be described in detail.

[0099] On the other hand, the dispersive confocal displacement sensing device 11d is disposed on one side of the third image capturing device 11c and is used to obtain the light wave signal of the first area A1. Specifically, the light wave signal can be calculated to obtain information such as the thickness, height, and depth of the circuit pattern C. In some embodiments, the dispersive confocal displacement sensing device 11d is configured to measure the first area A1 (such as Figure 4 In some embodiments, the dispersive confocal displacement sensing device 11d may also be disposed on the inclined side of the third image capturing device 11c (not shown) to measure the first area A1 by tilting, but the invention is not limited thereto.

[0100] Continue to refer to Figure 1 and Figure 2 (or Figure 1 and Figure 4). In some embodiments, in addition to controlling the measuring device 11, the carrying device 13, the moving device 14 and the light source device 15, the processing device 12 is also configured to correspond to the multiple control point information of the first area, thereby generating a measurement circuit information, and is configured to adjust the operation parameters or circuit layout parameters of the etching device (not shown in the figure) according to the measurement circuit information. The ratio of the number of the multiple control points corresponding to the control point information to the number of all the measurement points in the first area is greater than 80%. For example, when the minimum unit of the measurement point is a pixel, when the number of pixels is 50 million groups, the number of control points can be more than 40 million groups, thereby achieving a large number of measurements and high precision effects.

[0101] The control point information may include coordinate information and / or measurement line information, and the coordinate information may be two-dimensional coordinates (e.g., pixel coordinates) or three-dimensional coordinates, but the present invention is not limited thereto. In some feasible embodiments, the present invention may use a large number of control point measurements to improve the overall accuracy and efficiency of the measurement process, for example, multiple sampling control points may be set for the object to be measured for measurement, a large number of control points may be set for measurement, or all control points may be set for measurement, but the present invention is not limited thereto.

[0102] The measured circuit information includes physical characteristics of the circuit pattern C, such as upper line width, lower line width, line height, line spacing, line volume or three-dimensional line shape, but the present invention is not limited thereto. In some embodiments, the measured circuit information may also include etching factor information, intensity distribution information, stability distribution information and process capability index (CPK), but the present invention is not limited thereto. The specific operation for generating the measured circuit information will be further described in the etching analysis method below, and only the possible configurations and functions of each device are described here.

[0103] In addition to the above two different embodiments, the detection process of the substrate S can also be completed by means of fluorescence detection. For example, please refer to Figure 5 , is a schematic diagram showing fluorescence of electronic components according to some other embodiments of the present invention. As shown in the figure, in some other embodiments, the measuring device 11 includes at least one excitation light generating device 15a and a fourth image capturing device 11e. At least one excitation light generating device 15a provides excitation light Ld1 to the first area A1 of the substrate S, so that the first area A1 of the substrate S generates fluorescence, and the line contour of the substrate S is highlighted by the fluorescence, and then the fluorescent image of the substrate S is captured and processed by the processing device 12 to generate image information of the substrate S, and finally the measurement line information is generated according to the image information.

[0104] like Figure 5As shown, the position irradiated by the excitation light Ld1 of the excitation light generating device 15a may be the peripheral area of ​​the substrate S adjacent to the circuit BD1, so that the organic matter (such as the organic matter layer BD2) on the peripheral surface of the circuit is excited to generate diffuse fluorescence J1, so that the peripheral area of ​​the circuit BD1 and the circuit BD1 have a brightness difference, thereby obtaining image information with features highlighted by fluorescence. The excitation light provided by the excitation light generating device 15a may include, but is not limited to, ultraviolet light, X-rays, or any other specific light source that can excite organic matter to generate fluorescence, and the present invention is not limited thereto.

[0105] In some feasible embodiments, the lens of the fourth image capturing device 11 e is equipped with a fluorescence filter, which filters out the reflected excitation light and other ambient light and allows the fluorescence to pass through, thereby eliminating noise in the fluorescence image.

[0106] It is worth noting that, in addition to the above-mentioned implementation of the measuring device 11, in some embodiments, the etching surface information can also be obtained by 3D scanning technology (such as time of flight (TOF), triangulation, stereo vision method), etc., but the present invention is not limited thereto. In addition, in some feasible embodiments, in order to quickly measure the entire board or a part of the area of ​​the substrate S, Figure 2 a first image capturing device 11a, a second image capturing device 11b, Figure 4 The third image capture device 11c or Figure 5 The fourth image capturing device 11e may be selected from but not limited to a line scan image capturing device (Line Scan Camera), and the image information of the first area A1 is quickly acquired through the line scan image capturing device.

[0107] When one or more of the physical characteristics of the circuit pattern C in the measured circuit information, the etching factor information, the intensity distribution information, the stability distribution information, and the process capability index (CPK) do not meet the standards, the processing device 12 can adjust the operating parameters of the etching device or the content of the circuit layout parameters according to these physical characteristics or information. In other words, the present invention analyzes the results of the etching process through the processing device 12 to improve the next etching process according to the results of the etching process.

[0108] In some embodiments, the operating parameters may include the type of etching solution, the concentration of the etching solution, the volume of the etching solution, the temperature of the etching process, the execution time of the etching process, a combination thereof, or other suitable parameters during wet etching; and may include gas composition, gas pressure, radio frequency power, etching time, temperature, exhaust rate, a combination thereof, or other suitable parameters during dry etching, but the present invention is not limited thereto. In some embodiments, the circuit layout may be presented as a digital file of an engineering drawing software, and the circuit layout parameters include the upper line width, lower line width, line height, line spacing, material, a combination thereof, or other suitable parameters of the circuit pattern, but the present invention is not limited thereto.

[0109] In some embodiments, the processing device 12 may include processing and storage components such as a processor, a computer readable medium, and a memory to execute a computer program to implement the functions described above. Examples of processors may include a central processing unit (CPU), a multi-core CPU, a graphics processing unit (GPU), etc., but the present invention is not limited thereto. Examples of computer readable media may include a compact disc read-only memory (CD-ROM), a hard disk drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present invention is not limited thereto. Examples of memory may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, etc., but the present invention is not limited thereto. It is worth mentioning that the term "computer program" used herein refers to an application stored in a computer readable medium, which can be read into a memory for processing by a processor. In some embodiments, the application is written in any combination of one or more programming languages. Programming languages ​​include object-oriented programming languages, such as Java, Smalltalk, C++, or similar languages, and traditional procedural programming languages, such as the C programming language or similar programming languages.

[0110] like Figure 2As shown, the carrier device 13 is configured to transport an electronic component (e.g., a substrate S) having a first area A1 to a shooting area of ​​the measuring device 11. It is worth mentioning that the shooting area refers to the area to which the optical axis of the measuring device 11 points, that is, the area to be captured. For example, the carrier device 13 may include a conveying component for conveying an electronic component (e.g., a substrate S or other substrates), a clamping component or an adsorption component for fixing the electronic component, a combination thereof, or a suitable component known to a person of ordinary skill in the art, but the present invention is not limited thereto. Among them, the conveying component is such as a conveyor belt, the clamping component is such as a robotic arm, and the adsorption component is such as a vacuum adsorption component.

[0111] like Figure 2 As shown, the mobile device 14 is physically connected to the measuring device 11 and is configured to adjust the sensing angle of the measuring device 11. That is, the mobile device 14 can drive, for example, Figure 2 The first image capturing device 11a and the second image capturing device 11b in the embodiment can move, or can drive, for example, Figure 4 The third image capture device 11c and the dispersive confocal displacement sensing device 11d in the image capture device are moved. In some embodiments, the moving device 14 may include a clamping component or an adsorption component for fixing the image capture device, and include a horizontal moving component, a vertical moving component or a combination thereof, but the present invention is not limited thereto. The clamping component is such as a mechanical arm, the adsorption component is such as a vacuum adsorption component, and the horizontal moving component and the vertical moving component are such as electric slide rails.

[0112] like Figure 2 As shown, the light source device 15 is disposed above the first area A1 of the substrate S to provide auxiliary lighting. In some embodiments, the light source device 15 may be a backlight, a ring light, a dome light, a parallel light, a diffuse light, a coaxial light group, a combination thereof, or other suitable light sources, but the present invention is not limited thereto. In some embodiments, a plurality of light source devices 15 may be provided to improve the efficiency of image capture. In some embodiments, a light switching controller connected to different types of light source devices 15 may also be provided. By switching the light mode and capturing the image of the first area A1 of the substrate S under different environments, the contrast between the features may be highlighted, thereby facilitating image capture or image segmentation of the captured area.

[0113] Refer to Figure 6 , which is a flow chart showing an etching analysis method according to some embodiments of the present invention. First, the electronic component (i.e., substrate S) having the first area A1 can be transported to the shooting area of ​​the measuring device 11 by the carrier device 13, and the sensing position and angle of the measuring device 11 can be adjusted by the mobile device 14. It is worth mentioning that the mobile device 14 can also continuously adjust the sensing position and angle of the measuring device 11 in subsequent steps to improve the accuracy of image capture.

[0114] Then, if Figure 6 As shown, in step S0, the substrate S is measured by the measuring device 11 (for example, photographing the substrate S) to obtain image information of the first area A1 of the substrate S. Figure 2 In some embodiments shown, the image information may include a first top view image and a first side view image. Figure 4 In some other embodiments shown, the image information may include a top view image and a light wave signal of the first area A1. Continuing from the above, in step S2, the processing device 12 generates a plurality of control point information corresponding to the first area A1 according to the image information, and then generates measurement line information, wherein the ratio of the number of the plurality of control points corresponding to the control point information to the number of all measurement points in the first area A1 is greater than 80%. In step S4, the processing device 12 adjusts the operating parameters or circuit layout parameters of the etching device according to the measurement line information.

[0115] In order to understand step S2 and step S4 more clearly, refer to Figure 3 , Figures 7 to 9 To describe Figure 2 In some of the embodiments shown, an image analysis operation for measuring line information is performed using a first top view image and a first side view image. Figures 7 to 9 Schematic diagrams of top view, side view and cross-section are shown respectively, showing electronic components according to some embodiments of the present invention.

[0116] In some embodiments, the image analysis operation includes obtaining physical characteristic information. Figure 3 As shown, in some embodiments, the circuit pattern C in the first area A1 is a long strip structure with a trapezoidal cross-sectional area. First, the starting point of the circuit pattern C is defined to have coordinates M1 (X1, Y1, Z1), any point of the circuit pattern C is defined to have coordinates Mn (Xn, Yn, Zn), and the end point of the circuit pattern C is defined to have coordinates MN (XN, YN, ZN).

[0117] Next, the first image capturing device 11a captures the image directly above the electronic component. Figure 7 The first top view image is shown, and the upper line width W1 and the lower line width W2 of the circuit pattern C at the position of the coordinates Mn (Xn, Yn, Zn) are defined by the processing device 12 according to the first top view image. In some embodiments, the top view sidewall width D of the circuit pattern C at the position of the coordinates Mn (Xn, Yn, Zn) can also be directly defined.

[0118] On the other hand, the second image capturing device 11b captures the electronic component from above. Figure 8The first side view image shown in the figure is used to define the side wall width W3 of the circuit pattern C at the position of the coordinate Mn (Xn, Yn, Zn) according to the first side view image by the processing device 13. It is worth mentioning that in this embodiment, since the optical axis of the second image capturing device 11b is substantially parallel to the normal direction of the side wall surface C10 of the circuit pattern C, Figure 8 The first side view image shown only allows observation of one side wall surface C10 of the circuit pattern C. Fig. 9 As shown, after obtaining the top view sidewall width D and the sidewall width W3, the line height H can be obtained by the Pythagorean theorem (D2+H2=W32). In this way, the physical characteristic information of the circuit pattern C at the position of the coordinate Mn (Xn, Yn, Zn) can be obtained (for example, the upper line width W1, the lower line width W2, the line height H, the top view sidewall width D, etc.).

[0119] In other embodiments, the method for calculating the line height H may be replaced by other methods. For example, when the angle θ between the optical axis of the second image capture device 11b and the normal direction of the substrate S is 90 degrees (i.e., the optical axis of the second image capture device 11b is parallel to the extension direction of the upper surface and the lower surface of the substrate S), the line height H can be directly obtained through the first side view image without the need to calculate it through the Pythagorean theorem.

[0120] It is worth mentioning that the image analysis operations described above are only some embodiments of the present invention, which are only used to make the present invention easier to understand, but are not intended to limit the present invention. In other embodiments, image analysis operations different from the above may be used to achieve similar or identical functions. For example, in Figure 4 In some of the embodiments shown, the optical wave signal (and the top view image) captured by the dispersive confocal displacement sensing device 11d can be analyzed by the processing device 12 to directly obtain the measurement line information (eg, the height physical characteristics described above).

[0121] Continuing from the above, the operating parameters or circuit layout parameters of the etching device can be adjusted by the processing device 12 according to the measured circuit information including these physical characteristic information. For example, the step of adjusting the operating parameters for the wet etching device may include: adjusting the type of etching solution, the concentration of the etching solution, the volume of the etching solution, the temperature of the etching process and the execution time of the etching process in the operating parameters, but the present invention is not limited to this. The step of adjusting the operating parameters for the dry etching device may include: selecting the gas composition, adjusting the gas pressure, adjusting the power of the radio frequency, adjusting the etching time, temperature control, exhaust rate control, a combination thereof or other suitable parameters, but the present invention is not limited to this. For example, the step of adjusting the circuit layout parameters for the etching device includes: adjusting the upper line width, lower line width, line height, line spacing, line volume or three-dimensional line shape and material in the circuit layout parameters, but the present invention is not limited to this.

[0122] In some embodiments, the image analysis operation further includes obtaining etching factor information. After obtaining the above-mentioned physical feature information (i.e., upper line width W1, lower line width W2, top view sidewall width D and line height H), the etching factor is defined as line height H / top view sidewall width D. In some embodiments, the value of the etching factor may be between 1.2 and 1.8, but the present invention is not limited thereto. For example, the etching factor may be 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8 or any value or any range between the above values. In other words, in addition to intuitively judging whether the etching process meets expectations by measuring the physical features in the circuit information (e.g., values ​​such as upper line width W1, lower line width W2 and sidewall width W3), it is also possible to judge whether the etching process meets expectations by the etching factor defined above.

[0123] In some embodiments, the cross-section of any position of the circuit pattern C may be a trapezoidal shape that is asymmetric on the left and right, so there may be two etching factors corresponding to the two sides at the position. Therefore, the etching factor may be alternatively defined as line height H / (lower line width W2-upper line width W1) / 2) so that the etching factor at the position is an average value. In other words, the above-mentioned image analysis steps are only examples, which can be replaced or substituted by methods known to those with ordinary knowledge in the relevant technical field.

[0124] For details on how to set the control point information in step S2, please refer to Fig.10 , is a schematic diagram showing the distribution of control points according to some embodiments of the present invention. As shown in the figure, the processing device 12, for example, divides the substrate S into a plurality of areas AR1, AR2...AR64 (such as 2 to the power of N, 64 in the figure), and defines the centroids of the areas AR1, AR2, AR3, AR4...AR64 as control points Y1, Y2, Y3, Y4...Y64 for random sampling measurement. It should be noted that, for the convenience of explanation, some embodiments of the present invention are exemplified with 64 control points, but in practice the number of control points is selected according to actual needs, and the 64 control points are represented only for the convenience of explanation, and the present invention is not limited thereto. In other embodiments, for example, the number of random sampling can be determined according to odd-numbered (AR1, AR3...AR63) or even-numbered (AR2, AR4...AR64) areas or other methods; in some feasible embodiments, random control point measurement can also be performed based on the percentage of the number of divided areas (for example, 70%). The principle of large-scale control point measurement and random sampling measurement is the same, except that the number of segmented areas is different. For example, full measurement means that 100% of the sub-areas must be measured. At this time, the smallest unit of the control point can be a single pixel. For example, when the entire image includes 50 million groups of pixels, 50 million groups of control points are set, but the present invention is not limited to this.

[0125] In some feasible embodiments, the substrate S has multiple sub-regions, and the multiple control points corresponding to the multiple control point information are respectively taken from the corresponding positions of the multiple sub-regions. Specifically, in mass production, the same substrate can integrate multiple repeated sub-regions at the same time, and the processing device 12 and the measurement device 11 can only set multiple control points on a single sub-region of the substrate S to generate measurement line information based on the single sub-region; Fig.10 As shown, when the measuring device 11 captures the image of the substrate, it can only capture a single sub-region (such as sub-region S1). In a feasible embodiment, the processing device 12 and the measuring device 11 can generate measurement circuit information for multiple single sub-regions of the substrate S respectively, and integrate the data of the multiple single sub-regions into the measurement circuit information of a complete substrate through the coordinate positions of the individual sub-regions, but the present invention is not limited thereto.

[0126] In some feasible embodiments, the measuring device 11 may measure only a single sub-area of ​​the processing device 12, for example, by driving the moving device 14. Figure 2 The first image capturing device 11a and the second image capturing device 11b in the embodiment move or drive Figure 4 The third image capture device 11c and the dispersive confocal displacement sensing device 11d are moved to lock the focus position and the imaging range on a single sub-area, and multiple control points are set and measured on the single sub-area. This method can improve the measurement accuracy of the single sub-area; or the measuring device 11 can only capture the entire surface image of the substrate once for the processing device 12, but only set multiple control points and measure at the position of a single sub-area. The present invention is not limited to this.

[0127] Please also read Fig.11, is a schematic diagram of setting control points by partition according to some other embodiments of the present invention. As shown in the figure, the substrate S includes a plurality of sub-regions RG1 to RG16, and the measuring device 11 divides only a single sub-region RG1 into a plurality of regions AT1, AT2...AT64 (such as 2 to the Nth power, 64 in the figure), and defines the centroid of the region AT1, AT2, AT3, AT4...AT64 as the control point Z1, Z2, Z3, Z4...Z64, and performs sampling measurement. It should be noted that, for the convenience of explanation, 64 control points are used as examples in some other embodiments of the present invention, but in practice the number of control points can be selected according to actual needs, and the present invention is not limited thereto. In other embodiments, for example, the number of sampling can be determined according to odd-numbered (AT1, AT3...AT63) or even-numbered (AT2, AT4...AT64) regions or other methods; in a feasible embodiment, random control points can also be measured according to the percentage of the number of divided regions (for example, 70%). The principle of large-scale control point measurement and random sampling measurement is the same, except that the number of segmented areas is different. For example, full measurement means that 100% of the sub-areas must be measured. At this time, the smallest unit of the control point can be a single pixel. For example, when the entire image includes 50 million groups of pixels, 50 million groups of control points are set, but the present invention is not limited to this.

[0128] In some feasible embodiments, the multiple control points corresponding to the control point information of the processing device 12 can be set according to the importance of the line features in the first area A1. Specifically, in areas with higher importance, more control points can be set to increase the accuracy of the measurement, while in areas with lower importance, the setting of control points can be reduced or even omitted, and the amount of calculation of the processing device 12 can be reduced by measuring only the area of ​​interest. In some feasible embodiments, the importance can be determined based on the line type, line characteristics, or substrate characteristics, such as straight wires, turning lines, pad areas, circular holes, wireless areas on the substrate surface, or other similar features, but the present invention is not limited to this. In some feasible embodiments, the importance can be multiple levels, such as providing more control points for features with higher importance levels, and providing fewer control points for features with relatively lower importance, and adjusting the number of control points of individual features in sequence.

[0129] In some feasible embodiments, when the processing device 12 allocates control points according to the importance of the features, it can be determined based on the coordinates set by the user. For example, the user can first provide the coordinates of the features to the processing device 12 for pre-storage. When the processing device 12 allocates the number of control points, it can determine the distribution density of the control points based on the coordinates of the corresponding features. In other feasible embodiments, the processing device 12 can classify and segment based on the type of substrate features through an image processing module, and determine the importance of the features based on the classification results, and then provide a corresponding number of control points for different segmented areas based on the importance, but the present invention is not limited to this. The above-mentioned classification and segmentation can be completed by traditional algorithms (such as binarization, color segmentation, wavelet transform, edge detection, or other similar methods), machine learning, deep learning (such as Mask R-CNN,), but the present invention is not limited to this.

[0130] See also Fig.12 , is a schematic diagram of setting the distribution of control points based on feature importance according to some other embodiments of the present invention. As shown in the figure, the substrate S includes a straight conductor RH1, a turning line RH2, a circular hole RH3, and a pad area RH4. In this embodiment, for example, the importance level of the features can be distributed as circular hole RH3>pad area RH4>turning line RH2>straight conductor RH1. According to the importance level, the control point P3 configured in the circular hole RH3 can be distributed more densely, the control point P4 configured in the pad area RH4 has the second highest distribution density, the control point P2 configured in the turning line RH2 has the third highest distribution density, and the control point P1 configured in the straight conductor RH1 has the most sparse distribution density. In this way, the computing consumption of the processing device 12 is reduced.

[0131] In some feasible embodiments, the multiple control points corresponding to the control point information of the processing device 12 are set according to the measurement circuit information generated by the substrate S in the previous measurement stage. For example, when the processing device 12 generates the measurement circuit information based on the previous substrate (or the same substrate but different sub-area), the corresponding measurement circuit information can be stored in the database and compared with the standard value. When the error between the measurement circuit information and the preset circuit information (standard value) exceeds), it is marked based on the corresponding feature or coordinate. When the processing device 12 generates the measurement circuit information for the next substrate (or the next sub-area) next time, more dense control points can be provided for the features or coordinates exceeding the threshold to improve the measurement precision.

[0132] In some feasible embodiments, the processing device 12 can determine the density of control point distribution by setting different thresholds. For example, when the error between the measurement line information and the preset line information (standard value) exceeds 30%, a high-density control point distribution pair is used to generate the measurement line information of the corresponding area; when the error between the measurement line information and the preset line information (standard value) is between 20% and 30%, a second-highest-density control point distribution pair is used to generate the measurement line information of the corresponding area; when the error between the measurement line information and the preset line information (standard value) is between 10% and 20%, a medium-density control point distribution pair is used to generate the measurement line information of the corresponding area; when the error between the measurement line information and the preset line information (standard value) is less than 10%, a low-density control point distribution pair is used to generate the measurement line information of the corresponding area, and so on. The values ​​disclosed by the above thresholds are only for reference and understanding of the present invention, and these values ​​are not used to limit the protection scope of the present invention.

[0133] See also Fig.13 , is a distribution diagram of control points focused on setting based on past measurement results according to some other embodiments of the present invention. As shown in the figure, the processing device 12 generates measurement line information in the previous measurement stage, and stores the corresponding measurement line information in the database to compare with the standard value. The processing device 12 detects that the error between the measurement line information and the preset line information (standard value) exceeds the threshold value (Threshold). For example, the line width of the straight wire RK1 in the substrate image IM1 is obviously narrower than the straight wire RK2 at the corresponding position of the standard film IM2, so that its error is greater than the threshold value. The processing device 12 stores the position or coordinate corresponding to this error in the database. When the processing device 12 generates measurement line information for the next substrate S (substrate image IM3), more dense control points (such as control point U1) are provided for the corresponding position or coordinate, and the remaining areas can retain relatively sparse control points (such as control point U2) to improve the precision of the measurement of the corresponding specific area.

[0134] Refer to Figures 14 to 16 , which are respectively a schematic diagram showing the partitioning of electronic components, a schematic diagram showing abnormal marking, and a schematic diagram showing analysis according to some embodiments of the present invention. Fig.14As shown, in some embodiments, the image analysis operation further includes obtaining the full-plate intensity distribution information of the substrate S. The full-plate of the substrate S has a plurality of first sub-areas SA1, SA2..., SAn, each of the first sub-areas SA1, SA2..., SAn has the same circuit pattern, and the first sub-areas SA1, SA2..., SAn will be further divided in the subsequent process. The measuring device 11 photographs and the processing device 12 obtains the measured sub-circuit information of each first sub-area SA1, SA2..., SAn, and the processing device 12 then compares the measured sub-circuit information of each first sub-area SA1, SA2..., SAn with a preset circuit information. When the difference between the two exceeds a threshold (for example, 5% above or below the standard), it is considered abnormal, and an abnormal mark E is displayed on the sub-area. In some embodiments, the measured sub-circuit information of each first sub-area can be a circuit-related dimension or an etching factor, but the present invention is not limited to this. When the number of abnormalities in the same first sub-area is greater, the range of the abnormal mark of the first sub-area will also be larger, such as Fig.14 In the example, no abnormality occurs in the first sub-region SA3, while the number of abnormalities in the first sub-region SA8 is much greater than that in the first sub-region SA26. Fig.14 In the figure, the number of abnormalities in the upper half of the substrate S is also greater than that in the lower half. The distribution of abnormal points can be used to show the gradient change of the abnormal etching line, so as to facilitate the subsequent judgment and adjustment of various variables of the substrate process. In some embodiments, in addition to presenting the abnormal point distribution of the entire substrate S, the local abnormal point distribution can also be presented, thereby presenting the local etching abnormal distribution trend. The local substrate S to be presented can be selected by the operator, and the present invention is not limited thereto.

[0135] Next, in some embodiments, as Fig.15 As shown, when any first sub-area (for example, the first sub-area SA1) displays an abnormal mark E, the operator can click on the first sub-area and present the complete circuit pattern of the first sub-area through the display device (not shown in the figure) connected to the processing device 12. The distribution of the abnormal mark E will also be presented on the complete circuit pattern of the first sub-area, so that the defective position of the circuit can be confirmed in detail.

[0136] Next, in some embodiments, as Fig.16 As shown, the number or degree of non-compliance statistics can also be presented in the analysis diagram through a display device (not shown) connected to the processing device 12.

[0137] As mentioned above, after completing the full-plate etching analysis, the processing device 12 is also configured to adjust the operating parameters or circuit layout parameters for the etching device according to the intensity distribution information. For example, for the position where the etching is insufficient, the processing device 12 can increase the temperature and / or humidity of the etching at the corresponding position to speed up the etching speed. Conversely, for the position where the etching is too strong, the above parameters can be reduced to slow down the etching speed; or, the processing device 12 can increase the etching solution concentration and the etching solution flow rate to improve the problem of insufficient etching, and conversely, the above parameters can be reduced to improve the problem of excessive etching. For example, in some embodiments, the processing device 12 can control the injection speed and distribution range of the etching solution by adjusting the pressure and / or direction of the nozzle to improve the problem of uneven etching. For example, in some embodiments, the processing device 12 can adjust the stirring speed of the etching solution, which also helps to ensure the uniformity of etching. For example, in some embodiments, the processing device 12 can adjust the length of time for etching the substrate S, and the etching time is roughly proportional to the etching depth, thereby improving the problem of insufficient etching or excessive etching. For example, in some embodiments, the processing device 12 can adjust the size, shape and material of the mask, and adjust the etching effect by changing the contact range between the etching liquid and the substrate S. For example, in some embodiments, the processing device 12 can increase the contact time between the etching liquid and the substrate S, or increase the concentration and / or flow rate of the etching liquid, to solve the problem that the thickness of the substrate S body, the photoresist layer and / or the circuit layer exceeds the threshold, so as to adjust the etching effect; conversely, the processing device 12 can reduce the contact time between the etching liquid and the substrate S, or reduce the concentration and / or flow rate of the etching liquid, to solve the problem that the thickness of the substrate S body, the photoresist layer and / or the circuit layer is lower than the threshold, so as to adjust the etching effect. The above-mentioned process adjustment methods are only several examples for the convenience of understanding the present invention. The present invention is not limited to the above-mentioned embodiments, and the present invention does not intend to limit the number of process control variables that can be adjusted at one time, which is described in advance.

[0138] In some embodiments, abnormal etching conditions can also be adjusted by changing circuit design parameters. For example, for locations where etching is insufficient, the circuit can be designed to be narrower than the original size, so that the expected size can be achieved under the same process parameters. Conversely, for locations where etching is excessive, the circuit can be designed to be wider than the original size, so that the expected size can be achieved under the same process parameters. The present invention is not limited to this.

[0139] Refer to Fig.17 and Fig.18, which respectively show a partition schematic diagram and an analysis schematic diagram of multiple electronic components according to some embodiments of the present invention. As shown in the figure, in some embodiments, the image analysis operation further includes obtaining stability distribution information. For example, the etching process can be applied to electronic components produced in batches. Each batch of electronic components includes multiple substrates, such as a first substrate S1, a second substrate S2, a third substrate S3, a twentieth substrate S20, etc. In this case, the measuring device 11 is configured to measure the first area A1 of the first substrate S1, the second area A2 of the second substrate S2, the third area A3 of the third substrate S3, the twentieth area A20 of the twentieth substrate S20, etc., to obtain a first image corresponding to the first area A1, a second image corresponding to the second area A2, a third image corresponding to the third area A3, a twentieth image of the twentieth area A20, etc. Among them, the first area A1 of the first substrate S1 corresponds to the second area A2 of the second substrate S2, ... and the twentieth area A20 of the twentieth substrate S20.

[0140] Then, the etching analysis operation as described above can be used to define whether the line width or etching factor at the corresponding positions of these regions (e.g., the central region) meets the standard. When the line width or etching factor exceeds the threshold (e.g., exceeds the standard or is 5% below the standard), the analysis result can be recorded in the memory of the processing device 12. In this way, etching analysis can be performed on mass-produced electronic components to confirm the etching stability at corresponding positions on different substrates. Fig.18 As shown, in some embodiments, the historical data line of the etching factor can be presented in the form of a statistical chart in the analysis schematic diagram through a display device (not shown) connected to the processing device 12.

[0141] Finally, the processing device 12 can generate stability distribution information based on the first measurement circuit information of the first substrate S1, the second measurement circuit information of the second substrate S2, and the third measurement circuit information of the third substrate S3, and adjust the operating parameters or circuit layout parameters used for the etching device according to the stability distribution information. The contents and adjustment directions of the operating parameters and circuit layout parameters can be referred to above and will not be repeated here. It is worth mentioning that although Fig.17 The stability distribution analysis is performed only on the central region of each substrate, but the present invention is not limited thereto. In other embodiments, the stability distribution analysis may be performed on multiple regions of each substrate.

[0142] In some embodiments, the operating parameters or circuit layout parameters for the etching device can be adjusted by using the stability distribution information and the intensity distribution information at the same time, but the present invention is not limited thereto. In some embodiments, the operating parameters or circuit layout parameters can be adjusted first according to the stability distribution information to ensure high stability of the etching process. Then, the operating parameters or circuit layout parameters can be adjusted according to the intensity distribution information to ensure high precision of the etching process.

[0143] In some embodiments, the process capability index (CPK) may be calculated by the following formula:

[0144]

[0145] Among them, USL is the upper specification limit of the selected line segment, LSL is the lower specification limit of the selected line segment, that is, the maximum and minimum values ​​allowed by the process, σ is the standard deviation allowed in the process, and μ is the average value of the measured line information of the entire board S in a specific line segment. By calculating the unitless CPK value, it can be used to evaluate the process capability. When the CPK value is greater than or equal to 1.33, it means that the process capability is good. If the CPK value is less than 1.33, it means that the process needs to be improved.

[0146] It is worth noting that the threshold of the aforementioned measurement circuit information is not limited to 5% and can be changed according to manufacturing requirements. In addition, when performing the aforementioned etching intensity or stability analysis, the etching factor is not limited to be used as the judgment standard, and other judgment standards can be used as required.

[0147] It is worth noting that in some embodiments, the processing device 12 can be an artificial intelligence model, which generates measurement circuit information after receiving the image provided by the measurement device 11 through artificial intelligence, and adjusts the process control variables of the etching process and calculates the adjustment amount of the circuit design parameters through artificial intelligence. In some embodiments, the training of the artificial intelligence model can be completed by providing images with etching defects and / or images without etching defects as training sets to the artificial intelligence model, and using process variables as annotations (for example, images with etching defects are annotated with process parameters that should be adjusted, and images without etching defects are annotated as empty).

[0148] In some embodiments, the etching analysis system 1 can not only analyze and subsequently adjust the circuit pattern of the electronic component, but also perform measurement and adjustment on the hole after etching. For example, after the measuring device 11 obtains the image of the hole, the processing device 12 calculates the hole information such as the upper hole diameter, the lower hole diameter, the hole depth and the hole inclination. In addition to performing defect detection such as the hole bottom / hole wall / inclined hole, the obtained hole information can also be used to adjust the etching process or hole design, but the present invention is not limited to this.

[0149] In summary, the etching analysis system and etching analysis method of the present invention utilize images for non-contact detection, and the detection accuracy and convenience are not affected by the size of electronic components, thereby achieving large-scale, fast, and high-precision detection effects. Control point, fluorescence and other detection technologies can also be utilized and applied to the etching process of various electronic components, and the system has a high application field and a wide range of detection methods.

[0150] The above summarizes a plurality of embodiments so that those of ordinary skill in the art can better understand the concepts of the embodiments of the present invention. It should be understood by those of ordinary skill in the art that other processes and structures can be designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. It should also be understood by those of ordinary skill in the art that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

Claims

1. An etching analysis system, characterized in that: include: A measuring device is configured to measure a substrate and obtain image information of a first area of ​​the substrate; as well as a processing device, electrically connected to the measuring device, configured to generate a plurality of control point information corresponding to the first area according to the image information, thereby generating a measurement circuit information, and configured to adjust an operation parameter or a circuit layout parameter of an etching device according to the measurement circuit information; The ratio of the number of the plurality of control points corresponding to the plurality of control point information to the number of all measurement points in the first area is greater than 80%.

2. The etching analysis system according to claim 1, characterized in that: The measured circuit information includes an upper line width, a lower line width, a line height and a top-view sidewall width. The processing device is also configured to generate an etching factor information based on the upper line width, the lower line width, the line height and the top-view sidewall width, and the processing device is also configured to adjust the operating parameters or the circuit layout parameters used for the etching device according to the etching factor information.

3. The etching analysis system according to claim 1, characterized in that: The size of the first region is equal to or smaller than that of the substrate.

4. The etching analysis system according to claim 1, characterized in that: wherein the substrate has a plurality of first sub-regions, and the measurement circuit information includes a plurality of measurement sub-circuit information corresponding to the plurality of first sub-regions, The processing device is configured to generate intensity distribution information according to the plurality of measurement sub-circuit information, and the processing device is further configured to adjust the operation parameters or the circuit layout parameters used for the etching device according to the intensity distribution information.

5. The etching analysis system according to claim 4, characterized in that: The processing device obtains a process capability index according to the upper specification limit, the lower specification limit, the standard deviation allowed in the process, and the average value of the measurement sub-line information of the selected line segments in all the first sub-areas.

6. The etching analysis system according to claim 1, characterized in that: The measuring device is configured to measure a plurality of substrates and obtain a plurality of image information from corresponding regions of the plurality of substrates. wherein the processing device is further configured to generate a plurality of measurement line information according to the plurality of image information, and is configured to generate a stability distribution information according to the plurality of measurement line information, The processing device is further configured to adjust the operating parameters or the circuit layout parameters for the etching device according to the stability distribution information.

7. The etching analysis system according to claim 1, characterized in that: The processing device is an artificial intelligence model, and the artificial intelligence model generates the measurement circuit information through artificial intelligence, and adjusts the operation parameters or the circuit layout parameters of the etching device through artificial intelligence.

8. The etching analysis system according to claim 1, characterized in that: The substrate has a plurality of first sub-regions, and a plurality of control points corresponding to the plurality of control point information are respectively taken from corresponding positions of the plurality of first sub-regions.

9. The etching analysis system according to claim 1, characterized in that: The multiple control points corresponding to the multiple control point information are set according to the importance of the line characteristics in the first area.

10. The etching analysis system according to claim 1, characterized in that: A plurality of control points corresponding to a plurality of the control point information are set according to the measurement circuit information generated by the substrate in the previous measurement stage.

11. The etching analysis system according to claim 1, characterized in that: The measuring device includes an excitation light generating device, which provides an excitation light to the first area of ​​the substrate, so that the first area of ​​the substrate generates fluorescence.

12. The etching analysis system according to claim 1, characterized in that: The measuring device includes a line scanning image capturing device to obtain the image information of the first area.

13. An etching analysis method, characterized in that: include: Measuring a substrate by a measuring device to obtain image information of a first area of ​​the substrate; generating a plurality of control point information corresponding to the first area according to the image information by a processing device, and then generating a measurement line information, wherein the ratio of the number of the plurality of control points corresponding to the plurality of control point information to the number of all measurement points in the first area is greater than 80%; as well as An operation parameter or a circuit layout parameter of an etching device is adjusted according to the measured circuit information by the processing device.

14. The etching analysis method according to claim 13, characterized in that: The measured circuit information includes an upper line width, a lower line width, a line height, and a top view sidewall width. The etching analysis method further includes: Generate an etching factor information according to the upper line width, the lower line width, the line height and the top-view sidewall width by the processing device; and The operating parameters or the circuit layout parameters used for the etching device are adjusted by the processing device according to the etching factor information.

15. The etching analysis method according to claim 13, characterized in that: The size of the first region is equal to or smaller than that of the substrate.

16. The etching analysis method according to claim 13, characterized in that: The substrate has a plurality of first sub-regions, the measurement circuit information includes a plurality of measurement sub-circuit information corresponding to the plurality of first sub-regions, and the etching analysis method further includes: Generate intensity distribution information according to the plurality of measurement sub-circuit information by the processing device; and The operating parameters or the circuit layout parameters used for the etching device are adjusted by the processing device according to the intensity distribution information.

17. The etching analysis method according to claim 16, characterized in that: Also includes: The processing device obtains the process capability index according to the upper specification limit, the lower specification limit, the standard deviation allowed in the process, and the average value of the measurement sub-line information of the selected line segments in all the first sub-areas.

18. The etching analysis method according to claim 13, characterized in that: Also includes: Measuring a plurality of substrates by the measuring device and obtaining a plurality of image information from corresponding areas of the plurality of substrates; Generate a plurality of measurement line information according to a plurality of the image information by the processing device; Generate stability distribution information according to the plurality of measurement line information by the processing device; as well as The operating parameters or the circuit layout parameters used for the etching device are adjusted by the processing device according to the stability distribution information.

19. The etching analysis method according to claim 13, characterized in that: The processing device is an artificial intelligence model, and the artificial intelligence model generates the measurement circuit information through artificial intelligence, and adjusts the operation parameters or the circuit layout parameters of the etching device through artificial intelligence.

20. The etching analysis method according to claim 13, characterized in that: The substrate has a plurality of first sub-regions, and a plurality of control points corresponding to the plurality of control point information are respectively taken from corresponding positions of the plurality of first sub-regions.

21. The etching analysis method according to claim 13, characterized in that: The multiple control points corresponding to the multiple control point information are set according to the importance of the line characteristics in the first area.

22. The etching analysis method according to claim 13, characterized in that: A plurality of control points corresponding to a plurality of the control point information are set according to the measurement circuit information generated by the substrate in the previous measurement stage.

23. The etching analysis method according to claim 13, characterized in that: The measuring device includes an excitation light generating device, which provides an excitation light to the first area of ​​the substrate, so that the first area of ​​the substrate generates fluorescence.

24. The etching analysis method according to claim 13, characterized in that: The measuring device includes a line scanning image capturing device to obtain the image information of the first area.

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