Layout patterns for static random access memory

Abstract

The invention provides a layout pattern unit of a static random access memory (SRAM), which at least comprises a first SRAM unit, a plurality of gate structures spanning a plurality of fin structures, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor are formed on the substrate. Wherein the first parasitic transistor and the first pull-down transistor span the same fin-shaped structure, and the fin-shaped structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a layout pattern for reducing the on-current (Ion) of a pull-down transistor (PD) and improving the performance of the static random access memory (SRAM). Background Art

[0002] An embedded static random access memory (embedded SRAM) includes a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The way in which static random access memory stores data is to use the conductive state of the transistor in the memory cell. The design of static random access memory is based on mutually coupled transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep the data from being lost. In other words, there is no need to update the memory. This is different from the way that dynamic random access memory (DRAM), which is also a volatile memory, uses the charged state of the capacitor to store data. The access speed of static random access memory is quite fast, so it is used as cache memory in computer systems. Summary of the invention

[0003] The present invention provides a layout pattern unit of a static random access memory (SRAM), which at least includes a first SRAM unit in a first area, wherein the first SRAM unit includes a plurality of fin structures located on a substrate, and a plurality of gate structures located on the substrate, wherein the plurality of gate structures span across the plurality of fin structures to form a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1 (first pull-down transistor), a PD2 (second pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor), a PG2B (fourth access transistor), and a first parasitic transistor and a second parasitic transistor located on the substrate, wherein the first parasitic transistor and the PD1 span the same fin structure, and the fin structure spanned by the first parasitic transistor and the PD1 is a continuous structure.

[0004] The present invention is characterized in that it provides an improved static random access memory (SRAM) layout pattern, which differs from the existing static random access memory pattern in that the fin structure included in the pull-down transistor is a continuous and uninterrupted structure between different regions, so that a parasitic transistor can be formed in conjunction with a gate structure. The applicant has found that forming a parasitic transistor helps to reduce the turn-on current of the pull-down transistor, thereby reducing the difference between the turn-on current of the pull-down transistor and the turn-on current of the pull-up transistor, thereby increasing the operating rate of the SRAM. In addition, forming a parasitic transistor can also reduce the probability of leakage current and improve component quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A circuit diagram of a group of eight-transistor dual port SRAM (8TDP-SRAM) storage cells in the static random access memory of the present invention;

[0006] Figure 2 A layout diagram of a static random access memory according to a first preferred embodiment of the present invention;

[0007] Figure 3 is a layout diagram of two adjacent 8TDP-SRAM memory cells 10;

[0008] Figure 4 It is a schematic diagram of the distribution of multiple regions and fin structures of the present invention.

[0009] Explanation of symbols

[0010] 10: Eight-transistor dual-port static random access memory cell

[0011] 60A: First area connection layer

[0012] 60B: First area connection layer

[0013] 65:Metal layer

[0014] BL1: bit line

[0015] BL2: bit line

[0016] BL3: bit line

[0017] BL4: bit line

[0018] CT: Contact Column

[0019] F: Fin structure

[0020] F1: Fin structure

[0021] F2: Fin structure

[0022] F3: Fin structure

[0023] F4: Fin structure

[0024] F5: Fin structure

[0025] F6: Fin structure

[0026] G: Gate structure

[0027] G1: First gate structure

[0028] G2: Second gate structure

[0029] G3: The third gate structure

[0030] G4: Fourth gate structure

[0031] G5: The fifth gate structure

[0032] G6: Sixth gate structure

[0033] G7: Seventh gate structure

[0034] G8: Eighth Gate Structure

[0035] MD:Metal layer

[0036] MD1: Metal layer

[0037] MD2: Metal layer

[0038] MD3: Metal layer

[0039] MD4: Metal layer

[0040] MP:Metal Layer

[0041] N1: Storage Node

[0042] N2: Storage Node

[0043] O: Center point

[0044] PU1: First pull-up transistor

[0045] PU2: Second pull-up transistor

[0046] PD1: First pull-down transistor

[0047] PD2: Second pull-down transistor

[0048] PG1A: First access transistor

[0049] PG1B: Second access transistor

[0050] PG2A: The third access transistor

[0051] PG2B: fourth access transistor

[0052] PT1: First parasitic transistor

[0053] PT2: First parasitic transistor

[0054] R: Region

[0055] R1: First Area

[0056] R2: Second Area

[0057] S: Base

[0058] Vcc: voltage source

[0059] Vss: voltage source

[0060] WL1: word line

[0061] WL2: word line DETAILED DESCRIPTION

[0062] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0063] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0064] Please refer to Figure 1 and Figure 2 , Figure 1 The present invention is a circuit diagram of a group of eight-transistor dual port static random access memory (eight-transistor dual port SRAM, 8TDP-SRAM) storage cells in the static random access memory. Figure 2 FIG. 4 is a layout diagram of a static random access memory according to the first preferred embodiment of the present invention.

[0065] like Figure 1 and Figure 2 As shown, the SRAM of the present invention preferably comprises at least one group of SRAM cells, wherein each SRAM cell comprises an eight-transistor dual-port SRAM cell (eight-transistor SRAM, 8TDP-SRAM) 10 .

[0066] Please refer to Figure 1 In this embodiment, each 8TDP-SRAM memory cell 10 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1A, a second access transistor PG1B, a third access transistor PG2A, and a fourth access transistor PG2B to form a flip-flop, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit, so that data can be latched in the storage node N1 or N2. In addition, the first pull-up transistor PU1 and the second pull-up transistor PU2 are used as active loads, and they can also be replaced by ordinary resistors as pull-up transistors, in which case it is a four-transistor static random access memory (four-transistor SRAM, 4T-SRAM). In addition, in the present embodiment, a source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0067] In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the 8TDP-SRAM memory cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2 and the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A and the fourth access transistor PG2B are composed of N-type metal oxide semiconductor (NMOS) transistors, but the present invention is not limited thereto. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the two ends of the series circuit formed by the two are respectively coupled to a voltage source Vcc and a voltage source Vss; similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the two ends of the series circuit formed by the two are also respectively coupled to the voltage source Vcc and the voltage source Vss. The access transistors (including the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A and the fourth access transistor PG2B) are respectively connected to the output ends of the two mutually coupled inverters, wherein each pull-up transistor, each pull-down transistor and each access transistor include a gate structure spanning over at least one fin structure to form a fin transistor (FinFET).

[0068] In addition, at the storage node N1, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, as well as the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, the first access transistor PG1A, and the second access transistor PG1B are electrically connected respectively; similarly, at the storage node N2, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, as well as the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, the third access transistor PG2A, and the fourth access transistor PG2B are also electrically connected respectively. The gates of the first access transistor PG1A and the third access transistor PG2A are respectively coupled to a word line WL1, the gates of the second access transistor PG1B and the fourth access transistor PG2B are respectively coupled to a word line WL2, the source of the first access transistor PG1A is coupled to the corresponding bit line BL1, the source of the second access transistor PG1B is coupled to the corresponding bit line BL2, the source of the third access transistor PG2A is coupled to the corresponding bit line BL3, and the source of the fourth access transistor PG2B is coupled to the corresponding bit line BL4.

[0069] In addition, the present embodiment further includes a first parasitic transistor PT1 and a second parasitic transistor PT2. The gate of the first parasitic transistor PT1 is connected to the source and to the voltage source Vss, and the drain of the first parasitic transistor PT1 is connected to the storage node N1. The gate of the second parasitic transistor PT2 is also connected to the source and to the voltage source Vss, and the drain of the second parasitic transistor PT2 is connected to the storage node N2. In the present embodiment, the first parasitic transistor PT1 and the second parasitic transistor PT2 are only non-functional transistors generated due to the configuration of the layout pattern during the manufacturing process. The gate of the first parasitic transistor PT1 and the second parasitic transistor PT2 are connected to the source and are kept in a constant off state, so they have no transistor function. However, the formation of the parasitic transistor can partially affect the electrical properties of the first pull-down transistor PD1 and the second pull-down transistor PD2, which will be described in the following paragraphs.

[0070] Please refer to Figure 2 In the present embodiment, an 8TDP-SRAM memory cell 10 is located in a first region R1 and is disposed on a substrate S, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. A plurality of fin structures F arranged in parallel to each other are disposed on the substrate S, and shallow trench isolation (not shown) is disposed around each fin structure F.

[0071] In addition, the substrate S includes multiple gate structures G, and each of the above-mentioned transistors (including the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, the fourth access transistor PG2B, the first parasitic transistor PT1 and the second parasitic transistor PT2) includes a gate structure G that spans at least one fin structure F and constitutes each transistor.

[0072] like Figure 2As shown, in order to clearly define the position of each gate structure G, the gate structure 56 is divided into a first gate structure G1, a second gate structure G2, a third gate structure G3, a fourth gate structure G4, a fifth gate structure G5, a sixth gate structure G6, a seventh gate structure G7 and an eighth gate structure G8. At the same time, the fin structures are also defined as fin structure F1, fin structure F2, fin structure F3, fin structure F4, fin structure F5 and fin structure F6 according to their positions. It can be understood that the first gate structure G1 to the eighth gate structure G8 all belong to the gate structure G, and the fin structure F1 to the fin structure F6 also belong to the fin structure F. Among them, the first gate structure G1 crosses over the fin structure F1 to form a first pull-down transistor PD1; the first gate structure G1 crosses over the fin structure F3 to form a first pull-up transistor PU1; the second gate structure G2 crosses over the fin structure F2 to form a second access transistor PG1B; the third gate structure G3 crosses over the fin structure F2 to form a first access transistor PG1A; the fourth gate structure G4 crosses over the fin structure F1 to form a first parasitic transistor PT1. On the other hand, the fifth gate structure G5 crosses over the fin structure F4 to form a second pull-down transistor PD2; the fifth gate structure G5 crosses over the fin structure F6 to form a second pull-up transistor PU2; the sixth gate structure G6 crosses over the fin structure F5 to form a third access transistor PG2A; the seventh gate structure G7 crosses over the fin structure F5 to form a fourth access transistor PG2B; the eighth gate structure G8 crosses over the fin structure F4 to form a second parasitic transistor PT2.

[0073] It is worth noting that in the first region R1, the patterns of the transistors are mirror-symmetric along the center point O, so the features of the partially symmetrical elements in the following paragraphs will be the same as the other half and will not be repeated, but will be explained here first.

[0074] In the present invention, each gate structure G is arranged along a first direction (eg, X-axis), and each fin structure F is arranged along a second direction (eg, Y-axis). Preferably, the first direction and the second direction are perpendicular to each other.

[0075] The present invention further includes a first region connection layer 60A and a second region connection layer 60B, both arranged along the first direction (X direction). The first region connection layer 60A spans over the fin structure F included in the first pull-up transistor PU1, the first pull-down transistor PD1, the first access transistor PG1A and the second access transistor PG1B. The second region connection layer 60B spans over the fin structure F included in the second pull-up transistor PU2, the second pull-down transistor PD2, the third access transistor PG2A and the fourth access transistor PG2B.

[0076] In addition, the substrate S includes multiple metal layers MP, metal layers MD and contact pillars CT, which connect different transistors (for example, connecting the gate of the second pull-up transistor PU2 and the drain of the first pull-up transistor PU1), or connecting each transistor to other elements (for example, connecting the source of the first pull-up transistor PU1 to the voltage source Vcc). In this embodiment, the metal layer MP contacts the gate structure G, while the metal layer MD spans over the fin structure F but does not contact the gate structure G, and the contact pillars CT are conductive elements used to connect different layers (for example, the current metal layer and other metal layers above / below). It is understandable that the metal layer MP, the metal layer MD and the contact pillars CT can all be made of materials with good conductivity such as metals, and may include the same or different materials. In addition, the above-mentioned first area connection layer 60A and the second area connection layer 60B also belong to the metal layer MD.

[0077] For the sake of clarity, Figure 2 The components corresponding to each metal layer and the contact column (for example, the voltage source Vcc, the voltage source Vss, the first word line WL1, the second word line WL2, the first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL4) are directly marked on each metal layer MP, MD and the contact column CT to clearly express the corresponding components of each metal layer MP, MD and the contact column CT.

[0078] in addition, Figure 2 The metal layer MD of the other part is defined as follows: the metal layer MD1 connects the source of the first pull-down transistor PD1 and the voltage source Vss; the metal layer MD2 connects the source of the second access transistor PG1B and the bit line BL2; the metal layer MD3 connects the source of the first access transistor PG1A and the bit line BL1; the metal layer MD4 connects the source of the first parasitic transistor PT1. It can be understood that the above metal layers MD1 to MD4 all belong to the metal layer MD.

[0079] In this embodiment, the distance between metal layer MD1 and metal layer MD2 is equal to the distance between metal layer MD3 and metal layer MD4. Such a configuration can make the overall SRAM pattern distribution more uniform. And because the distance from the metal layer of each transistor to the adjacent metal layer is equal, the manufacturing process conditions of each transistor can be controlled to be in an approximate state, which is conducive to improving the stability of the structure and manufacturing process.

[0080] Please refer to Figure 3 , Figure 3 The layout diagram of two adjacent 8TDP-SRAM memory cells 10 is shown. Figure 2 Only one unit of 8TDP-SRAM is shown, which is formed in a first region R1. Figure 3The focus is on the relationship between two adjacent 8TDP-SRAMs, that is, the two 8TDP-SRAM memory cells 10 are respectively located in the adjacent first region R1 and second region R2, so the reference numerals of some components will be omitted. Figure 3 However, it is worth noting that Figure 2 and Figure 3 In the figure, components with the same properties include the same mesh bottom. For example, all gate structures, fin structures, metal layers, contact pillars, etc. are depicted with the same mesh bottom. The same is true for the remaining components depicted in the present invention.

[0081] It is also worth noting that the first region R1 and the second region R2 each include only one 8TDP-SRAM memory cell 10 , and the substrate S may include other regions with 8TDP-SRAM memory cells in addition to the first region R1 and the second region R2 .

[0082] like Figure 3 As shown, one of the features of this embodiment is that, compared to the existing 8TDP-SRAM pattern, the fin structure F1 crossed by the first pull-down transistor PD1 of the present invention extends toward the second direction (Y direction) to other regions, for example, from the first region R1 to the second region R2, and the fourth gate G4 in the first region R1 also crosses the fin structure F1 and forms the first parasitic transistor PT1. Similarly, due to the symmetry of the pattern, the fin structure F4 also extends toward the second direction (Y direction) to other regions, for example, from the first region R1 to the second region R2, and the eighth gate G8 in the first region R1 also crosses the fin structure F4 and forms the second parasitic transistor PT2. The following paragraphs only focus on the pattern in the left half of the first region R1, and the pattern in the right half is not repeated because it has similar features.

[0083] In addition, Figure 3 In the figure, a metal layer 65 is formed to electrically connect the source and gate of the first parasitic transistor PT1, and connect the source and gate of the first parasitic transistor PT1 to another adjacent first parasitic transistor PT1 (i.e., the first parasitic transistor PT1 located in the second region R2). And subsequently, the metal layer 65 is connected to the voltage source Vss through a contact column (not shown). Therefore, the first parasitic transistor PT1 (and the second parasitic transistor PT2) are always off in the circuit. The purpose of forming the metal layer 65 is to connect the parasitic transistor to the voltage source Vss through the metal layer 65 in addition to connecting the gate and source of the parasitic transistor itself, so that the parasitic transistor will not easily affect the electrical properties of the pull-down transistors around it, thereby achieving the effect of stabilizing the current of the pull-down transistor.

[0084] The applicant has found that in the existing 8TDP-SRAM pattern, the turn-on current (Ion) of the first pull-down transistor PD is relatively large, which will cause the voltage conversion rate to be insufficient when the low voltage is increased to the high voltage at the node N1 (or the node N2). This is because the Ion of the PD is larger than the Ion of the PU, which makes it difficult to increase the voltage. Therefore, the switching rate of the SRAM is reduced, affecting the quality and execution speed of the SRAM.

[0085] The applicant has found that one of the methods to reduce the above problem is to reduce the difference between the Ion of the PD and the Ion of the PU. One method is to extend the fin structure (such as the fin structure F1 or F4) included in the PD and form a parasitic transistor. The presence of a parasitic transistor can slightly reduce the Ion of the PD, thereby solving the problem of insufficient voltage conversion rate. In addition, the applicant has found that forming a transistor also helps to reduce the leakage current of the SRAM pattern.

[0086] Figure 4 The schematic diagram of the distribution of multiple regions and fin structures of the present invention is shown. It is worth noting that the 8TDP-SRAM memory cells 10 of the present invention can be repeatedly arranged on the substrate S. Figure 4 As shown, the substrate S includes a first region R1, a second region R2 and a plurality of regions R, each region R includes an 8TDP-SRAM storage unit that is the same as the first region R1 or the second region R2. Figure 4 Since the focus is on describing the relationship between the region and the fin structure, only the fin structure F1 to the fin structure F6 are drawn, and the other elements are omitted. Figure 4 It is found that the fin structure (F1 or F4) included in the pull-down transistor (PD1 or PD2) and the parasitic transistor (PT1 or PT2) extends to different regions (including the first region R1, the second region R2 and multiple regions R) along the second direction. In other words, the fin structure F1 and the fin structure F4 are continuous and will not be truncated. In addition, in different regions, the fin structure F2 and the fin structure F5 included in the access transistor are also continuous and will not be truncated. Similarly, the active area (not shown) in the substrate S located below the fin structures F1, F2, F4, and F5 is also a continuous and uninterrupted structure in different regions.

[0087] Compared to the prior art, in order to isolate components in different regions, the fin structures between parasitic transistors in adjacent regions are usually separated (for example, cut by a photolithography step). In this embodiment, in adjacent regions, the fin structures between parasitic transistors are directly in contact and not cut, and then connected to the voltage source Vss (constantly off in the circuit), so as to reduce leakage current and improve the SRAM operation speed.

[0088] More specifically, according to the applicant's experimental results, the fin structure of the pull-down transistor (PD1 or PD2) is made into a continuous extension structure (not cut off between different regions), which can increase the operating voltage of the pull-down transistor and slightly reduce the turn-on current of the pull-down transistor (by about 5%). In this way, the difference between the turn-on current of the pull-down transistor and the turn-on current of the pull-up transistor can be reduced, thereby improving the write rate of the SRAM.

[0089] In summary, the present invention provides a layout pattern unit of a static random access memory (SRAM), which at least includes a first SRAM unit 10 in a first region R1, wherein the first SRAM unit 10 includes a plurality of fin structures F located on a substrate S, and a plurality of gate structures G located on the substrate S, wherein the plurality of gate G structures span the plurality of fin structures F to form a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A), a fourth access transistor (PG2B), and a first parasitic transistor (PT1) and a second parasitic transistor (PT2) located on the substrate S, wherein the first parasitic transistor PT1 and the first pull-down transistor PD1 span the same fin structure F1, and the fin structure F1 spanned by the first parasitic transistor PT1 and the first pull-down transistor PD1 is a continuous structure.

[0090] In some embodiments of the present invention, a source of the first parasitic transistor PT1 is connected to a gate and is also connected to a source of the first pull-down transistor PD1 (eg, Figure 1 shown).

[0091] In some embodiments of the present invention, the source and gate of the first parasitic transistor PT1 and the source of the first pull-down transistor PD1 are also connected to a Vss voltage source (eg, Figure 1 shown).

[0092] In some embodiments of the present invention, the multiple gate structures include a first gate structure G1, a second gate structure G2, a third gate structure G3, and a fourth gate structure G4, wherein the first pull-down transistor PD1 includes the first gate structure G1, the second access transistor PG1B includes the second gate structure G2, the first access transistor PG1A includes the third gate structure G3, and the first parasitic transistor PT1 includes the fourth gate structure G4.

[0093] In some embodiments of the present invention, it also includes: a first metal layer MD1, electrically connected to a source of the first pull-down transistor PD1, a second metal layer MD2, electrically connected to a source of the second access transistor PG1B, a third metal layer MD3, electrically connected to a source of the first access transistor PG1A, and a fourth metal layer MD4, electrically connected to a source of the first parasitic transistor.

[0094] In some embodiments of the present invention, a distance between the first metal layer MD1 and the second metal layer MD2 in a lateral direction (X direction) is equal to a distance between the third metal layer MD3 and the fourth metal layer MD4 in the lateral direction.

[0095] In some embodiments of the present invention, the distance in the lateral direction from the second metal layer MD2 to the fin structure F1 spanned by the first parasitic transistor PT1 and the first pull-down transistor PD1 is equal to the distance in the lateral direction from the third metal layer MD3 to the fin structure F1 spanned by the first parasitic transistor PT1 and the first pull-down transistor PD1.

[0096] In some embodiments of the present invention, the second metal layer MD2 and the third metal layer MD3 are equal in area and size.

[0097] In some embodiments of the present invention, the first metal layer MD1 and the fourth metal layer MD4 are aligned in a longitudinal direction (Y direction), and the second metal layer MD2 and the third metal layer MD3 are aligned in the longitudinal direction.

[0098] In some embodiments of the present invention, the first metal layer MD1 is also electrically connected to a Vss voltage source, the second metal layer MD2 is also electrically connected to a bit line BL2, the third metal layer MD3 is also electrically connected to another bit line BL1, and the fourth metal layer MD4 is also electrically connected to the Vss voltage source.

[0099] Some embodiments of the present invention further include a fifth metal layer 65 . The fifth metal layer 65 is connected to and directly contacts the fourth metal layer MD4 and the fourth gate structure G4 , and is arranged along a longitudinal direction (Y direction).

[0100] In some embodiments of the present invention, a second region R2 is adjacent to the first region R1 and includes another SRAM cell, wherein the SRAM cell in the second region R2 and the SRAM cell in the first region R1 are arranged in a mirror-like manner.

[0101] In some embodiments of the present invention, the fifth metal layer 65 is further connected to a parasitic transistor in the second region R2 (ie, a first parasitic transistor in the second region R2 ).

[0102] In some embodiments of the present invention, the fin structure F1 crossed by the first parasitic transistor PT1 and the first pull-down transistor PD1 extends into the second region R2 and is a continuous structure.

[0103] In some embodiments of the present invention, the first pull-up transistor PU1 crosses the fin structure F3, and the fin structure F3 crossed by the first pull-up transistor PU1 does not extend into the second region R2 (eg, Figure 3 As shown, the fin structure F3 is cut off when it extends to near the boundary of the second region R2).

[0104] In some embodiments of the present invention, a substrate S further includes a plurality of regions R, each of the plurality of regions includes an SRAM cell, wherein a first region R1, a second region R2, and the plurality of regions R are arranged in the same direction, and a fin structure F1 spanned by a first parasitic transistor PT1 and a first pull-down transistor PD1 extends into the first region R1, the second region R2, and the plurality of regions R, and is not cut off.

[0105] In some embodiments of the present invention, an active region is further included under the fin structure F1 crossed by the first parasitic transistor PT1 and the first pull-down transistor PD1 , and the active region extends to the first region R1 , the second region R2 and the plurality of regions R and is not cut off.

[0106] In some embodiments of the present invention, from a top view, the first pull-up transistor PU1, the first pull-down transistor PD1 and the second access transistor PG1B are aligned along a lateral direction (X direction), and the first access transistor PG1A and the first parasitic transistor PT1 are aligned along the lateral direction.

[0107] In some embodiments of the present invention, from a top view, the first pull-down transistor PD1 and the first parasitic transistor PT1 are aligned along a longitudinal direction (Y direction), and the longitudinal direction is perpendicular to the lateral direction.

[0108] In some embodiments of the present invention, the number of fin structures spanned by the first pull-down transistor PD1 and the first parasitic transistor PT1 is equal (in terms of Figure 2 For example, there are 4 of them, but the present invention is not limited to this).

[0109] The present invention is characterized in that it provides an improved static random access memory (SRAM) layout pattern, which differs from the existing static random access memory pattern in that the fin structure included in the pull-down transistor is a continuous and uninterrupted structure between different regions, so that a parasitic transistor can be formed in conjunction with a gate structure. The applicant has found that forming a parasitic transistor helps to reduce the turn-on current of the pull-down transistor, thereby reducing the difference between the turn-on current of the pull-down transistor and the turn-on current of the pull-up transistor, thereby increasing the operating rate of the SRAM. In addition, forming a parasitic transistor can also reduce the probability of leakage current and improve component quality.

[0110] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A layout pattern unit of a static random access memory (SRAM), comprising at least: The first region includes a first static random access memory unit, and the first static random access memory unit includes: A plurality of fin-like structures are located on a substrate; A plurality of gate structures are located on the substrate, wherein the plurality of gate structures span the plurality of fin structures to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, and a first parasitic transistor and a second parasitic transistor located on the substrate; The first parasitic transistor and the first pull-down transistor cross over the same fin structure, and the fin structure crossed by the first parasitic transistor and the first pull-down transistor is a continuous structure. 2 . The layout pattern unit of the static random access memory as claimed in claim 1 , wherein a source of the first parasitic transistor is connected to a gate and is also connected to a source of the first pull-down transistor. 3 . The layout pattern unit of the static random access memory as claimed in claim 2 , wherein the source and the gate of the first parasitic transistor, and the source of the first pull-down transistor are further connected to a Vss voltage source.

4. The layout pattern unit of the static random access memory as described in claim 1, wherein the plurality of gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein the first pull-down transistor includes the first gate structure, the second access transistor includes the second gate structure, the first access transistor includes the third gate structure, and the first parasitic transistor includes the fourth gate structure.

5. The layout pattern unit of the static random access memory as claimed in claim 4, further comprising: a first metal layer electrically connected to a source of the first pull-down transistor; a second metal layer electrically connected to a source of the second access transistor; a third metal layer electrically connected to a source of the first access transistor; as well as The fourth metal layer is electrically connected to the source of the first parasitic transistor. 6 . The layout pattern unit of the static random access memory as claimed in claim 5 , wherein the distance between the first metal layer and the second metal layer in the lateral direction is equal to the distance between the third metal layer and the fourth metal layer in the lateral direction.

7. The layout pattern unit of a static random access memory as described in claim 5, wherein the distance from the second metal layer to the fin structure crossed by the first parasitic transistor and the first pull-down transistor in the lateral direction is equal to the distance from the third metal layer to the fin structure crossed by the first parasitic transistor and the first pull-down transistor in the lateral direction. 8 . The layout pattern unit of a static random access memory as claimed in claim 5 , wherein the second metal layer and the third metal layer are equal in area and size. 9 . The layout pattern unit of the static random access memory as claimed in claim 6 , wherein the first metal layer and the fourth metal layer are aligned in a longitudinal direction, and the second metal layer and the third metal layer are aligned in the longitudinal direction.

10. The layout pattern unit of the static random access memory as claimed in claim 5, wherein the first metal layer is also electrically connected to a Vss voltage source, the second metal layer is also electrically connected to a bit line, the third metal layer is also electrically connected to another bit line, and the fourth metal layer is also electrically connected to the Vss voltage source. 11 . The layout pattern unit of the static random access memory as claimed in claim 5 , further comprising a fifth metal layer, the fifth metal layer is connected to and directly contacts the fourth metal layer and the fourth gate structure, and is arranged along a longitudinal direction.

12. The layout pattern unit of the static random access memory as described in claim 11, further comprising a second area adjacent to the first area, and the second area comprises another static random access memory cell, wherein the static random access memory cell in the second area and the static random access memory cell in the first area are arranged in a mirror image with each other. 13 . The layout pattern unit of a static random access memory as claimed in claim 12 , wherein the fifth metal layer is further connected to a parasitic transistor in the second region. 14 . The layout pattern unit of a static random access memory as claimed in claim 12 , wherein the fin structure crossed by the first parasitic transistor and the first pull-down transistor extends into the second region and is a continuous structure. 15 . The layout pattern unit of the static random access memory as claimed in claim 12 , wherein the first pull-up transistor crosses over a fin structure of the plurality of fin structures, and the fin structure crossed by the first pull-up transistor does not extend into the second region.

16. The layout pattern unit of the static random access memory as described in claim 12, wherein the substrate further includes a plurality of regions, each of the plurality of regions includes a static random access memory unit, wherein the first region, the second region, and the plurality of regions are arranged along the same direction, and the fin structure crossed by the first parasitic transistor and the first pull-down transistor extends into the first region, the second region, and the plurality of regions and is not cut off.

17. The layout pattern unit of the static random access memory as claimed in claim 16, further comprising an active region located below the fin structure crossed by the first parasitic transistor and the first pull-down transistor, and the active region extends into the first region, the second region and the plurality of regions and is not cut off.

18. The layout pattern unit of the static random access memory as claimed in claim 1, wherein from a top view, the first pull-up transistor, the first pull-down transistor and the second access transistor are aligned along a lateral direction, and the first access transistor and the first parasitic transistor are aligned along the lateral direction. 19 . The layout pattern unit of the static random access memory as claimed in claim 18 , wherein from a top view, the first pull-down transistor and the first parasitic transistor are aligned along a longitudinal direction, and the longitudinal direction is perpendicular to the lateral direction. 20 . The layout pattern unit of a static random access memory as claimed in claim 1 , wherein the first pull-down transistor and the first parasitic transistor cross an equal number of the fin structures.

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