Non-volatile memory element

Abstract

A non-volatile memory device includes at least one memory cell including a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is disposed in the substrate. The erase gate is disposed in the trench and includes a recessed angle. The control gate electrode is arranged on the substrate, and the bottom surface of the control gate electrode is higher than the bottom surface of the erasing gate electrode. The floating gate is disposed on the substrate, and the floating gate includes a lower tip pointing to a recessed corner of the erase gate, and the lower tip extends beyond a sidewall of the trench.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and more particularly to a non-volatile memory device. Background Art

[0002] Since non-volatile memory can repeatedly perform operations such as storing, reading and erasing data, and the stored data will not be lost after the non-volatile memory is turned off, non-volatile memory has been widely used in personal computers and electronic devices.

[0003] The structure of the existing non-volatile memory has a stacked gate structure, including a tunneling oxide layer, a floating gate, a coupling dielectric layer and a control gate sequentially arranged on a substrate. When programming or erasing operations are performed on such a flash memory element, appropriate voltages are applied to the source region, the drain region and the control gate, respectively, so that electrons are injected into the floating gate or pulled out of the floating gate.

[0004] In the programming and erasing operations of non-volatile memory, a larger gate-coupling ratio (GCR) between the floating gate and the control gate usually means a lower operating voltage required for operation, thus significantly improving the operating speed and efficiency of the flash memory. However, during the programming or erasing operation, electrons must flow through the tunnel oxide layer disposed under the floating gate to be injected into the floating gate or pulled out of the floating gate. This process usually damages the structure of the tunnel oxide layer, thereby reducing the reliability of the memory device.

[0005] In order to improve the reliability of the memory element, an erase gate can be used and integrated into the memory element. By applying a positive voltage to the erase gate, the erase gate can pull electrons out of the floating gate. Therefore, since the electrons in the floating gate are pulled out by flowing through the tunnel oxide layer set on the floating gate, rather than flowing through the tunnel oxide layer set under the floating gate, the reliability of the memory element is further improved.

[0006] The memory device is usually integrated with logic devices, such as transistors with a planar gate structure, and fabricated on the same wafer. The memory device is usually taller than the logic device because the memory device includes a stacked gate structure including a select gate and an erase gate.

[0007] During the manufacturing process of the middle-end-of-line (MEOL) structure, a blanket ILD layer is formed to cover both the logic element and the memory element. Usually, after the planarization process is performed on the ILD layer, the ILD layer above the memory element is thinner than the ILD layer above the logic element due to the stacked gate structure in the memory element.

[0008] In order to further miniaturize the line width of all contact plugs formed in the ILD layer, it is necessary to reduce the thickness of the ILD layer covering the logic elements and the memory elements. However, if the ILD layer above the memory element becomes too thin, it may cause undesirable electrical coupling between the memory element and the interconnection located thereon, thereby adversely affecting the electrical performance of the memory element.

[0009] Therefore, there is a need for further improvement in the structural design of memory devices. Summary of the invention

[0010] An object of the present invention is to provide a highly reduced non-volatile memory element suitable for integration into a logic device.

[0011] According to some embodiments, the present invention provides a non-volatile memory element, including at least one memory cell, the memory cell including a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is located in the substrate. The erase gate is located in the trench and includes a concave corner. The control gate is located on the substrate, and the bottom surface of the control gate is higher than the bottom surface of the erase gate. The floating gate is located on the substrate, and the floating gate includes a lower tip, pointing to the concave corner of the erase gate, and extending beyond the sidewall of the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The purpose of the following drawings is to make the present invention more easily understood, and these drawings will be incorporated into and constitute a part of the specification. The drawings illustrate embodiments of the present invention, and together with the sections of the implementation methods, they are used to explain the working principle of the invention.

[0013] Figure 1 FIG. 4 is a schematic top view of a non-volatile memory device according to some embodiments of the present invention.

[0014] Figure 2 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line AA′ is shown.

[0015] Figure 3 For the corresponding Figure 2 An enlarged cross-sectional schematic diagram of region R1.

[0016] Figure 4 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line BB′ is shown.

[0017] Figure 5 According to another embodiment of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line BB′ is shown.

[0018] Figure 6 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line CC' is shown.

[0019] Figure 7 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention.

[0020] Figure 8 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention.

[0021] Fig. 9 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to yet another embodiment of the present invention.

[0022] Figures 10 to 15 Schematic cross-sectional views of different stages in a manufacturing process of a non-volatile memory device according to some embodiments of the present invention.

[0023] Fig.16 Schematic cross-sectional views of different stages in a manufacturing process of a non-volatile memory device according to another embodiment of the present invention.

[0024] Description of reference numerals: 100_1, 100_2, 100_3-non-volatile memory element; 102-isolation structure; 103-active region; 110-first memory cell region; 112-second memory cell region; 114-third memory cell region; 116-fourth memory cell region; 200-substrate; 202-select gate dielectric layer; 204-select gate; 208-insulating layer; 212-dielectric spacer; 218-floating gate dielectric layer; 220-end; 222-source region; 224-floating gate; 224_1-vertical portion; 224_2-horizontal portion; 224_3-lower tip; 224a-first sidewall; 224b-second Sidewall; 226-groove; 226a-sidewall; 226b, 240b, 236b, 224d, 224c-bottom surface; 234-erase gate dielectric layer; 234_1-lower section; 234_2-upper section; 236-erase gate; 236a, 204a, 225, 225_2, 225_1, 240a-top surface; 237-erase gate layer; 238-coupling dielectric layer; 239-recessed corner; 240-control gate; 244-drain region; 246-select gate layer; 248-top etching mask; 249, 252-self-aligned etching mask; 250-dielectric layer; 254-filling layer; 260-floating gate layer; R1-region. DETAILED DESCRIPTION

[0025] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0026] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "below", "above", "upper", "lower", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the possible swing direction of the semiconductor device during use and operation. As the swing direction of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its swing direction should also be interpreted in a similar manner.

[0027] Although the invention of the present invention is described below through specific embodiments, the inventive principle of the present invention is defined by the claims and can be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians with common knowledge in the relevant technical field.

[0028] Figure 1 is a schematic top view of a non-volatile memory element according to some embodiments of the present invention. Figure 1 , the non-volatile memory element 100_1 may be a NOR flash memory element, which includes at least one memory cell, for example, four memory cells respectively accommodated in a first memory cell area 110, a second memory cell area 112, a third memory cell area 114, and a fourth memory cell area 116. The structures in the first memory area 110 and the second memory cell area 112 are mirror images of each other, and the structures in the third memory cell area 114 and the fourth memory cell area 116 are mirror images of each other. According to an embodiment of the present invention, the non-volatile memory element 100_1 includes more than four memory cells, and these memory cells may be arranged in an array having many rows and columns.

[0029] See also Figure 1 The non-volatile memory element includes a substrate 200 and an isolation structure 102. The substrate 200 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator substrate (SOI), but is not limited thereto. The isolation structure 102 may be made of an insulating material and is used to define an active region 103 of a memory cell.

[0030] Each memory cell includes a source region 222 and a drain region 244 disposed in an active region 103 defined by an isolation structure 102. The source region 222 and the drain region 244 may be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 244 is different from the conductivity type of the substrate 200, or different from the conductivity type of a doping well (not shown) used to accommodate the source region 222 and the drain region 244. The source region 222 may be disposed in one end of the active region 103 of each memory cell, and the drain region 244 may be disposed in the other end of the active region 103 of each memory cell. According to some embodiments of the present invention, the source region 222 is a continuous region extending along the Y direction, and is a common source shared by the memory cells arranged in the same row.

[0031] Each memory cell may further include a selection gate 204 disposed on the substrate 200 and adjacent to the drain region 244. The selection gate 204 may extend along the Y direction and be shared by the memory cells arranged in the same row. The selection gate 204 may be made of a conductive material such as polysilicon or metal, and the selection gate 204 may serve as a word line configured to turn on / off the corresponding channel region of the memory cells in the same row.

[0032] The dielectric spacer 212 may be disposed on the sidewall of the select gate 204 to insulate the select gate 204 from other conductive parts. The dielectric spacer 212 may be a single-layer, double-layer or multi-layer spacer disposed on each sidewall of the select gate 204, but is not limited thereto.

[0033] Each memory cell also includes a floating gate 224, which is disposed on the substrate 200 and adjacent to the source region 222. Therefore, the floating gate 224 is disposed on one side of the selection gate 204 and opposite to the drain 244 (i.e., the other side of the selection gate 204 is adjacent to the drain 244). The floating gate 224 is made of a conductive material such as polysilicon or other conductive semiconductors. The floating gates 224 are spaced apart from each other so that current is not directly transmitted between the floating gates 224. Each floating gate 224 may include two opposing first sidewalls 224a and two opposing second sidewalls 224b. The first sidewalls 224a are arranged along a first direction (i.e., the X direction), and the second sidewalls 224b are opposite to each other and arranged along a second direction (i.e., the Y direction) different from the first direction (i.e., the X direction).

[0034] Since the floating gates 224 are spaced apart from each other, each floating gate 224 can be independently programmed or erased, thereby determining the state of each memory cell, such as state "1" or state "0". As shown in the following cross-sectional view, Figure 2 , Figures 7 to 9Each floating gate 224 can be a strip-shaped structure, an L-shaped structure, or a structure with a curved sidewall. The detailed cross-sectional structure of the floating gate 224 is shown in FIG. Figure 2 , Figures 7 to 9 This is described in the description.

[0035] The floating gate dielectric layer 218 is at least located between the first sidewall 224a of the floating gate 224 and the select gate 204. The floating gate dielectric layer 218 also extends below the floating gate 224 so that hot electrons can be injected into the floating gate 224 during a programming operation. The floating gate dielectric layer 218 is made of, for example, silicon oxide or other materials.

[0036] During a programming operation, hot electrons are allowed to pass through the floating gate dielectric layer 218 and accumulate in the corresponding floating gate 224 .

[0037] See also Figure 1 , each memory cell also includes a control gate 240, which is disposed on the substrate 200 and extends along the Y direction. Three sidewalls of the floating gate 224 (i.e., a first sidewall 224a and two second sidewalls 224b) may be covered by the control gate 240. The control gate 240 is located in the gap between the opposite selection gates 204 and extends along the Y direction. The control gate 240 may be shared by a pair of memory cells arranged in the same column. For example, the control gate 240 may be shared by memory cells respectively accommodated in the first memory cell region 100 and the second memory cell region 120. In a top view, the control gate 240 may cover the continuous source region 222. The control gate 240 is made of a conductive material, such as polysilicon, metal or other conductive semiconductors, but is not limited thereto.

[0038] The purpose of the control gate 240 is to allow hot carriers (e.g., electrons) to be injected from the channel into the floating gate 224. For example, when a suitable positive voltage is applied to the control gate 240, hot carriers (e.g., electrons) transported in the carrier channel below the floating gate 224 can be injected and accumulated in the corresponding floating gate 224.

[0039] A coupling dielectric layer 238 is disposed between the control gate 240 and the floating gate 224. Therefore, the sidewall of the select gate 204 facing the control gate 240 may be covered by the coupling dielectric layer 238. Three sidewalls (i.e., one first sidewall 224a and two second sidewalls 224b) of each floating gate 224 may also be covered by the coupling dielectric layer 238. The coupling dielectric layer 238 may be a single dielectric layer including silicon oxide or silicon oxynitride, or a composite dielectric layer including silicon oxide / silicon nitride / silicon oxide, but is not limited thereto.

[0040] The non-volatile memory device 100_1 further includes an erase gate 236 extending along the Y direction. The erase gate 236 may be a continuous layer located in a recess (not shown) formed in the substrate 200. Therefore, when viewed from a top-down view, the erase gate 236 is covered by both the control gate 240 and the floating gate 224. In addition, the erase gate 236 is laterally separated from the select gate 204, and when viewed from a top-down view, the erase gate 236 does not overlap with the select gate 204. During an erase operation of the non-volatile memory device 100_1, the erase gate 236 is biased, causing the electrons stored in the floating gate 224 to be pulled out primarily through the lower tip (not shown) of the floating gate 224.

[0041] Figure 2 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line AA′ is shown. Figure 2 The configuration shown in the figure includes a first memory cell and a second memory cell, which are respectively accommodated in a first memory cell region 110 and a second memory cell region 112. The first memory cell region 110 and the second memory cell region 112 each include at least an erase gate 236, a control gate 240 and a floating gate 224. The source region 222 is shared by the first memory cell region 110 and the second memory cell region 112. In some embodiments, the first memory cell and the second memory cell are mirror images of each other.

[0042] See also Figure 2 , the non-volatile memory element includes a trench 226 located in the substrate 200. The trench 226 extends along the second direction (ie, the Y direction) and is used to accommodate the erase gate 236. The source region 222 is in direct contact with the trench 226 and is disposed along the sidewall 226a and the bottom surface 226b of the trench 226. When, for example, Figure 1 When viewed from above, the source region 222 and the trench 226 may extend in the same direction (ie, the Y direction).

[0043] The erase gate dielectric layer 234 is a conformal layer disposed on the inner surface of the trench 226. In other words, the erase gate dielectric layer 234 is disposed on the sidewall 226a and the bottom surface 226b of the trench 226. The erase gate dielectric layer 234 is disposed between the lower tip 224_3 of the floating gate 224 and the erase gate 236, and is made of a dielectric layer, which allows the electrons originally stored in the floating gate 224 to penetrate therein due to the Fowler-Nordheim (FN) tunneling mechanism.

[0044] The erase gate 236 is located in the trench 226, and the top surface of the erase gate 236 is higher than the top surface of the substrate 200. The erase gate 236 includes a concave corner 239, which is formed corresponding to the lower tip 224_3 of the floating gate 224. The lower tip 224_3 of the floating gate 224 can extend beyond the sidewall 226a of the trench 226 and point to the concave corner 239 of the erase gate 236. Under this configuration, it can be seen that the lower tip 224_3 of the floating gate 224 is partially covered by the concave corner 239 of the erase gate 236. Due to the presence of the lower tip 224_3, during the erase operation of the non-volatile memory device 100_1, the erase gate 236 can be biased to allow the electrons originally stored in the floating gate 224 to be more effectively pulled out through the lower tip 224_3.

[0045] The control gate 240 covers the top surface 236a of the erase gate 236, and the bottom surface 240b of the control gate 240 is higher than the bottom surface 236b of the erase gate 236. The control gate 240 is separated from the erase gate 236 thereunder by a coupling dielectric layer 238.

[0046] The coupling dielectric layer 238 is a continuous layer extending from below the control gate 240 to a region between the control gate 240 and the floating gate 224. Therefore, a portion of the coupling dielectric layer 238 is disposed between the top surface 236a of the erase gate 236 and the bottom surface 240b of the control gate 240.

[0047] The floating gate dielectric layer 218 is initially an L-shaped structure including a vertical portion and a horizontal portion. The vertical portion of the floating gate dielectric layer 218 is disposed between the floating gate 224 and the select gate 204 , while the horizontal portion of the floating gate dielectric layer 218 is disposed between the floating gate 224 and the substrate 200 .

[0048] The select gate 204 is laterally separated from the erase gate 236 and the control gate 240. In this embodiment, a top surface 204a of the select gate 204 is higher than a top surface 236a of the erase gate 236. The select gate 204 may be made of a conductive material such as polysilicon or metal, and the select gate 204 may serve as a word line configured to turn on / off channel regions of a plurality of memory cells in the same row.

[0049] The select gate dielectric layer 202 is disposed between the select gate 204 and the substrate 200 , and the select gate dielectric layer 202 and the select gate 204 are components of the select gate structure.

[0050] Still see Figure 2During the manufacturing of the non-volatile memory device, a planarization process may be performed on the select gate 204, the control gate 240, and the floating gate 224. Therefore, the top surface 204a of the select gate 204 and the top surface 225 of the floating gate 224 are substantially flush with each other.

[0051] Figure 3 For the corresponding Figure 2 See FIG. Figure 3 In the region R1, the lower tip 224_3 of the floating gate 224 pointing to the concave corner 239 of the erase gate 236 is located above the trench 226. The lower tip 224_3 and the erase gate 236 are separated by the erase gate dielectric layer 234. Specifically, the bottom surface 224d and the sidewall (i.e., the lower portion of the first sidewall 224a) of the lower tip 224_3 are in direct contact with the erase gate dielectric layer 234. The erase gate dielectric layer 234 may be conformal to the shape of the lower tip.

[0052] The coupling dielectric layer 238 is located above the erase gate dielectric layer 234 and the erase gate 236. Specifically, a portion of the coupling dielectric layer 238 is sandwiched between the top surface 236a of the erase gate 236 and the bottom surface 240b of the control gate 240.

[0053] The floating gate dielectric layer 218 is disposed between the floating gate 224 and the substrate 200 , and an end portion 220 of the floating gate dielectric layer 218 is in direct contact with the erase gate dielectric layer 234 . Figure 3 The edge of the end portion 220 shown in the figure is substantially aligned with the sidewall 226a of the trench 226, but the edge of the end portion 220 may not be aligned with the sidewall 226a. In this example, a portion of the erase gate dielectric layer 234 may be filled in the gap between the floating gate 224 and the substrate 200.

[0054] In some embodiments, the bottom surface 224c of the floating gate 224 is higher than the bottom surface of the erase gate 236. The top surface 225 of the floating gate 224 is higher than the top surface 236a of the erase gate 236 and is flush with the top surface 240a of the control gate 240. Since the top surface 225 of the floating gate 224 does not overlap with the top surface 240a of the control gate 240, the contacts (also called contact plugs) formed in subsequent processes and respectively located on the floating gate 224 and the control gate 240 can have the same height. The thickness of the floating gate 224 is greater than the thickness of the control gate 240.

[0055] Figure 4 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the line BB′ is shown. Figure 5FIG. 1 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention corresponding to the section line BB' in FIG. Figure 4 , the select gate 204 is disposed on the isolation structure 102 . The trench 226 and the source region 222 are disposed in the substrate 200 between two adjacent portions of the isolation structure 102 .

[0056] A major portion of the erase gate dielectric layer 234 is disposed in the trench 226. A minor portion of the erase gate dielectric layer 234 may extend out of the trench 226 (eg, Figure 4 ) or limited to the space above the groove 226, the width of which is approximately equal to or less than the width of the groove 226 (as shown in Figure 5 See Figure 4 , the portion of the erase gate dielectric layer 234 outside the trench 226 may cover the top surface of the isolation structure 102 and the sidewalls of the select gate 204. Figure 4 and Figure 5 For both structures shown, the bottom surface 240 b of the control gate 240 is higher than the bottom surface 236 b of the erase gate 236 .

[0057] The erase gate 236 is filled in the trench 226 and extends outward to partially cover the top surface of the isolation structure 102 .

[0058] The control gate 240 and the coupling dielectric layer 238 may extend between two adjacent select gates 204 and partially cover the top surface of the isolation structure 102 .

[0059] Figure 6 According to some embodiments of the present invention, Figure 1 The cross-sectional view of the non-volatile memory device taken along the section line CC' is shown. Figure 6 The erase gate dielectric layer 234 includes a lower section 234_1 and an upper section 234_2, and the lower section 234_1 and the upper section 234_2 are vertically separated from each other by the erase gate 236. Specifically, the lower section 234_1 of the erase gate dielectric layer 234 is located between the source region 222 and the erase gate 236, and the upper section 234_2 of the erase gate dielectric layer 234 is located between the floating gate 224 (also referred to as the lower tip 224_3 of the floating gate 224) and the erase gate 236. The upper section 234_2 of the erase gate dielectric layer 234 covers the bottom surface and the lower portion of the sidewall 224b of the lower tip 224_3.

[0060] The coupling dielectric layer 238 is located above the upper section 234_2 of the erase gate dielectric layer 234 and extends continuously along the Y direction. The coupling dielectric layer 238 covers the upper portion of the sidewall 224 b of the lower tip 224_3 .

[0061] Figure 7 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention. Figure 7 The structure shown in Figure 2 The structure shown in FIG. 1 is similar to that shown in FIG. 1 , with the main difference being the shape of the floating gate 224. Figure 7 In the non-volatile memory device 100_2 shown, the floating gate 224 is not in a strip shape, but in an L shape, and includes a vertical portion 224_1 and a horizontal portion 224_2. The vertical portion 224_1 and the control gate 240 and the select gate 204 are laterally separated. The horizontal portion 224_2 is located below the control gate 240 and includes a lower tip 224_3. The top surface 225_2 of the horizontal portion 224_2 is lower than the top surface 225_1 of the vertical portion 224_1. Due to the existence of the vertical portion 224_1, the top surface of the vertical portion 224_1 of the floating gate 224 can be substantially flush with the top surfaces of both the control gate 240 and the select gate 204.

[0062] Figure 8 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention. Figure 8 The structure shown in Figure 7 The structure shown in FIG. 1 is similar to that shown in FIG. 1 , with the main difference being the shape and relative position of the erase gate 236 and the control gate 240. Specifically, in FIG. Figure 8 In the embodiment, the top surface of the erase gate 236 is higher than the bottom surface of the horizontal portion 224_2 of the floating gate 224 and is substantially flush with the top surface of the select gate 204. In addition, a pair of control gates 240 are separated by the upper portion of the erase gate 236, which is located above the trench 226.

[0063] like Figure 7 and Figure 8 As shown in FIG. 1 , the top surface of the erase gate 236 may be lower than the top surface 225_2 of the horizontal portion 224_2 of the floating gate 224 (eg, Figure 7 ), or may be higher than the top surface 225_2 of the horizontal portion 224_2 of the floating gate 224 (as shown in FIG. Figure 8 shown).

[0064] Fig. 9 FIG. 4 is a schematic cross-sectional view of a non-volatile memory device according to yet another embodiment of the present invention. Fig. 9 The structure shown in Figure 2 The structure shown in FIG. 1 is similar to that shown in FIG. 1 , with the main difference being the shape of the floating gate 224. Fig. 9 In the non-volatile memory device 100_3 shown, the first sidewall 224 a of the floating gate 224 facing the control gate 240 is an arc-shaped sidewall rather than a vertical surface or an inclined surface, and the upper portion of the first sidewall 224 a is covered by the control gate 240 .

[0065] Similarly, the top surface 225 of the floating gate 224 may be substantially flush with the top surfaces 240 a and 204 a of both the control gate 240 and the select gate 204 .

[0066] Figures 10 to 15 In some embodiments of the present invention, a non-volatile memory element (such as Figure 1-Figure 4 and Figure 6 Schematic cross-section of different stages in the manufacture of the Figures 10 to 15 In the diagram, view AA' corresponds to Figure 1 The section line A-A'.

[0067] See also Fig.10 In step 801, a substrate 200 is provided. According to some embodiments of the present invention, the substrate 200 may be a semiconductor substrate with a suitable conductivity type (such as p-type or n-type). The composition of the substrate 200 may include silicon, germanium, gallium nitride or other suitable semiconductor materials, but is not limited thereto.

[0068] At least one stack structure 300 is disposed on the substrate 200. For example, there are two stack structures 300 disposed on the substrate 200, which are laterally separated from each other. One of the stack structures 300 is disposed in the first memory cell region 110, and the other stack structure 300 is disposed in the second memory cell region 112. Each stack structure 300 includes a select gate dielectric layer 202, a select gate layer 246, an insulating layer 208, and a top etching mask 248. The top etching mask 248 is a patterned etching mask used to define the shapes of the layers below (e.g., the select gate dielectric layer 202 and the select gate layer 246).

[0069] Next, a dielectric layer 250 is conformally deposited on the stacked structure 300 and the substrate 200 . The thickness of the dielectric layer 250 is smaller than the thickness of the select gate layer 246 .

[0070] After the dielectric layer 250 is formed, two self-aligned etching masks 249 are formed on the sidewalls of the stacked structure 300. The two self-aligned etching masks 249 are laterally separated from each other to expose a portion of the dielectric layer 250 between the two self-aligned etching masks 249. The self-aligned etching masks 249, which may be made of a dielectric material such as nitride, oxide, or oxynitride, form a strip extending along the Y direction in a top view.

[0071] Then, in step 802, by using the top etching mask 248 and the self-aligned etching mask 249 as etching masks, an etching process is performed to etch the portion of the substrate 200 located between the two self-aligned etching masks 249. Therefore, a trench 226 laterally separated from the selection gate layer 246 is formed in the substrate 200. The depth of the trench 226 can be adjusted according to actual needs.

[0072] Next, a source region 222 is formed along the sidewall 226a and the bottom surface 226b of the trench 226. The method for forming the source region 222 includes, for example, performing an ion implantation process. The implanted dopant may be n-type or p-type, depending on the device design. The dopant and doping concentration of the source region 222 may be adjusted according to actual needs.

[0073] See also Fig.11 In step 803, a filling layer 254 is deposited to cover the stacked structure 300 and the self-aligned etching mask 249. A portion of the filling layer 254 is filled into the trench 226. A planarization process may be selectively performed on the filling layer 254 until the filling layer 254 has a substantially flat top surface. The filling layer 254 may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0074] Then, in step 804, an etch-back process is performed on the filling layer 254 to remove the portion of the filling layer 254 located above the stacked structure 300 and the self-aligned etching mask 249. When the etch-back process is completed, the trench 226 is still filled with the filling layer 254, and the top surface of the filling layer 254 may be higher than the top surface of the substrate 200 and substantially flush with the bottom surface of the self-aligned etching mask 249.

[0075] In such Fig.11 After the steps shown, the top etch mask 248, the self-aligned etch mask 249, and the dielectric layer 250 may be further removed.

[0076] See also Fig.12 In step 805, a floating gate dielectric layer 218 is formed on the substrate 200 to conformally cover the stacked structure 300 and the filling layer 254. The floating gate dielectric layer 218 may be a single dielectric layer including silicon oxide or silicon oxynitride, or a composite dielectric layer including silicon oxide / silicon nitride / silicon oxide, but not limited thereto. Next, a floating gate layer 260 is deposited on the floating gate dielectric layer 218. The thickness of the floating gate layer 260 may be appropriately controlled so that the floating gate layer 260 may conform to the shape of the underlying structure. The floating gate layer 260 may be made of a conductive material such as polysilicon or metal, but not limited thereto.

[0077] The floating gate layer 260 may be further patterned to become a structure including a plurality of stripe patterns, each of which extends along the X direction in a top view.

[0078] After the floating gate layer 260 including a plurality of strip patterns is formed, two self-aligned etching masks 252 are formed on the vertical surface of the floating gate layer 260. The etching masks 252 can be made of a dielectric material, such as silicon oxide, silicon nitride or oxynitride, but are not limited to these materials. The two self-aligned etching masks 252 are laterally separated from each other to expose a portion of the floating gate layer 260 between the two self-aligned etching masks 252. The self-aligned etching mask 252 is a strip structure extending along the Y direction in a top view. The width of the etching mask 252 and the thickness of the floating gate layer 260 can be adjusted to ensure that the floating gate edge (described below) extends beyond the trench sidewall 226a.

[0079] As described above, in step 806, an etching process is performed by using the self-aligned etching mask 252 as an etching mask to etch a portion of the floating gate layer 260. As a result, a floating gate 224 including a vertical portion 224_1 and a horizontal portion 224_2 is obtained. The horizontal portion 224_2 of the floating gate 224 includes a lower tip 224_3 located above the trench 226 and extending beyond the trench sidewall 226a. The floating gate 224 is a self-aligned structure, thereby eliminating the need for a photolithography etching process for defining the position of the floating gate 224. Two floating gates 224 can be formed in the first memory cell region 110 and the second memory cell region 112, respectively, and can be laterally separated from each other in the X direction.

[0080] In addition, during the process of forming the floating gate 224, the portion of the floating gate dielectric layer 218 located above the select gate layer 246 and the filling layer 254 may be removed. Therefore, the insulating layer 208 located on the select gate layer 246 may be exposed or even completely removed, and the filling layer 254 may be partially etched to include a recess 256.

[0081] Then, the filling layer 254 and the portion of the floating gate dielectric layer 218 covering the bottom surface of the lower tip 224_3 can be further removed, thereby exposing the bottom surface of the lower tip 224_3. The self-aligned etching mask 252 can be removed later, or in another embodiment, the self-aligned etching mask 252 remains in place during the removal of the filling layer 254. The remaining self-aligned etching mask 252 can be used to confine the subsequently deposited erase gate dielectric layer 234 to the space above the trench 226, and its width is approximately equal to or less than the width of the trench 226.

[0082] See also Fig.13In step 807, an erase gate dielectric layer 234 is conformally formed to cover the select gate layer 246, the floating gate 224, the bottom surface of the lower tip 224_3, and the sidewalls 226a and the bottom surface 226b (also referred to as the inner surface) of the trench 226. The thickness of the erase gate dielectric layer 234 is less than the thickness of the floating gate 224. Next, an erase gate layer 237 is deposited to cover the stacked structure 300 and the floating gate 224. A portion of the erase gate layer 237 is filled into the trench 226. Due to the presence of the lower tip 224_3 of the floating gate 224, the erase gate layer 237 may have a concave angle 239, which corresponds to the position of the lower tip 224_3. An optional planarization process may be performed on the erase gate layer 237 until the erase gate layer 237 has a substantially flat top surface. The erase gate layer 237 may be made of a conductive material, such as polysilicon or metal, but is not limited thereto.

[0083] Next, in step 808, an etch-back process is performed on the erase gate layer 237 to remove the portion of the erase gate layer 237 located above the select gate 204 and the floating gate 224. When the etch-back process is completed, the erase gate 236 can be obtained. The erase gate 236 is filled in the trench 226, and the top surface of the erase gate 236 is higher than the bottom surface of the horizontal portion 224_2. According to the shape of the floating gate 224, its shape can be a spacer shape, an L shape, or a strip shape, and the top surface of the erase gate 236 can be lower or higher than the top surface of the horizontal portion 224_2. Therefore, the sidewall of the horizontal portion 224_2 can be partially covered by the erase gate 236.

[0084] Next, an etching process is performed to remove the erase gate dielectric layer 234 located above the select gate layer 246 and the floating gate 224 .

[0085] After step 808 is completed, the lower tip 224_3 of the floating gate 224 may be covered by the erase gate 236 and the erase gate dielectric layer 234 .

[0086] See also Fig.14 In step 809, a coupling dielectric layer 238 and a control gate 240 are formed to cover the horizontal portion 224_2 of the floating gate 224 and the erase gate 236. The upper sidewall of the horizontal portion 224_2 may be covered by the coupling dielectric layer 238 and the control gate 240. An optional planarization process may be performed on the select gate layer 246, the vertical portion 224_1 of the floating gate 224, and the control gate 240 until the select gate layer 246, the vertical portion 224_1, and the control gate 240 are flush with each other. The erase gate layer 237 may be made of a conductive material such as polysilicon or metal, but is not limited thereto.

[0087] Then, in step 810, the selection gate layer 246 may be patterned to form the selection gate 204. A dielectric spacer 212 is formed on the selection gate 204 to insulate the selection gate 204 from other conductive components. At least one drain region 244, for example, two drain regions 244, are formed on the side of the selection gate 204. The two drain regions 244 are respectively located in the first memory cell region 110 and the second memory cell region 112, and they may be electrically coupled to each other through vias or contacts in subsequent processes.

[0088] The formation method of the drain region 244 includes, for example, performing an ion implantation process. The implanted dopant may be n-type or p-type, depending on the device design. The dopant and doping concentration of the source region 222 and the drain region 244 may be the same or different.

[0089] Then, other electronic components can be manufactured by performing appropriate processes to obtain similar Figure 1 and Figure 7 A non-volatile memory element of the structure shown.

[0090] See also Fig.15 In step 811, in order to further reduce the height of the memory elements in the first memory cell region 110 and the second memory cell region 112, an additional planarization process may be performed on the select gate 204, the vertical portion 224_1 of the floating gate 224, and the control gate 240 until the coupling dielectric layer 238 located above the horizontal portion 224_2 of the floating gate 224 is exposed. When the planarization process is completed, almost all of the vertical portion 224_1 is removed.

[0091] In addition, the height of the memory elements in the first memory cell area 110 and the second memory cell area 112 can be further reduced to meet strict design requirements. In step 812, an additional planarization process can be performed on the select gate 204, the vertical portion 224_1 of the floating gate 224, and the control gate 240 until the coupling dielectric layer 238 located above the top surface of the horizontal portion 224_2 of the floating gate 224 is removed. When the planarization process is completed, the vertical portion 224_1 of the entire floating gate 224 is removed. Therefore, the select gate 204, the control gate 240, and the floating gate 224 are flush with each other.

[0092] Then, other electronic components can be manufactured by performing appropriate processes to obtain similar Figure 1-Figure 4 and Figure 6 A non-volatile memory element of the structure shown.

[0093] Fig.16 According to another embodiment of the present invention, Figure 1 and Figure 6Schematic cross-sectional views of different stages in the fabrication of a non-volatile memory device are shown. Fig.16 In the diagram, view AA' corresponds to Figure 1 The section line A-A'. Figure 10-15 Some processes of the embodiment shown in the figure can be replaced by Fig.16 The process shown or Fig.16 For the sake of simplicity, only the main differences between the embodiments are described below.

[0094] See also Fig.16 The manufacturing stage of step 813 is similar to the manufacturing stage of step 806, and the main difference is the shape of the floating gate 224. In step 813, the floating gate 224 is a self-aligned structure formed by etching a conductive layer (such as a floating gate layer). The floating gate 224 has an arc-shaped sidewall, an upper tip and a lower tip 224_3.

[0095] In forming similar Figure 13-14 After the erase gate dielectric layer 234 and the erase gate 236 are formed, in step 814, a coupling dielectric layer 238 is deposited to cover the arc-shaped sidewalls of the floating gate 224 and the top surface of the erase gate 236. Next, a control gate layer 260 is deposited to cover the coupling dielectric layer 238, and the control gate layer 260 may be further planarized to form a structure as shown in FIG. Fig. 9 A control gate 240 is shown.

[0096] Similar Figure 10-15 Other processes shown in order to obtain similar Fig. 9 A non-volatile memory element of the structure shown.

[0097] In some embodiments, see Figure 10-Figure 16 , a method for manufacturing a non-volatile memory device is provided, comprising the following steps: providing a substrate 200; forming a trench 226 in the substrate 200; forming a floating gate 224 on the substrate 200, wherein the floating gate 224 includes a lower tip 224_3 extending beyond the sidewall 226a of the trench 226; forming an erase gate dielectric layer 234, covering the lower tip 224_3 of the floating gate 224 and the sidewall 226a and bottom surface 226b of the trench 226; after forming the erase gate dielectric layer 234, forming an erase gate 236 in the trench 226; and forming a control gate 240 after forming the erase gate 236, wherein a bottom surface 240b of the control gate 240 is higher than a bottom surface 236b of the erase gate 236.

[0098] In some embodiments, see Figure 10-Figure 16The method for manufacturing a non-volatile memory device further includes: forming a select gate layer 246 that is laterally separated from the erase gate 236 and the floating gate 224; and planarizing a top surface 204a of the select gate layer 246, a top surface 240a of the control gate 240, and a top surface 225 of the floating gate 224 until the top surfaces of the select gate layer 246, the control gate 240, and the floating gate 224 are flush with each other.

[0099] In some embodiments, see Figure 10-Figure 16 The method for manufacturing the non-volatile memory device further includes: forming a filling layer 254 in the trench 226 before forming the floating gate 224 on the substrate 200; forming the floating gate 224 on the filling layer 254 when forming the floating gate 224 on the substrate 200; and exposing the bottom surface 224d of the lower tip 224_3 of the floating gate 224 before forming the erase gate dielectric layer 234.

[0100] In some embodiments, see Figure 10-Figure 16 In the above method for manufacturing a non-volatile memory device, before forming the erase gate 236 in the trench 226 , the bottom surface 224 d of the lower tip 224_3 of the floating gate 224 is covered by the erase gate dielectric layer 234 .

[0101] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A non-volatile memory device, comprising at least one memory unit, characterized in that: The at least one memory unit comprises: a substrate; a trench disposed in the substrate; an erase gate disposed in the trench, wherein the erase gate includes a concave corner; a control gate disposed on the substrate, wherein a bottom surface of the control gate is higher than a bottom surface of the erase gate; and A floating gate is disposed on the substrate, wherein the floating gate includes a lower tip pointing to the concave corner of the erase gate, and the lower tip extends beyond a side wall of the trench.

2. The non-volatile memory device according to claim 1, wherein: A bottom surface of the floating gate is higher than the bottom surface of the erase gate.

3. The non-volatile memory device according to claim 1, wherein: A top surface of the floating gate is higher than a top surface of the erase gate.

4. The non-volatile memory device according to claim 1, wherein: A top surface of the floating gate is flush with a top surface of the control gate.

5. The non-volatile memory device according to claim 1, wherein: The lower tip is disposed above the groove.

6. The non-volatile memory device according to claim 1, wherein: The invention also comprises a coupling dielectric layer, which is arranged between a top surface of the erase gate and the bottom surface of the control gate.

7. The non-volatile memory device according to claim 1, wherein: The invention also comprises a source region which is arranged in the substrate, wherein the source region is arranged along the side wall and the bottom surface of the trench.

8. The non-volatile memory device according to claim 1, wherein: The invention also comprises an erase gate dielectric layer, which is arranged between the lower tip and the erase gate.

9. The non-volatile memory device according to claim 8, wherein: The erase gate dielectric layer conformally covers the lower tip, and the erase gate dielectric layer directly contacts a bottom surface of the lower tip.

10. The non-volatile memory device according to claim 8, wherein: The erase gate dielectric layer is further disposed on the sidewall and the bottom surface of the trench.

11. The non-volatile memory device according to claim 8, wherein: The invention also comprises a floating gate dielectric layer, which is arranged between the floating gate and the substrate, wherein one end of the floating gate dielectric layer directly contacts the erase gate dielectric layer.

12. The non-volatile memory device as claimed in claim 1, wherein: The floating gate also includes: Two first side walls, each of the first side walls extending along a first direction; and two second side walls, facing each other and extending along a second direction different from the first direction, The control gate extends along the second direction and covers an upper portion of each second side wall of the floating gate.

13. The non-volatile memory device according to claim 12, wherein: The erase gate extends along the second direction and covers a lower portion of each second sidewall of the floating gate.

14. The non-volatile memory device according to claim 12, wherein: One of the two first side walls is an arc-shaped side wall, and the arc-shaped side wall is covered by the control gate.

15. The non-volatile memory device according to claim 1, wherein: The invention also includes a selection gate which is laterally separated from the erase gate.

16. The non-volatile memory device according to claim 15, wherein: A top surface of the selection gate is higher than a top surface of the erase gate.

17. The non-volatile memory device according to claim 15, wherein: A top surface of the selection gate, a top surface of the control gate and a top surface of the floating gate are flush with each other.

18. The non-volatile memory device according to claim 1, wherein: The floating gate also includes: a horizontal portion disposed below the control gate and including the lower tip; and a vertical portion laterally separated from the control gate, A top surface of the horizontal portion is lower than a top surface of the vertical portion.

19. The non-volatile memory device according to claim 1, wherein: The at least one memory cell includes a first memory cell and a second memory cell, each of the first memory cell region and the second memory cell includes the erase gate, the control gate and the floating gate, and the non-volatile memory element further includes a source region shared by the first memory cell and the second memory cell, and the source region and the trench extend in the same direction.

20. The non-volatile memory device according to claim 18, wherein: The first memory cell and the second memory cell are mirror images of each other.

Images