Non-volatile memory element

Abstract

A non-volatile memory element includes at least one memory cell including a substrate, a select gate, a control gate, an erase gate, and a floating gate. The select gate is disposed on the substrate. The control gate is disposed on the substrate and laterally separated from the selection gate. The erase gate is disposed on the substrate and laterally separated from the control gate, and the erase gate includes a concave angle. And the floating gate electrode covers the control gate electrode and the erasing gate electrode. The floating gate comprises a convex corner facing the concave corner of the erasing gate, and the vertex of the floating gate is lower than the top surface of the selection gate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a non-volatile memory device. Background Art

[0002] Since non-volatile memory can repeatedly perform operations such as storing, writing and erasing data, and since the stored data will not be lost after the non-volatile memory is turned off, non-volatile memory is widely used in personal computers and electronic devices.

[0003] The common structure of non-volatile memory has a stacked gate structure, which includes a tunneling oxide layer, a floating gate, a coupling dielectric layer and a control gate sequentially arranged on a substrate. When performing programming or erasing operations on such flash memory elements, appropriate voltages are applied to the source region, the drain region and the control gate, respectively, so that electrons are injected into the floating gate or pulled out of the floating gate.

[0004] In the programming and erasing operations of non-volatile memory, a larger gate-coupling ratio (GCR) between the floating gate and the control gate generally means that the operation requires a lower operating voltage, which results in a significant increase in the operating speed and efficiency of the flash memory. However, during the programming and erasing operations, electrons need to pass through the tunnel oxide layer disposed under the floating gate to be injected into the floating gate or pulled out of the floating gate, which generally causes structural damage to the tunnel oxide layer, thereby reducing the reliability of the memory element.

[0005] In order to improve the reliability of the memory element, an erase gate can be used and integrated into the memory element. By applying a positive voltage to the erase gate, the erase gate can pull electrons out of the floating gate. Therefore, since the electrons in the floating gate are pulled out by flowing through the tunnel oxide layer set on the floating gate, rather than flowing through the tunnel oxide layer set under the floating gate, the reliability of the memory element is further improved.

[0006] The memory device is usually integrated with logic devices, such as transistors with a planar gate structure, and fabricated on the same wafer. The memory device is usually taller than the logic device because the memory device includes a stacked gate structure including a select gate and an erase gate.

[0007] During the manufacturing process of the middle-end-of-line (MEOL) structure, a blanket ILD layer is formed to cover both the logic element and the memory element. Usually, after the planarization process is performed on the ILD layer, the ILD layer above the memory element is thinner than the ILD layer above the logic element due to the stacked gate structure in the memory element.

[0008] In order to further miniaturize the line width of all contact plugs formed in the ILD layer, it is necessary to reduce the thickness of the ILD layer covering the logic elements and the memory elements. However, if the ILD layer above the memory element becomes too thin, it may cause undesirable electrical coupling between the memory element and the interconnection located thereon, thereby adversely affecting the electrical performance of the memory element.

[0009] Therefore, there is a need for further improvement in the structural design of memory devices. Summary of the invention

[0010] An object of the present invention is to provide a highly reduced non-volatile memory device suitable for integration into a logic device.

[0011] The present invention provides a non-volatile memory element, comprising at least one memory cell. The memory cell comprises a substrate, a selection gate, a control gate, an erase gate and a floating gate. The selection gate is arranged on the substrate. The control gate is arranged on the substrate and is laterally separated from the selection gate. The erase gate is arranged on the substrate and is laterally separated from the control gate, and the erase gate comprises a concave corner. The floating gate is covered by the control gate and the erase gate, and the floating gate comprises a convex corner. The convex corner of the floating gate faces the concave corner of the erase gate. The vertex of the convex corner of the floating gate is lower than the top surface of the selection gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The purpose of the following drawings is to make the present invention more easily understood, and these drawings will be incorporated into and constitute a part of the specification. The drawings illustrate embodiments of the present invention, and together with the sections of the implementation methods, they are used to explain the working principle of the invention.

[0013] Figure 1 is a schematic top view of a non-volatile memory device according to some embodiments of the present invention.

[0014] Figure 2 is a non-volatile memory element according to some embodiments of the present invention corresponding to Figure 1 Schematic cross-sectional view of the section line AA'.

[0015] Figure 3 yes Figure 2 Enlarged cross-section of the middle area.

[0016] Figure 4 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention.

[0017] Figure 5 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention.

[0018] Figure 6 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention.

[0019] Figures 7 to 12 are cross-sectional views of different stages in the fabrication process of a non-volatile memory device according to some embodiments of the present invention.

[0020] Figures 13 to 17 are cross-sectional views of different stages in the manufacturing process of a non-volatile memory device according to some other embodiments of the present invention.

[0021] Description of reference numerals: 100 - non-volatile memory element; 100_1, 100_2, 100_3, 100_4 - non-volatile memory element; 102 - isolation structure; 103 - active region; 110 - first memory cell region; 112 - second memory cell region; 114 - third memory cell region; 116 - fourth memory cell region; 200 - substrate; 202 - selection gate dielectric layer; 204 - selection Gate; 204a, 224a, 236a, 238_2a, 240a, 245a-top surface; 208-insulating layer; 220-floating gate dielectric layer; 222-source region; 224-floating gate; 224_1-base portion; 224_2-protrusion; 226_1, 226_2, 226_3-convex corner; 228_1, 228_2, 228_3-vertex; 234-erase gate dielectric layer; 236-erase gate; 236_1-base; 236_1b, 236_2b, 250-bottom surface; 236_2-protrusion; 238-coupling dielectric layer; 238_1-first part; 238_2-second part; 239-recessed corner; 240-control gate; 243-continuous selection gate layer; 244-drain region; 245-selection gate layer; 248-etching mask; 252-self-aligned etching mask; 254-floating gate; 256-self-aligned etching mask; 258-sacrificial layer; 260-accommodating area; 300-stacked structure; 701, 702, 703, 704, 705, 706, 707, 708, 709, 710, 711, 801, 802, 803, 804, 805, 806, 807, 808, 809, 810-steps; R1, R2, R3, R4-areas. DETAILED DESCRIPTION

[0022] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0023] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "below", "above", "upper", "lower", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the possible swing direction of the semiconductor element during use and operation. As the swing direction of the semiconductor element is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its swing direction should also be interpreted in a similar manner.

[0024] Although the present invention is described below by specific embodiments, the inventive principle of the present invention is defined by the claims and can be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians with common knowledge in the relevant technical field.

[0025] Figure 1 is a schematic top view of a non-volatile memory element according to some embodiments of the present invention. Figure 1 , the non-volatile memory device 100 may be a NOR flash memory device including at least one memory cell, for example, four memory cells located in the first, second, third and fourth memory cell regions 110, 112, 114 and 116. The structures in the first memory cell region 110 and the second memory cell region 112 are mirror images of each other, while the structures in the third memory cell region 114 and the fourth memory cell region 116 are mirror images of each other. According to one embodiment of the present invention, the non-volatile memory device 100 includes more than four memory cells, which may be arranged in an array of multiple rows and columns.

[0026] Reference Figure 1 The non-volatile memory device 100 includes a substrate 200 and an isolation structure 102. The substrate 200 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The isolation structure 102 may be an insulating material and is used to define an active region 103 of a memory cell.

[0027] Each memory cell includes a source region 222 and a drain region 244, which are located in the active region 103 defined by the isolation structure 102. The source region 222 and the drain region 244 can be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 244 is different from the conductivity type of the substrate 200, or different from the conductivity type of the doping well (not shown) used to accommodate the source region 222 and the drain region 244. The source region 222 can be located at one end of the active region 103, and the drain region 244 can be located at the other end of the active region 103. According to some embodiments of the present invention, the source region 222 is a continuous region extending along the Y direction and is shared by the memory cells in the same row.

[0028] Each memory cell may further include a select gate 204 disposed on the substrate 200 and adjacent to the drain region 244. The select gate 204 may extend in the Y direction and be shared by the memory cells in the same row. The select gate 204 may be made of a conductive material, such as polysilicon or metal. The select gate 204 may serve as a word line, which is configured to turn on / off the channel region of the corresponding memory cell in the same row.

[0029] An optional dielectric spacer (not shown) may be disposed on the sidewall of the select gate 204 to isolate the select gate 204 from other conductive elements. The dielectric spacer may be a single-layer, double-layer, or multi-layer spacer disposed on each sidewall of the select gate 204, but is not limited thereto.

[0030] Each memory cell also includes a floating gate 224, which is disposed on the substrate 200 and adjacent to the source region 222. Therefore, the floating gate 224 is disposed on one side of the select gate 204, and the drain region 244 is disposed on the other side of the select gate 204. The floating gate 224 is made of a conductive material, such as polysilicon or other semiconductors. The floating gates 224 are laterally separated from each other to prevent current from being directly transmitted between the floating gates 224. Since the floating gates 224 are laterally separated from each other, each floating gate 224 can be independently programmed or erased, thereby determining the state of each memory cell, such as state "1" or state "0". As shown in the following cross-sectional diagram (for example Figure 2 and Figure 3 ), each floating gate 224 has a base portion and a protruding portion. The detailed structure of the floating gate 224 is shown in FIG. Figure 2 and Figure 3 Described in the description.

[0031] The floating gate dielectric layer 220 is disposed between the floating gate 224 and the select gate 204. The floating gate dielectric layer 220 also extends below the floating gate 224. The floating gate dielectric layer 220 may be made of, for example, silicon oxide or other materials.

[0032] During a programming operation, hot electrons generated under the floating gate dielectric layer 220 may be allowed to be injected and accumulated in the floating gate 224 .

[0033] Each memory cell also includes a control gate 240 disposed on the substrate 200 and extending in the Y direction. The control gate 240 is disposed in the gap between the opposing select gates 204. The control gate 240 may be shared by a pair of memory cells located in the same column. For example, the control gate 240 may be shared by memory cells respectively accommodated in the first memory cell region 110 and the second memory cell region 112. Since the floating gate 224 includes a base portion (not shown) and a protrusion (not shown), only the base portion of the floating gate 224 is covered by the control gate 240, while the protrusion of the floating gate 224 is laterally separated from the control gate 240. In a top view, the control gate 240 may cover the continuous source region 222. The control gate 240 is made of a conductive material such as polysilicon, metal or other conductive semiconductors, but is not limited thereto.

[0034] The purpose of the control gate 240 is to inject hot carriers (e.g., electrons) from the channel into the floating gate 224. For example, when an appropriate positive voltage is applied to the control gate 240, hot carriers (e.g., electrons) transported in the carrier channel below the floating gate 224 can be injected and accumulated in the corresponding floating gate 224.

[0035] The non-volatile memory device 100 further includes an erase gate (not shown) disposed on the substrate 200. The erase gate is located in the accommodation region 260 and extends in the same direction (i.e., the Y direction) as the source region 222. The erase gate is laterally separated from the control gate 240. According to different design requirements, the erase gate may cover or be laterally separated from the select gate 204. In other words, the width of the erase gate may be equal to or less than the width of the accommodation region 260. For example, when the width of the erase gate is the same as the width of the accommodation region 260, the erase gate may cover portions of the select gate 204 and the floating gate 224. In contrast, when the erase gate is narrower than the accommodation region 260, the erase gate may be laterally separated from the select gate 204 but still cover a portion of the floating gate 224.

[0036] During an erase operation of the non-volatile memory 100 , the erase gate is biased, thereby allowing the electrons stored in the floating gate 224 to be pulled out primarily through the tip (also referred to as the convex corner) of the floating gate 224 .

[0037] Figure 2 The non-volatile memory element according to some embodiments of the present invention corresponds to Figure 1 Schematic diagram of the cross section of the section line A-A'. Figure 2 In the first memory cell region 110 or the second memory cell region 112, the selection gate 204, the erase gate 236, and the control gate 240 of the non-volatile memory device 100_1 are all disposed on the substrate 200. The top surface 236a of the erase gate 236 is substantially flush with the top surface 240a of the control gate 240, and even substantially flush with the top surface 204a of the selection gate 204.

[0038] The floating gate 224 may be L-shaped, including a base portion and an upwardly protruding portion (also referred to as a protrusion). A top surface 224 a of the protrusion is lower than a top surface 204 a of the selection gate 204 .

[0039] The erase gate dielectric layer 234 is not only disposed between the erase gate 236 and the floating gate 224, but also disposed between the erase gate 236 and the select gate 204. The erase gate dielectric layer 234 may be made of a dielectric layer that allows electrons originally stored in the floating gate 224 to penetrate therethrough via a Fowler-Nordheim (FN) tunneling mechanism.

[0040] The coupling dielectric layer 238 is disposed below the control gate 240. The coupling dielectric layer 238 includes a first portion 238_1 disposed between the control gate 240 and the erase gate 236 and a second portion 238_2 disposed between the control gate 240 and the erase gate 236. The coupling dielectric layer 238 may be a single dielectric layer including silicon oxide or silicon oxynitride, or a composite dielectric layer including silicon oxide / silicon nitride / silicon oxide, or any high dielectric constant layer such as a plurality of metal oxides, but is not limited thereto. In the present invention, the high dielectric constant layer is made of a material having a k value greater than 4, such as HfO, HfSiO, HfAlO, or HfTaO.

[0041] according to Figure 2 In one embodiment, since the top surfaces 204a, 236a, and 240a are substantially flush with each other, the non-volatile memory device 100_1 may have a lower height compared to other non-volatile memory devices in which the erase gate is stacked on the select gate.

[0042] Figure 3 According to some embodiments of the present invention Figure 2 The enlarged cross-sectional view of the R1 region in Figure 2. Figure 3 , the floating gate 224 includes a base portion 224_1 and a protrusion 224_2 disposed on the base portion 224_1. The base portion 224_1 may extend from below the control gate 240 to below the erase gate 236. The protrusion 224_2 is located between the select gate 204 and the control gate 240, and is thus laterally separated from the control gate 240. The protrusion 224_2 includes a convex corner 226_2 (also referred to as a convex upper corner) facing the erase gate 236, and the vertex 228_2 of the convex corner 226_2 of the floating gate 224 may be lower than the top surface 204a of the select gate 204.

[0043] The erase gate 236 includes a concave corner 239 at a lower portion thereof, and the concave corner 239 faces the convex corner 226_2 of the floating gate 224. In some embodiments, the convex corner 226_2 of the floating gate 224 may point to the concave corner 239 of the erase gate 236.

[0044] The erase gate 236 further includes a base portion 236_1 and a protrusion 236_2 (also referred to as a downward protrusion) disposed below the base portion 236_1 . Therefore, a bottom surface 236_2 b of the protrusion 236_2 is lower than a bottom surface 236_1 b of the base portion 236_1 .

[0045] The base portion 236_1 covers portions of both the floating gate 224 and the select gate 204, extends from above the top surface of the floating gate 224, and extends beyond the convex corner 226_2 of the floating gate 224. The protrusion 236_2 is laterally separated from the floating gate 224, and a portion of the select gate 204 is located between the protrusion 236_2 and the substrate 200. In order to effectively remove the stored electrons from the floating gate 224 via the convex corner 226_2, the bottom surface 236_2b of the protrusion 236_2 of the erase gate 236 can be modified to be lower than the vertex 228_2 of the convex corner 226_2, which causes the vertex 228_2 of the convex corner 226_2 to be partially wrapped by the erase gate 236.

[0046] For the second portion 238_2 of the coupling dielectric layer 238 between the erase gate 236 and the control gate 240 , a top surface 238_2 a of the second portion 238_2 may be flush with a top surface 236 a of the erase gate 236 , or even flush with a top surface 240 a of the control gate 240 and a top surface 204 a of the select gate 204 .

[0047] Figure 4 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention. Figure 4 The structure shown in is similar to Figure 2 and Figure 3 structure shown; however, the main difference is Figure 4 The erase gate 236 is shown laterally separated from the select gate 204, rather than overlapping it. Figure 4 In the non-volatile memory device 100_2 shown in FIG. 1 , particularly in the enlarged cross-sectional view of the region R2, the convex corner 226_2 of the protrusion 224_2 of the selection gate 224 still faces the concave corner 239 of the erase gate 236. However, the base portion 236_1 and the protrusion 236_2 of the erase gate 236 are laterally separated from the selection gate 204. In addition, the protrusion 236_2 of the erase gate 236 is located between the protrusion 224_2 of the floating gate 224 and the control gate 240, and the protrusion 236_2 covers the base portion 224_1 of the selection gate 204.

[0048] Figure 5 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention. Figure 5 The structure of the non-volatile memory element 100_3 shown in FIG. 1 is similar to that of Figure 2 and Figure 3; however, the main difference is that the protrusion 224_2 of the floating gate 224 is disposed on the sidewall of the base portion 224_1 of the floating gate 224, rather than on the top surface. Therefore, the protrusion 224_2 can extend from the sidewall of the base portion 224_1 toward the selection gate 204. The thickness of the protrusion 224_2 is less than the thickness of the base portion 224_1, so the top surface of the protrusion 224_2 is lower than the top surface of the base portion 224_1. In addition, the base portion 224_1 includes a convex corner 226_1 (also called a convex upper corner) facing the erase gate 236, and the vertex 228_1 of the convex corner 226_1 of the floating gate 224 can be lower than the top surface 204a of the selection gate 204.

[0049] In order to efficiently remove electrons stored in the floating gate 224 through the convex corner 226_1 , the bottom surface 236_2 b of the protrusion 236_2 of the erase gate 236 can be modified to be lower than the vertex 228_1 of the convex corner 226_1 . This modification causes the vertex 228_1 of the convex corner 226_1 to be partially wrapped by the erase gate 236 .

[0050] Figure 6 is a schematic cross-sectional view and an enlarged cross-sectional view of a non-volatile memory element according to another embodiment of the present invention. Figure 6 The structure shown is similar to Figure 2 and Figure 3 However, the main difference is that the erase gate 236 lacks a concave corner and does not extend beyond the sidewall of the underlying floating gate 224. The erase efficiency of the non-volatile memory device 100_4 is expected to be lower than that of the aforementioned embodiments with convex corners 226_1 and 226_2. Figure 6 The memory cell is easier to manufacture.

[0051] In addition, the floating gate 224 includes a convex corner 226_3 (also referred to as a convex upper corner), and a vertex 228_3 of the convex corner 226_3 may be lower than the top surface 204 a of the selection gate 204 .

[0052] Figures 7 to 12 are cross-sectional views of various stages in the fabrication process of a non-volatile memory device according to some embodiments of the present invention. Figures 7 to 12 The structure shown corresponds to Figure 1 A-A' section line.

[0053] Reference Figure 7 In step 701, the structure formed at this manufacturing stage at least includes a substrate 200 and a stacked structure 300. The stacked structure 300 includes a select gate dielectric layer 202, a continuous select gate layer 243, an insulating layer 208, and an etching mask 248 stacked in sequence.

[0054] The substrate 200 may be a semiconductor substrate with an appropriate conductivity type, such as a p-type or an n-type. The substrate 200 may be made of silicon, germanium, gallium nitride or other appropriate semiconductor materials, but is not limited thereto.

[0055] The continuous selection gate layer 243 is made of a conductive material. In a subsequent manufacturing process, the continuous selection gate layer 243 may be patterned or processed to form one or more selection gates. When the selection gate is subjected to an appropriate bias voltage, the selection gate is configured to open or close a carrier channel (also referred to as a channel region) in the substrate 200 under the selection gate layer.

[0056] The insulating layer 208 and the etching mask layer 248 can be made of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto. Since the etching selectivity of the continuous selection gate layer 243 to the etching mask 248 is greater than 2, and preferably greater than 5, the etching mask 248 can be used to define a mesa of the continuous selection gate layer 243 during the etching process.

[0057] Subsequently, a dielectric layer (not shown) is uniformly deposited on the continuous selection gate layer 243 and the etching mask layer 248. Then, the dielectric layer is anisotropically etched to form a self-aligned etching mask layer 252, as shown in step 702.

[0058] In step 702, another anisotropic etching is performed on the continuous select gate layer 243 using the etching mask layer 248 and the self-aligned etching mask layer 252 as etching masks. During the etching process, the continuous select gate layer 243 may be split to form at least two laterally separated select gate layers 245 (or two stacked structures 300).

[0059] During the formation of the select gate layer 245, due to the presence of the self-aligned etching mask 252, each select gate layer 245 may include a concave corner 250 covered by the self-aligned etching mask 252. In the top view, the self-aligned etching mask 252 and the select gate layer 245 may both extend along the Y direction.

[0060] refer to Figure 8In step 703, a floating gate dielectric layer 220 and a conformal floating gate layer 254 are formed on the substrate 200 and the select gate layer 245. The material of the floating gate dielectric layer 220 is, for example, silicon oxide, or other layers that allow hot electrons to penetrate. The method for forming the floating gate dielectric layer 220 is, for example, thermal oxidation or deposition method, but is not limited thereto. The material of the conformal floating gate layer 254 is, for example, doped polysilicon, polycrystalline silicide or other appropriate conductive materials. When the material of the conductive layer is doped polysilicon, its formation method includes, for example, after forming a non-doped polysilicon layer by chemical vapor deposition, performing an ion implantation step; or using a chemical vapor deposition method with an in-situ dopant implantation method.

[0061] Then, a photolithography and etching process is performed to etch the conformal floating gate layer 254. As a result, the conformal floating gate layer 254 can be patterned to form a plurality of conductive strips separated from each other in a top view. Each conductive strip can extend along the X direction and be located at least in the first memory cell region 110 and the second memory cell region 112.

[0062] In step 704, after forming the floating gate layer 254 including a plurality of stripe patterns, two self-aligned etching masks 256 are formed on the vertical surface of the floating gate layer 254. The self-aligned etching masks 256 can be made of a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, but are not limited to these materials. The self-aligned etching masks 256 are laterally separated from each other so that the portion of the floating gate layer 254 located between the self-aligned etching masks 256 is exposed. In the top view, the self-aligned etching masks 256 are stripe structures extending along the Y direction.

[0063] Afterwards, an etching process is performed, using the self-aligned etching mask 256 as an etching mask to etch a portion of the floating gate layer 254. As a result, a floating gate 224 including a vertical portion and a horizontal portion is obtained. The floating gate 224 is a self-aligned structure, so there is no need to use a photolithography process to define the position of the floating gate 224. Two floating gates 224 can be formed in the first memory cell region 110 and the second memory cell region 112, respectively, and can be laterally separated from each other in the X direction.

[0064] Then, a source region 222 is formed in the portion of the substrate 200 not covered by the floating gate 224. Forming the source region 222 includes, for example, performing an ion doping process. The dopant introduced may be an n-type or p-type dopant, depending on the design requirements of the device. The dopant type and concentration of the source region 222 may be adjusted according to actual requirements.

[0065] Reference Fig. 9In step 705, a sacrificial layer 258 may be filled in the gap at the boundary between the first memory cell region 110 and the second memory cell region 112. The sacrificial layer 258 may be formed by sequentially performing a coating process and an etch-back process. During the coating process, all components placed on the substrate 200 may be covered by the sacrificial layer 258. Then, in the etch-back process, the height of the sacrificial layer 258 may be lowered until the top surface of the sacrificial layer 258 reaches a predetermined height. Since the etching rate of the sacrificial layer 258 is greater than the etching rate of other components (e.g., the floating gate 224) on the substrate 200 in the etch-back process, the height of the floating gate 224 may remain unchanged or only slightly reduced. The sacrificial layer 258 may be made of an organic material, such as a photosensitive polymer and / or a bottom anti-reflective coating (BARC), but is not limited thereto.

[0066] In step 706, an anisotropic etching process is performed to remove all of the self-aligned etching mask 252 and the upper portion of the floating gate 224 until a portion of the selection gate 204 originally covered by the self-aligned etching mask 252 is exposed. By properly controlling the etching recipe and the type or ratio of the etchant, when the self-aligned etching mask 252 is completely removed, the floating gate 224 including the base portion 224_1 and the protrusion 224_2 can be obtained. The protrusion 224_2 is placed on the base portion 224_1, and the vertex 228_2 of the convex corner 226_2 of the protrusion 224_2 is higher than the bottom surface of the concave corner 250 of the selection gate 204.

[0067] In addition, in the process of etching the self-aligned etching mask 252 and the floating gate 224, a portion of the sacrificial layer 258 may also be etched at the same time, and the height of the sacrificial layer 258 may be slightly reduced. However, in order to protect the base portion 224_1 of the floating gate 224 from being etched, when the etching process is completed, a portion of the sacrificial layer 258 may still cover the base portion 224_1. After the etching process, the remaining sacrificial layer 258 can be removed by a wet etching process.

[0068] refer to Fig.10In step 707, an erase gate dielectric layer 234 is formed to cover the select gate layer 245 and the floating gate 224. In some embodiments, the top surfaces of the base portion 224_1 and the protrusion 224_2 of the floating gate 224 may be covered by the erase gate dielectric layer 234. In addition, the convex corner 226_2 may also be covered by the erase gate dielectric layer 234. The thickness of the erase gate dielectric layer 234 is less than the thickness of the floating gate 224. Then, by performing deposition and etching processes, an erase gate 236 is formed on the floating gate 224. The erase gate 236 may be a self-aligned structure having a base portion 236_1 and a protrusion 236_2. Due to the presence of the convex corner 226_2 of the floating gate 224, the erase gate 236 may have a concave corner 239 corresponding to the position of the convex corner 226_2.

[0069] Then, in step 708 , a coupling dielectric layer 238 is formed to cover the base portion 224_1 of the floating gate 224 and the erase gate 236 .

[0070] refer to Fig.11 In step 709, a control gate 240 is formed in the gap at the boundary of the first memory cell region 110 and the second memory cell region 112. The top surface 240a of the control gate 240 is higher than the top surface 224a of the floating gate 224 (i.e., the top surface of the protruding portion of the floating gate 224) and the top surface 245a of the selection gate layer 245. The formation of the control gate 240 may include the following steps: filling a conductive layer such as polysilicon or metal into the gap, planarizing the conductive layer, and etching back the conductive layer until its top surface reaches a predetermined height.

[0071] In step 710, a planarization process may be performed to remove the etching mask layer 248 on the select gate layer 245 and make the top surface 236a of the erase gate 236 flush with the top surface 240a of the control gate 240. In order to effectively remove electrons from the floating gate 224 during the erase operation, the top surface 236a of the erase gate 236 is still higher than the top surface 224a of the floating gate 224 even after the planarization process is completed.

[0072] At this manufacturing stage, the top surface 245a of the selection gate layer 245 is still covered by the insulating layer 208. However, according to different design requirements, the insulating layer 208 can also be removed in the same or additional planarization process, so that the top surface 245a of the selection gate layer 245, the top surface 236a of the erase gate 236, and the top surface 240a of the control gate 240 can be flush with each other.

[0073] Afterwards, the select gate layer 245 may be patterned to form Fig.12 A select gate 204 is shown.

[0074] refer to Fig.12 In step 711, an optional dielectric spacer (not shown) may be formed on the sidewalls of the selection gate 204 to isolate the selection gate 204 from other conductive elements. At least one drain region 244, for example two drain regions 244, may be formed on the side of the selection gate 204. The drain regions 244 are respectively disposed in the first memory cell region 110 and the second memory cell region 112, which may be electrically coupled to each other through vias or contacts in a subsequent manufacturing process. The method for forming the drain region 244 includes, for example, performing an ion implantation process. The implanted dopant may be an n-type or p-type dopant, depending on the design of the device. The dopants and doping concentrations of the source region 222 and the drain region 244 may be the same or different.

[0075] Subsequently, other electronic components can be manufactured through appropriate manufacturing processes to obtain similar Figures 1 to 3 A non-volatile memory element of the structure shown in FIG.

[0076] Figures 13 to 17 are cross-sectional views of different stages in the manufacturing process of a non-volatile memory element according to some other embodiments of the present invention. Figures 13 to 17 The manufacturing process of the embodiment shown is similar to Figures 7 to 12 The manufacturing process of the embodiments shown is described above, so for the sake of brevity, only the main differences between the embodiments are described.

[0077] Reference Fig.13 The manufacturing process in steps 801 and 802 is similar to that in Figure 7 and Figure 8 The manufacturing process in steps 701 to 703 is shown.

[0078] In step 801, the structure formed in this manufacturing process includes a substrate 200 and two stacked structures 300. The stacked structures are laterally separated from each other, and each includes a select gate dielectric layer 202, a select gate layer 245, an insulating layer 208, and an etching mask 248 stacked in sequence.

[0079] Subsequently, in step 802 , a floating gate dielectric layer 220 and a conformal floating gate layer 254 are formed on the substrate 200 and the select gate layer 245 .

[0080] Reference Fig.14 The manufacturing process in steps 803 and 804 is similar to Figure 8 and Fig. 9 The manufacturing process in steps 704 and 705 is shown.

[0081] In step 803, after forming the floating gate layer 254 including a plurality of stripe patterns, two self-aligned etching masks 256 are formed on the vertical surface of the floating gate layer 254 shown in step 802. Thereafter, an etching process is performed using the self-aligned etching masks 256 as etching masks to etch a portion of the floating gate layer 254. As a result, a floating gate 224 including a vertical portion and a horizontal portion is obtained.

[0082] In step 804, a sacrificial layer 258 may be filled in the gap at the boundary between the first memory cell area 110 and the second memory cell area 112. The sacrificial layer 258 may be formed by sequentially performing a coating process and an etch-back process. In the coating process, all components deposited on the substrate 200 may be covered by the sacrificial layer 258. Then, in the etch-back process, the height of the sacrificial layer 258 may be reduced until the top surface of the sacrificial layer 258 reaches a predetermined height. Since the etching rate of the sacrificial layer 258 is greater than the etching rate of other components (e.g., the floating gate 224) on the substrate 200 in the etch-back process, the height of the floating gate 224 may remain unchanged or only slightly reduced.

[0083] Reference Fig.15 The manufacturing process in steps 805 and 806 is similar to Fig. 9 and Fig.10 The manufacturing process in steps 706 and 707 is shown.

[0084] In step 805, an anisotropic etching process is performed to etch the vertical portion of the floating gate 224 until the uppermost surface of the floating gate 224 is lower than the top surface 245a of the select gate layer 245. By properly controlling the etching recipe and the type or ratio of the etchant, the floating gate 224 including the base portion 224_1 and the protrusion 224_2 can be obtained. The protrusion 224_2 is disposed on the base portion 224_1, and its vertex 228_2 is higher than the top surface of the base portion 224_1.

[0085] In addition, during the etching process of the self-aligned etching mask 252 and the floating gate 224, a portion of the sacrificial layer 258 may also be etched simultaneously, and the height of the sacrificial layer 258 may be slightly reduced. After the etching process, the remaining sacrificial layer 258 may be removed by a wet etching process.

[0086] Then, a source region 222 is formed in the portion of the substrate 200 not covered by the floating gate 224 .

[0087] In step 806, an erase gate dielectric layer 234 is formed to cover the select gate layer 245 and the floating gate 224. The convex corner 226_2 may also be covered by the erase gate dielectric layer 234. Then, by performing deposition and etching processes, an erase gate 236 is formed on the floating gate 224. The erase gate 236 may be a self-aligned structure including a base portion 236_1 and a protrusion 236_2, and the protrusion 236_2 is laterally separated from the select gate layer 245 and the protrusion 224_2.

[0088] refer to Fig.16 , the manufacturing process in steps 807 and 808 is similar to Fig.10 and Fig.11 The manufacturing process in steps 708 and 709 is shown in FIG.

[0089] In step 807 , a coupling dielectric layer 238 is formed to cover the base portion 224_1 of the floating gate 224 and the erase gate 236 .

[0090] In step 808, a control gate 240 is formed in the gap between the first memory cell region 110 and the second memory cell region 112. The top surface 240a of the control gate 240 is higher than the top surface 224a of the floating gate 224 (i.e., the top surface of the protruding portion of the floating gate) and the top surface 245a of the select gate 245.

[0091] Reference Fig.17 The manufacturing process in step 809 and step 810 is similar to Fig.11 and Fig.12 The manufacturing process in steps 710 and 711 is shown in FIG.

[0092] In step 809, a planarization process may be performed to remove the etching mask 248 on the select gate layer 245 and make the top surface 236a of the erase gate 236 flush with the top surface 240a of the control gate 240. In order to effectively remove electrons from the floating gate 224 during the erase operation, the top surface 236a of the erase gate 236 remains higher than the top surface 224a of the floating gate 224 even after the planarization process is completed.

[0093] At this manufacturing stage, the top surface 245a of the selection gate layer 245 is still covered by the insulating layer 208. However, according to different design requirements, the insulating layer 208 can also be removed in the same or additional planarization process, so that the top surface 245a of the selection gate layer 245, the top surface 236a of the erase gate 236, and the top surface 240a of the control gate 240 can be flush with each other.

[0094] Afterwards, the select gate layer 245 may be patterned to form the select gate 204, as shown in step 810. In step 810, at least one drain region 244, for example, two drain regions 244, may be formed on the side of the select gate 204. In subsequent manufacturing processes, the plurality of drain regions 244 may be electrically coupled to each other through vias or contacts.

[0095] Afterwards, other electronic components can be manufactured through appropriate manufacturing processes to obtain similar Figure 4 A non-volatile memory element of the structure shown.

[0096] In some embodiments, Figure 5 and Figure 6 As shown in the structure, these structures can be used similar to Figures 7 to 17 The manufacturing process is described in detail below, and thus the corresponding manufacturing process is omitted for the sake of brevity.

[0097] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A non-volatile memory device, comprising at least one memory unit, characterized in that: The at least one memory unit comprises: a substrate; A selection gate is disposed on the substrate; a control gate disposed on the substrate and laterally separated from the select gate; an erase gate disposed on the substrate and laterally separated from the control gate, wherein the erase gate includes a concave corner; and a floating gate covered by the control gate and the erase gate, wherein the floating gate includes a convex corner, and the convex corner of the floating gate faces the concave corner of the erase gate; A vertex of the convex corner of the floating gate is lower than a top surface of the selection gate.

2. The non-volatile memory device according to claim 1, wherein: The convex corner of the floating gate points to the concave corner of the erase gate.

3. The non-volatile memory device according to claim 1, wherein: A top surface of the erase gate is flush with a top surface of the control gate.

4. The non-volatile memory device according to claim 1, wherein: A top surface of the erase gate, a top surface of the control gate and a top surface of the selection gate are flush with each other.

5. The non-volatile memory device according to claim 1, wherein: The floating gate further comprises: a base portion; and a protrusion, disposed on a top surface or a side wall of the base portion; The base portion extends from below the control gate to below the erase gate.

6. The non-volatile memory device according to claim 5, wherein: The protrusion is laterally separated from the control gate.

7. The non-volatile memory device according to claim 5, wherein: The protrusion includes the convex corner.

8. The non-volatile memory device according to claim 5, wherein: A portion of the erase gate is laterally separated from the base portion.

9. The non-volatile memory device according to claim 5, wherein: The erase gate is disposed on the protrusion and is laterally separated from the select gate.

10. The non-volatile memory device according to claim 5, wherein: The base portion includes the convex corner.

11. The non-volatile memory device according to claim 10, wherein: The protrusion extends from the base toward the selection gate.

12. The non-volatile memory device according to claim 10, wherein: A thickness of the protruding portion is smaller than a thickness of the base portion.

13. The non-volatile memory device according to claim 1, wherein: The erase gate further comprises: a base portion; and a protrusion disposed below the base portion; Wherein, a bottom surface of the protruding portion is lower than a bottom surface of the base portion.

14. The non-volatile memory device according to claim 13, wherein: The bottom surface of the protruding portion of the erase gate is lower than the top point of the convex corner of the floating gate.

15. The non-volatile memory device according to claim 13, wherein: The protrusion of the erase gate is laterally separated from the floating gate.

16. The non-volatile memory device according to claim 13, wherein: A portion of the selection gate is disposed between the protrusion of the erase gate and the substrate.

17. The non-volatile memory device according to claim 13, wherein: The protrusion of the erase gate is laterally separated from the select gate.

18. The non-volatile memory device according to claim 1, wherein: Further comprising a coupling dielectric layer disposed on the substrate, wherein the coupling dielectric layer comprises: a first portion disposed between the control gate and the floating gate; and A second portion is disposed between the control gate and the erase gate, wherein a top surface of the second portion is flush with a top surface of the erase gate.

19. The non-volatile memory device according to claim 18, wherein: The top surface of the second portion is flush with a top surface of the control gate and a top surface of the selection gate.

20. The non-volatile memory device according to claim 1, wherein: The at least one memory cell includes a first memory cell and a second memory cell, the first memory cell and the second memory cell respectively include the selection gate, the control gate, the erase gate and the floating gate, and the non-volatile memory element further includes a source region shared by the first memory cell and the second memory cell, wherein the source region and the erase gate extend along a same direction.

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