Self-aligned vertical integration of three-terminal memory devices

Abstract

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of dual channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double-channel holes have peanut-shaped cross sections in a second direction transverse to the first direction.

Description

This application is a divisional application of the invention patent application with application number 201980070832.1, application date October 22, 2019, and invention name “Self-aligned vertical integration of three-terminal memory devices”. CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 62 / 775,615, filed on December 5, 2018, and U.S. Provisional Application No. 62 / 751,089, filed on October 26, 2018. The entire disclosures of the above-referenced applications are incorporated herein by reference. Technical Field

[0002] The present invention relates to memory devices, and more particularly to self-aligned vertical integration of three-terminal memory devices. Background Art

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0004] Electronic devices include non-volatile memory such as flash memory for storing data. The flash memory is usually implemented as one or more integrated circuits (ICs) containing memory cells. As electronic devices shrink in size and use more data, the cost, density, and access speed of these memory cells become increasingly important.

[0005] Early on, these memory cells were arranged in two-dimensional (2-D) memory arrays. More recently, these memory cells have been arranged in three-dimensional (3D) arrays to increase density and reduce cost. Memory cells in three-dimensional memory arrays are typically two-terminal devices. Either a selector element is required, or the memory is not bit-addressable. If the memory is not bit-addressable, it is suitable for storage applications, but is generally not suitable for working memory applications. Summary of the invention

[0006] A three-dimensional (3D) memory structure for a memory cell includes a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction.

[0007] In other features, within the plurality of dual-channel holes, the plurality of word line layers are recessed relative to the plurality of oxide layers. The memory cell also includes a three-terminal NOR memory cell. A multilayer stack is deposited on the inner surface of the plurality of dual-channel holes and defines a first cavity extending in the first direction.

[0008] In other features, the first cavity has a peanut-shaped cross-section in the second direction. The multilayer stack includes a blocking oxide layer, a charge trapping layer, and a gate oxide layer. The multilayer stack includes a blocking oxide layer, a ferroelectric layer, and a gate oxide layer. The multilayer stack includes a blocking oxide layer, a spin-orbit torque (SOT) layer, and a gate oxide layer.

[0009] In other features, a polysilicon layer is disposed on an inner surface of the first cavity. The polysilicon layer defines a second cavity and a third cavity extending in the first direction. The second cavity and the third cavity have an elliptical cross-section in the second direction. The polysilicon layer includes P - The polysilicon layer has an 8-shaped cross section in the second direction.

[0010] Among other features, N + A layer is disposed within the second cavity and within the third cavity.

[0011] A method for manufacturing a three-dimensional (3D) memory structure for a memory cell includes: providing a substrate, the substrate including a plurality of oxide layers and a plurality of nitride layers. The plurality of oxide layers and the plurality of nitride layers are alternately stacked in a first direction. The method includes: etching a plurality of dual-channel holes in the plurality of oxide layers and the plurality of nitride layers. The plurality of dual-channel holes extend in the first direction. The plurality of dual-channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction.

[0012] In other features, the memory cell comprises a three-terminal NOR memory cell. The method comprises etching back the plurality of nitride layers relative to the plurality of oxide layers within the plurality of dual-channel holes. The method comprises depositing a multilayer stack on inner surfaces of the plurality of dual-channel holes. The multilayer stack defines a first cavity extending in the first direction. The first cavity has a peanut-shaped cross-section in the second direction.

[0013] In other features, depositing the multilayer stack includes depositing a blocking oxide layer, a charge trapping layer, and a gate oxide layer.Depositing the multilayer stack includes depositing a blocking oxide layer, a ferroelectric layer, and a gate oxide layer.Depositing the multilayer stack includes depositing a blocking oxide layer, a spin-orbit torque (SOT) layer, and a gate oxide layer.

[0014] In other features, the method includes depositing a polysilicon layer on an inner surface of the first cavity within the plurality of dual channel holes. The polysilicon layer defines a second cavity and a third cavity extending in the first direction. The second cavity and the third cavity have an elliptical cross-section in the second direction. The polysilicon layer includes P - The polysilicon layer has an 8-shaped cross section in the second direction.

[0015] In other features, the method includes depositing N in the second cavity and the third cavity. + The method includes cutting the substrate to at least partially expose portions of the plurality of nitride layers. The method includes etching the plurality of nitride layers. The method includes depositing a conductive filler at etched locations of the plurality of nitride layers.

[0016] A three-dimensional (3D) memory structure for a memory cell includes a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction. The plurality of word line layers within the plurality of double channel holes are concave relative to the plurality of oxide layers in the second direction. A blocking dielectric layer is deposited on inner surfaces within the plurality of double channel holes, on inner surfaces of the plurality of oxide layers within the first region at ends of the plurality of double channel holes between the plurality of oxide layers, and on inner surfaces of the plurality of oxide layers and the plurality of word line layers within the second region at sides of the plurality of double channel holes between the plurality of oxide layers.

[0017] In other features, the memory cell comprises a three-terminal NOR memory cell. The plurality of dual-channel holes have a peanut-shaped cross-section in the second direction. The self-aligned contacts are disposed in a first region between ends of the plurality of dual-channel holes. The charge trapping layer is disposed on opposite sides of the self-aligned contacts in the first region. The charge trapping layer is disposed in a second region adjacent to the blocking dielectric layer.

[0018] In other features, the gate oxide layer is disposed on the plurality of oxide layers and the charge trapping layer within the plurality of dual channel holes. The polysilicon layer is disposed on the gate oxide layer within the plurality of dual channel holes. The polysilicon layer defines a P - The polysilicon layer defines a first hole extending in a first direction and a second hole extending in the first direction. The first hole and the second hole have an elliptical cross section in the second direction. The polysilicon layer has an 8-shaped cross section in the second direction. + The layer is disposed within the first cavity and the second cavity.

[0019] A method for manufacturing a three-dimensional (3D) memory structure for a memory cell includes: providing a substrate, the substrate including a plurality of oxide layers and a plurality of nitride layers. The plurality of oxide layers and the plurality of nitride layers are alternately stacked in a first direction. The method includes: etching a plurality of double-channel holes in the plurality of oxide layers and the plurality of nitride layers. The plurality of double-channel holes extend in the first direction. The plurality of double-channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction. The method includes etching back a plurality of nitride layers in a first region at the ends of the plurality of double-channel holes between the plurality of oxide layers. The method includes partially etching back a plurality of nitride layers in a second region at the sides of the plurality of double-channel holes between the oxide layers. The method includes depositing a blocking dielectric layer on an inner surface within the plurality of double-channel holes, on an inner surface of the plurality of oxide layers in the first region, and on an inner surface of the plurality of oxide layers and the plurality of nitride layers in the second region.

[0020] In other features, the plurality of dual channel holes have a peanut-shaped cross-section. The method includes depositing a material within the plurality of dual channel holes. The method includes etching the material to define a self-aligned contact within a first region between ends of the plurality of dual channel holes.

[0021] In other features, the method includes depositing a charge trapping layer on opposite sides of the self-aligned contact in the first region. The charge trapping layer is also deposited into the second region adjacent to the blocking dielectric layer.

[0022] In other features, the method includes depositing a gate oxide layer on the plurality of oxide layers and the charge trapping layer within the plurality of dual channel holes. The method includes depositing a polysilicon layer within the plurality of dual channel holes. The polysilicon layer includes P - The polysilicon layer defines a first cavity and a second cavity extending in a first direction within the plurality of double channel holes.

[0023] In other features, the method includes depositing N in first and second holes of the plurality of dual channel holes. + layer.

[0024] A three-dimensional (3D) memory structure for a memory cell includes a substrate, the substrate including a plurality of spaced-apart oxide layers and a plurality of dual-channel holes etched in the plurality of oxide layers. The plurality of dual-channel holes extend through the plurality of oxide layers in a first direction. The plurality of dual-channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction. A first region is located at an end of a neighbor of the plurality of dual-channel holes between neighboring ones of the plurality of oxide layers. A second region is located at a side of a neighbor of the plurality of dual-channel holes between neighboring ones of the plurality of oxide layers. A barrier layer is located in the first region and has an I-shaped cross-section, and is located in the second region and has a C-shaped cross-section.

[0025] In other features, the plurality of dual channel holes have a peanut-shaped cross section. The metal layer is disposed within the C-shaped cross section of the barrier layer. The metal layer comprises tungsten.

[0026] In other features, the charge trapping layer is disposed on an outer surface of the C-shaped cross section of the blocking layer and an outer surface of the I-shaped cross section of the blocking layer. The gate oxide layer is disposed on the exposed portion of the charge trapping layer and the plurality of oxide layers within the plurality of dual channel holes. The polysilicon layer is disposed on the gate oxide layer within the plurality of dual channel holes. The polysilicon layer includes P - The polysilicon layer has an 8-shaped cross section in the second direction. The polysilicon layer defines a first cavity and a second cavity extending in the first direction in the plurality of double channel holes. + The layer is disposed within the first cavity and the second cavity of the plurality of dual channel holes.

[0027] A method for manufacturing a three-dimensional (3D) memory structure for a memory cell includes: providing a substrate, the substrate including a plurality of oxide layers and a plurality of nitride layers. The plurality of oxide layers and the plurality of nitride layers are alternately stacked in a first direction. The method includes: etching a plurality of double-channel holes in the plurality of oxide layers and the plurality of nitride layers. The plurality of double-channel holes extend in the first direction. The plurality of double-channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction. The method includes etching back a plurality of nitride layers in a first region at ends of adjacent ones of the plurality of double-channel holes between the plurality of oxide layers, and etching back a plurality of nitride layers in a second region at sides of adjacent ones of the plurality of double-channel holes between the oxide layers. The method includes depositing a self-aligned contact layer on inner surfaces of the plurality of double-channel holes, and on surfaces of the plurality of oxide layers and the plurality of nitride layers in the first region and the second region.

[0028] In other features, the plurality of dual channel holes have a peanut-shaped cross-section. The method includes etching the nitride layer in a first region and a second region of the plurality of dual channel holes. The method includes selectively depositing a barrier layer on surfaces of the plurality of dual channel holes in the first region and the second region. The barrier layer has an I-shaped cross-section in the first region and a C-shaped cross-section in the second region. The barrier layer includes a dielectric material.

[0029] In other features, the method includes etching a self-aligned contact layer. The method includes depositing a metal layer on an inner surface of a barrier layer having a C-shaped cross-section. The metal layer includes tungsten. The method includes depositing a charge trapping layer on an outer surface of the barrier layer having a C-shaped cross-section and on two opposite surfaces of the barrier layer having an I-shaped cross-section. The method includes depositing a gate oxide layer on the charge trapping layer within a plurality of dual-channel holes. The method includes depositing a polysilicon layer on the gate oxide layer within a plurality of dual-channel holes. The polysilicon layer includes P - The polysilicon layer defines a first cavity and a second cavity extending in a first direction within the plurality of double channel holes.

[0030] In other features, the method includes depositing N in first and second holes of the plurality of dual channel holes. + layer.

[0031] A method for fabricating a three-dimensional (3D) memory structure of a memory cell includes etching a plurality of holes into a substrate in a first direction. The substrate includes alternating layers of a first material and a second material stacked in the first direction. The method includes depositing a mask layer to mask pairs of holes in the plurality of holes while leaving one hole unmasked between every two pairs of pairs of holes in the plurality of holes. The method includes depositing a dielectric material into the unmasked holes in the plurality of holes, etching the mask layer to expose the pairs of holes in the plurality of holes, and isotropically etching the pairs of holes in the plurality of holes to form a plurality of double channel holes extending in the first direction.

[0032] In other features, the plurality of dual channel holes have a peanut-shaped cross-section in a second direction transverse to the first direction. The substrate includes alternating oxide layers and nitride layers. The first material includes an oxide and the second material includes polysilicon.

[0033] In other features, the method includes etching polysilicon within the plurality of dual-channel holes to recess the polysilicon relative to the oxide. The method includes depositing an inter-polysilicon dielectric layer on inner surfaces of the plurality of dual-channel holes. The inter-polysilicon dielectric layer and the plurality of dual-channel holes have a peanut-shaped cross-section.

[0034] In other features, the method includes depositing a floating gate layer on an inner surface of the inter-poly dielectric layer. The floating gate layer defines a first cavity and a second cavity extending in a first direction.

[0035] In other features, the method includes etching back the floating gate layer to further define the first cavity and the second cavity. The method includes depositing a gate oxide layer in the first cavity and the second cavity. The method includes depositing polysilicon in the first cavity and the second cavity. The plurality of holes are arranged in a plurality of lines that are evenly spaced apart. The isotropic etching includes atomic layer etching. The isotropic etching includes free radical etching. The plurality of holes have an elliptical cross-section in a first direction. The memory cell of the 3D memory structure includes a floating gate NOR memory cell.

[0036] A three-dimensional (3D) memory structure for a memory cell includes a substrate including alternating layers of a first material and a second material stacked in a first direction. The second material is different from the first material. A plurality of dual-channel holes extend into the substrate in the first direction and have a peanut-shaped cross-section in a second direction transverse to the first direction. A plurality of isolation pillars extend in the first direction and each isolation pillar is disposed between a pair of dual-channel holes.

[0037] In other features, the first material comprises an oxide and the second material comprises a nitride. The first material comprises an oxide and the second material comprises polysilicon. The inter-polysilicon dielectric layer is disposed on the inner surface of the plurality of dual-channel holes. The inter-polysilicon dielectric layer has a peanut-shaped cross-section in the second direction. The floating gate layer is disposed on the inner surface of the inter-polysilicon dielectric layer and defines a first cavity and a second cavity extending in the first direction within the plurality of dual-channel holes.

[0038] In other features, a gate oxide layer is disposed on an inner surface of a floating gate layer within a first cavity and a second cavity within the plurality of dual channel holes. A polysilicon layer is disposed on the gate oxide layer within the first cavity and the second cavity. The polysilicon is recessed relative to the oxide. The memory cell comprises a floating gate NOR memory cell.

[0039] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings.The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0041] Figure 1A FIG. 1 is a circuit diagram of an example of a three-terminal NOR memory device.

[0042] Figure 1BA perspective view of an example of a three-dimensional (3D) vertical two-terminal memory device.

[0043] FIG. 2A to FIG. 2C are side cross-sectional views of several examples of three-terminal memory devices including ferroelectric RAM, NOR flash memory, and spin-orbit torque RAM.

[0044] Figure 3A and Figure 3B A three-dimensional (3D) vertical two-terminal memory device.

[0045] 4A to 6B is a cross-sectional view showing the fabrication of an example of a three-dimensional vertical three-terminal memory device according to the present disclosure.

[0046] Figure 6C A mapping diagram of a two-dimensional (2D) memory device on a three-dimensional (3D) memory device is shown.

[0047] Fig.6D Flowchart of an example of a method of a three-dimensional vertical three-terminal memory device according to the present disclosure.

[0048] Fig. 7A To display FIG. 7B to FIG. 7I Plan views of the x-cutting orientation and the y-cutting orientation in the cross-sectional view.

[0049] FIG. 7B to FIG. 7I is a cross-sectional view showing the fabrication of an example of a three-dimensional (3D) vertical three-terminal memory device according to the present disclosure.

[0050] Figure 7J Flowchart of an example of a method for manufacturing a three-dimensional (3D) vertical three-terminal memory device according to the present disclosure.

[0051] FIG. 8A to FIG. 8H is a cross-sectional view showing the fabrication of an example of a three-dimensional (3D) vertical three-terminal memory device according to the present disclosure.

[0052] Fig.8I Flowchart of an example of a method for manufacturing a three-dimensional (3D) vertical three-terminal memory device according to the present disclosure.

[0053] Figures 9A to 9C Stereo and plan views showing an example of the generation of a dual channel hole.

[0054] Fig.10 is a plan view showing an example of the generation of a dual channel hole according to the present disclosure.

[0055] Fig.11A and Fig. 11BExamples of isotropic etch margins in barrier-through slits and barrier-through channel holes are shown.

[0056] FIG. 12A to FIG. 12D An example of a spacer column disposed between dual channel holes according to the present disclosure is shown.

[0057] Fig.12E is a flow chart showing an example of a method for manufacturing an isolation column and a dual channel hole according to the present disclosure.

[0058] FIG. 13A to FIG. 13D is a plan view showing the fabrication of an example of a floating gate three-dimensional (3D) NOR memory device according to the present disclosure.

[0059] FIG. 14A to FIG. 14D is a cross-sectional view showing an example of fabrication of a floating gate three-dimensional (3D) NOR device according to the present disclosure.

[0060] Fig.15 Flowchart of an example of a method for manufacturing a floating gate three-dimensional (3D) NOR device according to the present disclosure.

[0061] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0062] A three-dimensional (3D) three-terminal memory device according to the present disclosure includes three terminals for addressing each memory cell. The method described herein can be used to manufacture a three-dimensional (3D) three-terminal memory device and integrate the third terminal in a self-aligned manner in the vertical direction using etching and deposition. The three-dimensional (3D) three-terminal memory device uses a hole etching method rather than a line etching method generally used in a cross-point array. This method allows expansion to more layers than the line etching method, thereby increasing storage density and reducing costs.

[0063] A three-dimensional (3D) three-terminal memory device includes a NOR device instead of a NAND device. In NAND devices and NOR devices, a word line is connected to each memory cell. In a NAND device, a bit line is connected to a source / drain chain. In a NOR device, a bit line is connected to each other device (in a design with a reference cell). In a NAND device, there are no individual source / drain connections. In a NOR device, each device pair is connected to ground. A NAND device is a two-terminal device. A NOR device is a three-terminal device.

[0064] In the following description, Figure 1A As shown, a three-dimensional (3D) vertical structure includes a three-terminal NOR memory device. Figure 1B, an example of a bit-addressable two-terminal memory device 100 is shown. The memory device 100 has a plurality of word lines 110-1, 110-2, ... and 110-W or parallel layers (W here is an integer greater than two, and W may be greater than 25, 50, 75 or 100) arranged on parallel planes (collectively referred to as word lines 110). The memory device 100 further includes a plurality of bit lines 120-1, 120-2, ... and 120-B (B here is an integer greater than two) (collectively referred to as bit lines 120), which extend in a first direction parallel to the plane of the parallel word line planes.

[0065] The memory device 100 further includes a plurality of select lines 124-1, 124-2, ... and 124-S (where S is an integer greater than two) extending in a second direction parallel to the plane of the parallel word line plane (e.g., perpendicular to the first direction) (collectively referred to as select lines 124). The memory device 100 further includes pillar electrodes 130-11, 130-12, ... and 130-WB (collectively referred to as pillar electrodes 130) extending in a direction parallel to the parallel word line plane. The memory device 134 is disposed at the intersection of the pillar electrode 130 and the word line 110.

[0066] Now refer to FIG. 2A to FIG. 2C , a variety of three-terminal memory devices can be used for the three-dimensional (3D) three-terminal memory described herein. Although the foregoing description is about three-terminal NOR flash memory, other types of memory cells can also be used. Figure 2A , a ferroelectric field effect transistor (FeFET) memory cell 210 is shown. The FeFET memory cell 210 includes a source 212, a gate 214, and a drain 216. A ferroelectric stack 220 is disposed between the gate 214 and a layer 222 located in bulk silicon 224. The FeFET memory cell 210 operates about as fast as DRAM.

[0067] exist Figure 2B , a NOR flash memory cell 230 is shown. The NOR flash memory cell 230 includes a source 212, a gate 214, and a drain 216. A charge trapping stack 234 is disposed between the gate 214 and a layer 236 located in the bulk silicon 224. The NOR flash memory cell 230 operates faster than NAND memory.

[0068] exist Figure 2C , a spin-orbit torque (SOT) magnetoresistive (MRAM) memory cell 240 is shown. The SOT MRAM memory cell 240 includes a source 212, a gate 214, and a drain 216. A SOT stack 250 is disposed between the gate 214 and a layer 252 located in the bulk silicon 224. The operation of the SOT MRAM memory cell 240 is faster than that of the SST MRAM.

[0069] Reference now Figure 3A and Figure 3B , shows a two-terminal memory device. Adding a third terminal to each memory cell typically introduces a 50% bit density penalty due to the third terminal. Figure 3A and Figure 3B The device shown becomes a three-terminal device, and the systems and methods described herein will include different pillar electrodes (source and drain pillar electrodes). The systems and methods described herein configure transistors between the pillar electrodes and bring the pillar electrodes together to reduce the losses caused by the third terminal.

[0070] As will be further described below, a three-dimensional (3D) vertical three-terminal memory device according to the present disclosure reduces the density loss associated with a three-terminal device. In some embodiments, the spacing of at least some of the pillar electrodes 130 is reduced from the same distance d1 to a non-identical distance d2 (e.g., in a dual-channel hole described further below), where d2 <d1。

[0071] Reference now 4A to 6B , showing the fabrication of a three-dimensional (3D) vertical three-terminal memory device. Figure 4A In the embodiment, a plan view of a substrate 400 includes an oxide layer 410 having a plurality of dual channel holes 404. The plurality of dual channel holes 404 have a peanut-shaped cross section. The plurality of dual channel holes 404 are used to reduce the density loss caused by the third terminal. The substrate 400 includes a silicon dioxide (SiO2) layer or an oxide layer 410 and a silicon nitride (Si x N y ) layers 414 are alternately stacked in a first direction (eg, ONON . . . ). The oxide layer 410 is etched in a first direction or a vertical direction and the nitride layer 414 is etched to define the double channel hole 404 .

[0072] exist Figure 4B In the embodiment, the nitride layer 414 is isotropically etched in the dual channel hole 404 to etch back the exposed portion of the nitride layer 414 in a second or horizontal direction relative to the oxide layer 410. The second direction is transverse to the first direction. Figure 4C In the embodiment of the present invention, a blocking oxide layer, a nitride layer, and a gate oxide layer (shown together as a multilayer stack 440) are deposited on the oxide layer 410 and the nitride layer 414, as will be further described below. The multilayer stack 440 defines a first cavity or vertical cavity in the dual channel hole having a peanut-shaped cross-section (e.g., a profile resembling a figure 8).

[0073] exist Figure 5A In the -The trench polysilicon is filled and etched back to generate P on the inner surface of the multilayer stack 440. - The channel polysilicon layer 500 is formed after etching back. - The channel polysilicon layer 500 defines adjacent vertical holes in the double channel hole 404 and has a figure-8 shaped cross-section. In some examples, the adjacent vertical holes have an elliptical or circular cross-section. Figure 5B In, N + A wordline / bitline layer 510 is deposited in adjacent vertical holes within each dual channel hole.

[0074] Figure 5C In the embodiment, an etch is performed to etch the nitride layer 414 between the oxide layers 410 as shown at 550 to define word lines. In some examples, the substrate is cut or diced at one or more locations to expose the nitride layer 414 before the etching is performed.

[0075] Fig. 6A In FIG. 5 , a conductive filler 600 is deposited into the opening previously occupied by the nitride layer 414 shown at 550 to form a word line. In some embodiments, the conductive filler comprises tungsten (W). Figure 6B In FIG. 6 , a cross-section through a substrate at a layer of conductive filler 600 is shown. Figure 6C , a two-dimensional (2D) memory device is shown mapped onto a three-dimensional (3D) memory device.

[0076] Fig.6D , a method 680 for manufacturing a three-dimensional (3D) vertical three-terminal memory device is shown. At 682, a substrate 400 is provided, and the substrate 400 initially includes a stack of oxide layers 410 and nitride layers 414 alternating with each other. At 684, a dual channel hole is formed. In some embodiments, an intervening isolation hole is formed between the dual channel holes (described below). At 686, the nitride layer 414 is isotropically etched to make the nitride layer 414 concave. At 688, a multilayer stack 440 (including a blocking oxide layer, a charge trapping layer (such as a nitride layer), and a gate oxide layer) is deposited in the dual channel hole 404. At 690, P is deposited. - The channel polysilicon layer 500 is deposited. In 692, N + Wordline / bitline layer 510. In some examples, the substrate is cut or diced at one or more locations to expose the nitride layer prior to etching. At 694, nitride layer 414 is etched. At 696, a conductive filler 600, such as tungsten, is deposited at the previous location of nitride layer 414 to form a wordline.

[0077] Reference now Fig. 7A , showing FIG. 7B to FIG. 7I The x-cut and y-cut orientations of the cross-sectional view. FIG. 7B to FIG. 7I In FIG. 1 , a cross-sectional view of the fabrication of a three-dimensional (3D) vertical three-terminal memory device is shown. Figure 7B In the figure, the substrate is shown after high aspect ratio etching of the dual channel holes. Figure 7C , the substrate is shown after etching to make the nitride layer 414 concave. In some examples, the nitride layer 414 in the first region at the end of the double channel hole 404 between the oxide layers is removed, and the nitride layer 414 in the second region adjacent to the side of the double channel hole 404 between the oxide layers is partially removed.

[0078] exist Fig.7D , the substrate is shown after a blocking dielectric layer 708 is deposited within the dual channel hole 404. The blocking dielectric layer 708 is deposited on the nitride layer 414 and the oxide layer 410 in the second region and on the oxide layer 410 in the first region. A self-aligned contact (SAC) oxide layer 710 is deposited on the blocking dielectric layer 708 within the dual channel hole 404.

[0079] exist Fig. 7E , the substrate is shown after etching is performed to recess the SAC oxide layer 710. The SAC oxide layer 710 in the second region is removed except for the middle position between the oxide layers 410 in the first region in the y-cross-sectional view. Figure 7F , the substrate is shown after a nitride charge trapping layer 722 is deposited (and etched to recess the charge trapping layer 722) within the dual channel hole 404. A gate oxide layer 730 is deposited on the charge trapping layer 722 within the dual channel hole 404.

[0080] Figure 7G In FIG. 4 , P is deposited in the double channel hole 404. - The channel layer 740 is formed into a concave substrate. - N + Filler layer 750. In some examples, one or more locations of the substrate are cut or diced to expose the nitride layer for subsequent etching steps. Figure 7H , the substrate is shown in an x-section view at location 754 after the nitride layer 414 has been etched. Fig.7I , a deposition of a conductive fill 760 at location 754 is performed to fill the location previously occupied by the nitride layer 414 and to create a word line. In some examples, the conductive fill 760 includes tungsten (W).

[0081] Reference now Figure 7J, shows a method 780 for manufacturing a three-dimensional (3D) vertical three-terminal memory device. In 781, the nitride layer 414 is recessed (after defining the dual channel hole using HAR etching). In 782, a blocking dielectric layer 708 is deposited. In 784, a SAC oxide layer 710 is deposited and etched back. In 785, a charge trapping layer 722 is deposited. In 786, a gate oxide layer 730 is deposited. In 790, a P - The channel layer 740 is concave. In 792, N + Filler layer 750. At 793, one or more locations of the substrate are selectively cut or diced to expose the nitride layer for subsequent etching steps. At 794, the nitride layer 414 adjacent to the charge trapping layer 722 is etched. At 796, the locations of the previous nitride layer 414 are filled with conductive filler 760.

[0082] Reference now Figures 8A to 8H , showing a cross-sectional view of the fabrication of a three-dimensional (3D) vertical three-terminal memory device. Fig. 8A In FIG. 1 , a substrate is shown after high aspect ratio (HAR) etching to define multiple dual channel holes. Figure 8B , a substrate is shown that has been etched to recess the nitride layer 414. The first region 802 is located at the end between the multiple oxide layers between the adjacent ones in the multiple double channel holes. The second region 804 is located at the side between the multiple oxide layers between the adjacent ones in the multiple double channel holes. Since the etching of the first region 802 occurs on both sides, the nitride layer 414 after etching is located in the middle of the first region 802. Since the etching of the second region 804 only occurs on one side, the nitride layer 414 is only etched from the side shown in the figure. Figure 8C In the embodiment, the SAC oxide layer 808 is deposited to shape the dielectric barrier layers 810 and 812 to be deposited later (see Fig. 8E ).

[0083] In some examples, one or more locations of the substrate are selectively cut or diced to expose the nitride layer 414. Fig.8D In, the nitride layer 414 is etched. Fig. 8E In the process, dielectric barrier layers 810, 812 are deposited and patterned by the SAC oxide layer 808. Thereafter, the SAC oxide layer 808 is etched. Fig.8F In the embodiment, a conductive filler 824 is deposited. Figure 8G In, nitride is deposited and etched back to form charge trapping layers 820, 822. Gate oxide layer 826 is deposited. In Figure 8H In the figure, P - The substrate after the channel layer 830 is deposited and recessed. +The filler layer 834 is deposited on the P - On the channel layer 830 .

[0084] Reference now Fig.8I , a method 880 for manufacturing a three-dimensional (3D) vertical three-terminal memory device is shown. At 882, the nitride layer 414 is recessed (after defining the dual channel hole using HAR etching). At 884, a SAC oxide layer 808 is deposited. At 885, one or more locations of the substrate are selectively cut or diced to expose the nitride layer 414 for a subsequent etching step. At 886, the nitride layer 414 is etched. At 888, dielectric barrier layers 810, 812 are deposited and the SAC oxide layer 808 is etched. At 890, a conductive filler 824 is deposited. At 892, charge trapping layers 820, 822 are deposited and recessed. A gate oxide layer 826 is deposited. At 896, a P - Then, in 898, N + Filling layer 834.

[0085] Reference now Figures 9A to 9C , which can cause problems when etching dual channel holes with high aspect ratios. When etching progresses to the lower wordline layers, Fig. 9B The ideal shape of the dual channel hole 404 shown in FIG. 4 may be distorted. For example, Fig. 9B The half-circle shape of the double channel hole 404 in the lower word line layer is twisted into Fig. 9C The double channel hole 404' (in an oval shape) in FIG. 4A . This distortion will cause defects and / or reduce performance.

[0086] Reference now Figures 10 to 11B , a double channel hole can be formed to prevent distortion. Fig.10 In , circular high aspect ratio (HAR) holes are first masked and etched, followed by an isotropic oxide etch and an isotropic nitride etch. Fig.11A and Fig. 11B , isotropic etching margins in the barrier-through slit at 1100 and the barrier-through channel hole at 1110 are shown. In some examples, isotropic atomic layer etching (ALE) or radical etching is performed to precisely control etching at these locations and maintain etching margins.

[0087] Reference now FIG. 12A to FIG. 12D , isolation columns can be configured between the double channel holes. Fig. 12A In the embodiment of the present invention, a plurality of circular holes 1210 are etched in a substrate. Adjacent holes 1210-1 are associated with dual channel holes, and holes 1210-2 are associated with isolation columns. Holes 1210-2 are arranged between adjacent dual channel holes. Fig. 12BIn the embodiment of the present invention, a mask layer 1220 is deposited on hole 1210-1 to prevent dielectric deposition in the dual channel hole. Hole 1210-2 remains open. Fig. 12C In the embodiment, dielectric material 1230 is deposited in hole 1210-2 to form isolation column 1232 and then mask layer 1220 is removed. Fig.12D In FIG. 4 , an isotropic etch of hole 1210 - 1 is performed to generate dual channel hole 404 .

[0088] Reference now Fig.12E , a method 1270 for manufacturing the isolation column 1232 and the dual channel hole 404 is shown. In 1274, the HAR circular hole 1210 is etched at a predetermined position of the substrate. In some embodiments, the HAR circular holes 1210 are etched while maintaining the same spacing between each other. In 1278, a mask layer 1220 is deposited to cover the selected holes 1210-2 in the holes 1210-2 corresponding to the dual channel hole 404. In 1282, the isolation column 1232 is generated by depositing a dielectric in the hole 1210-2. In 1286, the mask layer 1220 is removed. In 1290, the hole 1210-1 corresponding to the dual channel hole 404 is widened by performing isotropic oxide etching and isotropic nitride etching using ALE or free radical etching.

[0089] Reference now FIG. 13A to FIG. 13D , showing the fabrication of a floating gate three-dimensional (3D) NOR device. Instead of using a substrate comprising alternating ONON layers, the substrate comprises an alternating stack of oxide and polysilicon layers (or OPOP). Fig.13A In FIG. 1 , a polysilicon layer 1310 having a plurality of holes 1312 is shown. Figures 14A to 14D The x-cut and y-cut cross-sections in the side view of FIG. The adjacent hole 1312-1 corresponds to the dual channel hole, and the hole 1312-2 corresponds to the isolation column 1316 filled with dielectric 1314. As described above, a mask layer is used to close the hole 1312-1 corresponding to the dual channel hole. The dielectric is deposited into the hole 1312-2 corresponding to the isolation column 1316. Then Fig. 13B In the embodiment, the hole 1312-1 is etched by isotropic etching of the oxide layer and isotropic etching of the polysilicon layer to generate a double channel hole 1317 having a peanut-shaped cross section.

[0090] Fig. 13C In the embodiment, an inter-polysilicon dielectric (IPD) layer 1330 is deposited on the side surface of the dual channel hole 1317. The IPD layer 1330 is located within the dual channel hole 1317 and also has a peanut-shaped cross section. Fig.13DIn the embodiment of the present invention, a floating gate 1332 is deposited and etched back. The floating gate 1332 has a figure-eight cross section and defines a first hole and a second hole extending vertically. A gate oxide layer 1340 is deposited and partially fills the first hole and the second hole. A channel polysilicon layer 1350 is deposited into the first hole and the second hole to fill the first hole and the second hole.

[0091] exist Fig.14A , the substrate is shown after the HAR circular hole in the oxide layer 1352 and the polysilicon layer 1310 is etched and the isolation column 1316 is deposited in the hole 1312-2. Fig. 14B In , etching is performed and the polysilicon layer 1310 is recessed. Fig. 14C , the deposition of the IPD layer 1330 is shown. Fig. 14C In the process, a floating gate 1332 is deposited and etched back. A gate oxide layer 1340 is deposited. A channel polysilicon layer 1350 is deposited.

[0092] Reference now Fig.15 , a method for manufacturing a floating gate three-dimensional (3D) NOR device is shown. In 1520, a HAR circular hole is etched into a substrate comprising alternating oxide layers 1352 and polysilicon layers 1310. In 1524, a mask is applied to the hole 1312-1 corresponding to the dual channel hole. In 1526, a dielectric 1314 is filled in the hole 1312-2 corresponding to the isolation hole. In 1528, the mask layer is removed. In 1530, an isotropic etching of the oxide layer 1352 and the polysilicon layer 1310 is performed to form a dual channel hole 1317. In 1532, etching is performed to make the polysilicon layer 1310 concave relative to the oxide layer 1352. In 1536, an inter-polysilicon dielectric (IPD) layer 1330 is deposited. In 1538, the floating gate 1332 is deposited and etched back. In 1548, a gate oxide layer 1340 is deposited. At 1554, the channel polysilicon layer 1350 is deposited.

[0093] As can be understood, the above-mentioned etching of oxide is performed selectively. That is, the etching of oxide can be performed using a process that etches oxide more than other exposed materials such as nitrides, polysilicon, etc. In some examples, the selectivity of the oxide etching process is greater than 4:1, 10:1, 50:1, or 100:1. The above-mentioned etching of nitride is performed selectively. That is, the etching of nitride can be performed using a process that etches nitride more than other exposed materials such as oxides, polysilicon, etc. In some examples, the selectivity of the nitride etching process is greater than 4:1, 10:1, 50:1, or 100:1. Similarly, the above-mentioned polysilicon etching is performed selectively. That is, the etching of polysilicon can be performed using a process that etches polysilicon more than other exposed materials such as nitrides, oxides, etc. In some examples, the selectivity of the polysilicon etching process is greater than 4:1, 10:1, 50:1, or 100:1. Various systems and methods for selectively etching oxides, nitrides, and polysilicon can be found in commonly assigned patents and patent applications.

[0094] Examples of free radical etching are shown and described in commonly assigned U.S. patent application Ser. No. 15 / 271,381, filed Sep. 21, 2016, entitled “Systems and Methods for Ultrahigh Selective Nitride Etch”; commonly assigned U.S. patent application Ser. No. 15 / 426,241, filed Feb. 7, 2017, entitled “Systems and Methods for Selectively Etching Film”; commonly assigned U.S. patent application Ser. No. 15 / 845,206, filed Dec. 18, 2017, entitled “Systems and Methods for Metastable Activated Radical Selective Strip and Etch Using Dual Plenum Showerhead”; and commonly assigned U.S. patent application Ser. No. 9,837,286, filed Feb. 3, 2016, entitled “Systems and Methods for Selectively Etching Tungsten in a Downstream Reactor" which are incorporated herein by reference in their entirety.

[0095] Examples of high aspect ratio etching of dielectric materials can be found in the following documents: the commonly assigned PCT patent with patent number No. WO2019178030A1 and invention name “Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics” applied on March 12, 2019, the entire content of which is incorporated herein by reference.

[0096] In some examples, deposition of materials such as oxides and / or nitrides is performed using a conformal process such as atomic layer deposition (ALD). Examples of conformal oxide and nitride deposition can be found in commonly assigned U.S. Patent No. 9,502,238, filed on April 3, 2015, entitled “Deposition of Conformal Films by Atomic Layer Deposition and Atomic Layer Etch,” and commonly assigned U.S. Patent No. 8,728,955, filed on March 1, 2012, entitled “Method Of Plasma Activated Deposition Of A Conformal Film On A Substrate Surface,” the entire contents of which are incorporated herein by reference.

[0097] Examples of tungsten deposition can be found in the following documents: the commonly assigned PCT patent No. WO19036292 A1 filed on August 10, 2018 and entitled “Metal Fill Process for Three-Dimensional Vertical NAND Wordline”, the commonly assigned U.S. patent No. 9,082,826 filed on May 22, 2014 and entitled “Methods and Apparatuses for Void-Free Tungsten Fill in Three-Dimensional Semiconductor Features”, and the commonly assigned U.S. patent No. 10,214,807 filed on June 2, 2016 and entitled “Atomic Layer Deposition of Tungsten for Enhanced Fill and Reduced Substrate Attack”, the entire contents of which are incorporated herein by reference.

[0098] In addition to selective etching, systems and methods for selective deposition of tungsten, oxides, nitrides, and polysilicon may also be used. Selective deposition of these materials involves deposition of materials on some exposed materials of the substrate more than on other exposed materials of the substrate. In some examples, the selectivity of a deposition process for a deposited material on a selected material of the substrate relative to other exposed materials of the substrate is greater than 4:1, 10:1, 50:1, or 100:1. Examples of selective deposition of tungsten can be found in the following literature: U.S. Patent No. 8,778,797, filed on September 23, 2011, commonly assigned, entitled "Systems And Methods For Selective Tungsten Deposition In Vias." Examples of selective deposition of oxide or nitride can be found in the following documents: U.S. Patent No. 10,199,212, filed on May 9, 2018, and entitled “Selective Growth of Silicon Oxide or Silicon Nitride on Silicon Surfaces in the Presence of Silicon Oxide”, commonly assigned, U.S. Patent Publication No. 20190043876A1, filed on August 1, 2018, and entitled “Selective Deposition of SiN on Horizontal Surfaces”, the entire contents of which are incorporated herein by reference.

[0099] The foregoing description is merely illustrative in nature and is by no means intended to limit the present disclosure, its application or use. The broad teachings of the present disclosure can be implemented in various forms. Therefore, although the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, because when studying the drawings, the specification and the appended claims, other modifications will become apparent. It should be understood that, without changing the principles of the present disclosure, one or more steps in the method can be performed in different orders (or simultaneously). In addition, although each embodiment is described above as having certain features, any one or more of those features described relative to any embodiment of the present disclosure can be implemented in the features of any other embodiment and / or combined with the features of any other embodiment, even if the combination is not clearly described. In other words, the described embodiments are not mutually exclusive, and the replacement of one or more embodiments with each other remains within the scope of the present disclosure.

[0100] Various terms are used to describe the spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless the relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the above disclosure, the relationship can be a direct relationship, in which there are no other intervening elements between the first and second elements, but can also be an indirect relationship, in which there are one or more intervening elements (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C."

Claims

1. A three-dimensional (3D) memory structure for a three-terminal NOR memory cell, comprising: Multiple oxide layers; multiple word line layers; wherein the plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction; and a plurality of dual channel holes extending in the first direction through the plurality of oxide layers and the plurality of word line layers; wherein the plurality of dual channel holes have an elliptical cross section in a second direction transverse to the first direction; and The middle portion of the elliptical cross section is contracted. 2 . The 3D memory structure of claim 1 , wherein the cross-section of the oval is similar to the shape of a figure 8. 3 . 3 . The 3D memory structure of claim 1 , wherein the elliptical cross-section comprises two partially intersecting ellipses. 4 . The 3D memory structure of claim 1 , wherein within the plurality of dual channel holes, the plurality of word line layers are recessed relative to the plurality of oxide layers. 5 . The 3D memory structure of claim 1 , further comprising a multi-layer stack deposited on inner surfaces of the plurality of dual channel holes and defining a first cavity extending in the first direction. 6 . The 3D memory structure of claim 5 , wherein the first cavity has the elliptical cross-section in the second direction.

7. The 3D memory structure of claim 5, wherein the multi-layer stack comprises a blocking oxide layer, a charge trapping layer, and a gate oxide layer.

8. The 3D memory structure of claim 5, wherein the multi-layer stack comprises a blocking oxide layer, a ferroelectric layer, and a gate oxide layer.

9. The 3D memory structure of claim 5, wherein the multi-layer stack comprises a blocking oxide layer, a spin-orbit torque (SOT) layer, and a gate oxide layer. 10 . The 3D memory structure of claim 5 , further comprising a polysilicon layer disposed on an inner surface of the first cavity. 11 . The 3D memory structure of claim 10 , wherein the polysilicon layer defines a second cavity and a third cavity extending in the first direction. 12 . The 3D memory structure of claim 11 , wherein the second cavity and the third cavity have elliptical cross-sections in the second direction.

13. The 3D memory structure of claim 10, wherein the polysilicon layer comprises P - layer. 14 . The 3D memory structure of claim 10 , wherein the polysilicon layer has an 8-shaped cross section in the second direction.

15. The 3D memory structure according to claim 10, further comprising N + Layer, the N + A layer is disposed within the second cavity and within the third cavity. 16 . The 3D memory structure of claim 1 , further comprising pillar electrodes for two of the three terminals of the three-terminal NOR memory cell and a transistor disposed between the pillar electrodes. 17 . The 3D memory structure of claim 1 , further comprising a spacer pillar disposed between the dual channel holes.

18. A method for fabricating a three-dimensional (3D) memory structure for a three-terminal NOR memory cell, comprising: providing a substrate, the substrate comprising a plurality of oxide layers and a plurality of nitride layers, wherein the plurality of oxide layers and the plurality of nitride layers are alternately stacked in a first direction; and etching a plurality of dual channel holes in the plurality of oxide layers and the plurality of nitride layers, wherein the plurality of dual channel holes extend in the first direction, in, The plurality of dual channel holes have an elliptical cross-section in a second direction transverse to the first direction; and The middle portion of the elliptical cross section is contracted.

19. The method of claim 18, wherein the oval cross-section resembles a figure eight shape.

20. The method of claim 18, wherein the elliptical cross-section comprises two partially intersecting ellipses.

21. The method of claim 18, further comprising etching back the plurality of nitride layers relative to the plurality of oxide layer portions within the plurality of dual channel holes.

22. The method of claim 21, further comprising depositing a multi-layer stack on inner surfaces of the plurality of dual channel holes, wherein the multi-layer stack defines a first cavity extending in the first direction.

23. The method of claim 22, wherein the first hole has an elliptical cross-section in the second direction.

24. The method of claim 22, wherein depositing the multilayer stack comprises depositing a blocking oxide layer, a charge trapping layer, and a gate oxide layer.

25. The method of claim 22, wherein depositing the multilayer stack comprises depositing a blocking oxide layer, a ferroelectric layer, and a gate oxide layer.

26. The method of claim 22, wherein depositing the multilayer stack comprises depositing a blocking oxide layer, a spin-orbit torque (SOT) layer, and a gate oxide layer.

27. The method of claim 22, further comprising depositing a polysilicon layer on inner surfaces of the first cavities within the plurality of dual channel holes.

28. The method of claim 27, wherein the polysilicon layer defines a second cavity and a third cavity extending in the first direction.

29. The method of claim 28, wherein the second hole and the third hole have an elliptical cross-section in the second direction.

30. The method of claim 27, wherein the polysilicon layer comprises P - layer. 31 . The method according to claim 27 , wherein the polysilicon layer has an 8-shaped cross section in the second direction.

32. The method of claim 28, further comprising depositing N in the second cavity and the third cavity. + layer.

33. The method of claim 32, further comprising cutting the substrate to at least partially expose portions of the plurality of nitride layers.

34. The method of claim 33, further comprising etching the plurality of nitride layers.

35. The method of claim 34, further comprising depositing a conductive filler at the etched locations of the plurality of nitride layers.

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