Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a first polar plate of a high-voltage capacitor; at least one interlayer dielectric layer is formed on a first polar plate of the high-voltage capacitor to serve as a dielectric layer of the high-voltage capacitor, a conductive through hole is formed in each interlayer dielectric layer, and the conductive through holes are mutually communicated and communicated with the first polar plate of the high-voltage capacitor to serve as a lead-out channel of the first polar plate of the high-voltage capacitor; etching the interlayer dielectric layer to form a deep groove; forming a first polar plate of the silicon capacitor on the side wall and the bottom of the deep groove, wherein the first polar plate of the silicon capacitor is communicated with the first polar plate of the high-voltage capacitor; forming a dielectric layer of the silicon capacitor on the side wall and the bottom of the deep groove; forming a second polar plate of the silicon capacitor in the deep groove; and forming a second pole plate of the high-voltage capacitor on the interlayer dielectric layer on the top layer. The manufacturing of the high-voltage capacitor and the silicon capacitor is integrated in one process, so that the process steps are saved, the manufacturing cost is saved, and the product competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] During chip design and manufacturing, the process of designing multiple high-voltage functional devices on a single chip can improve product competitiveness.

[0003] High voltage capacitors (HVCAP, voltage is 1000V ~ 6000V) can be integrated on functional semiconductor chips or packaged together with functional semiconductor chips as capacitive isolators and applied to the isolation of different voltage domains, including automotive isolation devices, which allow the safe transmission of electrical signals between different voltage domains.

[0004] Silicon capacitors (SICAP) use semiconductor deep trench technology. Compared with parallel plate capacitors such as MOS capacitors and MIM capacitors, they can greatly improve capacitance density and capacitance, and can save a lot of chip area. Under the same layout area, the actual area of ​​silicon capacitors is the surface area of ​​the entire deep trench. Silicon capacitors have important applications in new energy vehicle battery management systems, drive systems, etc. due to their high stability, high reliability, high density, low thickness, low equivalent series inductance (ESL), and low equivalent series resistance (ESR).

[0005] The above two types of capacitors are capacitive devices with independent structures and functions. Integrating high-voltage capacitors and silicon capacitors in the same process at low cost and improving product competitiveness are technical problems that technical personnel in this field need to solve urgently. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which integrates a high-voltage capacitor and a silicon capacitor in the same process, thereby saving process steps, saving manufacturing costs, and improving product competitiveness.

[0007] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0008] forming a first plate of a high voltage capacitor;

[0009] At least one interlayer dielectric layer is formed on the first electrode plate of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive through hole, and the conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as a lead-out channel of the first electrode plate of the high-voltage capacitor;

[0010] Etching the interlayer dielectric layer to form a deep groove;

[0011] forming a first electrode plate of a silicon capacitor on the sidewall and the bottom of the deep trench, the first electrode plate of the silicon capacitor being connected to the first electrode plate of the high-voltage capacitor; forming a dielectric layer of a silicon capacitor on the sidewall and the bottom of the deep trench, the dielectric layer of the silicon capacitor covering the first electrode plate of the silicon capacitor; forming a second electrode plate of the silicon capacitor in the deep trench, the second electrode plate of the silicon capacitor filling the deep trench; and

[0012] A second electrode plate of the high voltage capacitor is formed on the top interlayer dielectric layer.

[0013] Optionally, the step of forming a first electrode plate of a high voltage capacitor includes:

[0014] Providing a substrate, and forming a bottom interlayer dielectric layer on the substrate;

[0015] forming a first metal layer, wherein the first metal layer covers a portion of the bottom interlayer dielectric layer;

[0016] forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the first metal layer and the bottom interlayer dielectric layer; forming a conductive through hole in the first interlayer dielectric layer connected to the first metal layer;

[0017] A second metal layer is formed, wherein the second metal layer covers a portion of the first interlayer dielectric layer, and the second metal layer is connected to the first metal layer through the conductive via, and the second metal layer serves as a first electrode plate of the high-voltage capacitor.

[0018] Optionally, in a direction perpendicular to the substrate, the first electrode plate of the high-voltage capacitor covers a portion of the first metal layer.

[0019] Optionally, all the interlayer dielectric layers are etched to form deep grooves exposing the first metal layer, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor through the first metal layer.

[0020] Optionally, a metal layer is formed in each interlayer dielectric layer on the first electrode plate of the high-voltage capacitor, the metal layer connects two adjacent conductive through holes, and the metal layer and the conductive through holes together constitute a lead-out channel of the first electrode plate of the high-voltage capacitor.

[0021] Optionally, the substrate includes a first region and a second region, a semiconductor structure is formed in the second region, and the high-voltage capacitor and the silicon capacitor are formed in the first region;

[0022] forming a plurality of interlayer dielectric layers in the second region, and forming a metal layer and a conductive via in each interlayer dielectric layer, wherein the metal layer and the conductive via lead out corresponding electrodes of the semiconductor structure;

[0023] The first electrode plate of the high-voltage capacitor is formed synchronously with the metal layer located on the same layer in the second region, the dielectric layer of the high-voltage capacitor is formed synchronously with the interlayer dielectric layer located on the same layer in the second region, and the lead-out channel is formed synchronously with the metal layer and the conductive through hole located on the same layer in the second region.

[0024] Optionally, the method of etching the interlayer dielectric layer to form a deep trench includes:

[0025] forming a photoresist layer on the top interlayer dielectric layer;

[0026] Exposing and developing the photoresist layer to form a patterned photoresist layer;

[0027] Using the patterned photoresist layer as a mask, etching all interlayer dielectric layers until the first metal layer is exposed; and

[0028] The patterned photoresist layer is removed.

[0029] Optionally, the lead-out terminal of the first plate of the high-voltage capacitor, the lead-out terminal of the first plate of the silicon capacitor, and the lead-out terminal of the second plate of the silicon capacitor are formed simultaneously with the formation of the second plate of the high-voltage capacitor;

[0030] The method of forming a second plate of a high voltage capacitor on a top interlayer dielectric layer comprises:

[0031] forming a conductive material layer, wherein the conductive material layer covers the top interlayer dielectric layer;

[0032] The conductive material layer is etched to expose a portion of the top interlayer dielectric layer, and the conductive material layer directly above the first electrode plate of the high-voltage capacitor is retained as the second electrode plate of the high-voltage capacitor, the conductive material layer on the lead-out channel is retained as the first lead-out end of the first electrode plate of the high-voltage capacitor and the first electrode plate of the silicon capacitor, and the conductive material layer on the second electrode plate of the silicon capacitor is retained as the second lead-out end of the second electrode plate of the silicon capacitor.

[0033] Optionally, the material of the first plate and the second plate of the high-voltage capacitor includes copper, tungsten, aluminum, ruthenium or cobalt, and the material of the dielectric layer of the high-voltage capacitor includes ethyl silicate, borophosphosilicate glass or a low dielectric constant material; the material of the first plate of the silicon capacitor includes titanium nitride, the material of the second plate of the silicon capacitor includes tungsten, and the dielectric layer of the silicon capacitor includes a silicon nitride layer or a stack consisting of silicon oxide-silicon nitride-silicon oxide.

[0034] In order to solve the above technical problem, according to a second aspect of the present invention, a semiconductor device is further provided, which is manufactured by the above-mentioned method for manufacturing a semiconductor device, and the semiconductor device comprises:

[0035] A first plate of a high voltage capacitor;

[0036] At least one interlayer dielectric layer is located on the first electrode plate of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor. A conductive through hole is formed in each interlayer dielectric layer. The conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as an extraction channel for the first electrode plate of the high-voltage capacitor. A deep groove is formed in the interlayer dielectric layer and penetrates the interlayer dielectric layer.

[0037] A first electrode plate of the silicon capacitor is located on the sidewall and bottom of the deep groove, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor;

[0038] A dielectric layer of the silicon capacitor, located on the sidewall and bottom of the deep trench and covering the first electrode plate of the silicon capacitor;

[0039] a second electrode plate of the silicon capacitor, located in the deep trench and filling the deep trench; and

[0040] The second plate of the high voltage capacitor is located on the top interlayer dielectric layer.

[0041] In summary, in the semiconductor device and its manufacturing method provided by the present invention, firstly, a first electrode plate of a high-voltage capacitor is formed, and then at least one interlayer dielectric layer is formed on the first electrode plate as the dielectric layer of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive through hole, and the conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as the lead-out channel of the first electrode plate of the high-voltage capacitor, and then the interlayer dielectric layer is etched to form a deep groove, and then the first electrode plate of the silicon capacitor is formed on the side wall and bottom of the deep groove, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor; the dielectric layer of the silicon capacitor is formed on the side wall and bottom of the deep groove, and the dielectric layer of the silicon capacitor covers the first electrode plate of the silicon capacitor; the second electrode plate of the silicon capacitor is formed in the deep groove, and the second electrode plate of the silicon capacitor fills the deep groove, and then the second electrode plate of the high-voltage capacitor is formed on the top interlayer dielectric layer. The present invention integrates the production of high-voltage capacitors and silicon capacitors in one process, saves process steps, saves production costs, and improves product competitiveness.

[0042] Furthermore, the first plate and the second plate of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.

[0043] In addition, the dielectric layer of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown in weak locations caused by dielectric defects and dielectric uniformity during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0045] Figures 2 to 8 It is a schematic structural diagram of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0046] Description of reference numerals:

[0047] 100-substrate; 101-first metal layer; 102-second metal layer; 103-third metal layer; 104-fourth metal layer; 110-bottom interlayer dielectric layer; 111-first interlayer dielectric layer; 112-second interlayer dielectric layer; 113-third interlayer dielectric layer; 114-fourth interlayer dielectric layer; 115-fifth interlayer dielectric layer; 120-patterned first photoresist layer; 121-deep groove; 130-patterned second photoresist layer; 140-third lead-out terminal; 151-first passivation layer; 152-second passivation layer; 210-first plate of the high-voltage capacitor; 211-conductive through hole; 212-first lead-out terminal; 220-second plate of the high-voltage capacitor; 221-third conductive material layer; 310-first plate of the silicon capacitor; 311-first conductive material layer; 320-dielectric layer of the silicon capacitor; 321-insulating material layer; 330-second plate of the silicon capacitor; 331-second conductive material layer; 332-second lead-out terminal. DETAILED DESCRIPTION

[0048] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0049] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0050] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the method for manufacturing a semiconductor device comprises the following steps:

[0051] S1: forming the first plate of the high voltage capacitor;

[0052] S2: forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor, wherein each interlayer dielectric layer is formed with a conductive through hole, the conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as an outlet channel of the first electrode plate of the high-voltage capacitor;

[0053] S3: etching the interlayer dielectric layer to form a deep groove;

[0054] S4: forming a first electrode plate of a silicon capacitor on the sidewall and the bottom of the deep trench, the first electrode plate of the silicon capacitor being connected to the first electrode plate of the high-voltage capacitor; forming a dielectric layer of a silicon capacitor on the sidewall and the bottom of the deep trench, the dielectric layer of the silicon capacitor covering the first electrode plate of the silicon capacitor; forming a second electrode plate of the silicon capacitor in the deep trench, the second electrode plate of the silicon capacitor filling the deep trench; and

[0055] S5: forming a second electrode plate of the high-voltage capacitor on the top interlayer dielectric layer.

[0056] Figures 2 to 8 FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 , Figures 2 to 8 The method for manufacturing a semiconductor device provided by an embodiment of the present invention is described in detail.

[0057] In step S1, refer to Figure 2 As shown, a first plate 210 of a high voltage capacitor is formed.

[0058] In one embodiment of the present invention, the steps of forming the first electrode plate 210 of the high voltage capacitor include:

[0059] First, step S11 is performed to provide a substrate 100 , and to form a bottom interlayer dielectric layer 110 on the substrate 100 .

[0060] In this embodiment, the material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or silicon on insulator, germanium on insulator; or it can also be other materials, such as III-V compounds such as gallium arsenide. In one embodiment, the substrate 100 is a silicon substrate. The material of the bottom interlayer dielectric layer 110 can be tetraethyl ortho silicate (TEOS), boro-phospho-silicate glass (BPSG), or other suitable dielectric materials, such as low dielectric constant materials (low-k dielectric materials) or any combination of these materials. The bottom interlayer dielectric layer 110 can be formed by any suitable process known to those skilled in the art, such as atomic layer deposition process (ALD), chemical vapor deposition process (CVD), physical vapor deposition process (PVD), etc.

[0061] Next, step S12 is performed to form a first metal layer 101 on the bottom interlayer dielectric layer 110, wherein the first metal layer 101 covers a portion of the bottom interlayer dielectric layer 110. The material of the first metal layer 101 includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt.

[0062] Then, step S13 is performed to form a first interlayer dielectric layer 111 on the first metal layer 101. The first interlayer dielectric layer 111 covers the first metal layer 101 and the bottom interlayer dielectric layer 110. The material and the forming method of the first interlayer dielectric layer 111 can be the same as the material and the forming method of the bottom interlayer dielectric layer 110, but are certainly not limited thereto. Afterwards, the first interlayer dielectric layer 111 is etched to form a through hole exposing the first metal layer 101, and a conductive material is filled in the through hole to form a conductive through hole.

[0063] Next, step S14 is performed to form a second metal layer 102 on the first interlayer dielectric layer 111, wherein the second metal layer 102 covers a portion of the first interlayer dielectric layer 111, and the second metal layer 102 is connected to the first metal layer 101 through the conductive via, and the second metal layer 102 serves as the first electrode 210 of the high-voltage capacitor. Figure 2 As shown, a portion of the second metal layer 102 serves as the first electrode 210 of the high-voltage capacitor, another portion of the second metal layer 102 serves as a portion of the lead-out channel of the first electrode 210, and another portion of the second metal layer 102 is located in an area of ​​the substrate 100 where a semiconductor structure is formed, which will be described in detail later.

[0064] In one embodiment, in a direction perpendicular to the substrate 100, the first electrode 210 of the high-voltage capacitor covers a portion of the first metal layer 101, that is, the first electrode 210 of the high-voltage capacitor has only a partial overlap with the first metal layer 101, and the first electrode 210 of the high-voltage capacitor and the dielectric layer of the subsequently formed high-voltage capacitor and the second electrode of the high-voltage capacitor constitute a high-voltage capacitor, and the first metal layer 101 is used to connect the first electrode 210 of the high-voltage capacitor to an external circuit and to connect to the first electrode plate of the subsequently formed silicon capacitor.

[0065] In another embodiment of the present invention, the first metal layer 101 may also be directly used as the first electrode plate of the high-voltage capacitor without forming the second metal layer 102 on the first interlayer dielectric layer 111. The present invention is not limited to this.

[0066] In step S2, please continue to refer to Figure 2 As shown, at least one interlayer dielectric layer is formed on the first electrode plate 210 of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor, and a conductive through hole 211 is formed in each interlayer dielectric layer. The conductive through holes 211 are interconnected and connected to the first electrode plate 210 to serve as a lead-out channel of the first electrode plate 20.

[0067] A metal layer (for example, the third metal layer 103 and the fourth metal layer 104) is also formed in each interlayer dielectric layer on the first electrode plate 210 of the high-voltage capacitor, and the metal layer connects two adjacent conductive through holes 211. The metal layer and the conductive through holes 211 together constitute the lead-out channel of the first electrode plate 210 of the high-voltage capacitor.

[0068] In this embodiment, three interlayer dielectric layers are formed on the first electrode plate 210 of the high-voltage capacitor, such as the second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114, but this is not limited thereto. The second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114 may be made of the same material and manufactured by the same method as the bottom interlayer dielectric layer 110 and the first interlayer dielectric layer 111. Figures 2 to 8 There is no distinction between these interlayer dielectric layers.

[0069] In one embodiment of the present invention, the substrate 100 includes a first region I and a second region II, the high-voltage capacitor and the subsequent silicon capacitor are formed in the first region I, and a semiconductor structure is formed in the second region II. Of course, it is not limited to this. The substrate 100 may also include other regions. The positions of the first region I and the second region II are only exemplarily marked in the accompanying drawings. The semiconductor structure is, for example, an active device, such as a metal oxide semiconductor transistor device. Multiple interlayer dielectric layers are formed on the substrate 100 in the second region II, and a metal layer and a conductive via are formed in each interlayer dielectric layer. The metal layer and the conductive via lead out the corresponding electrodes of the semiconductor structure (for example, the gate, source and drain of the metal oxide semiconductor transistor are led out respectively). In this embodiment, four metal layers and five interlayer dielectric layers are formed on the semiconductor structure, for example, the bottom interlayer dielectric layer 110, the first interlayer dielectric layer 111, the second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114, the first metal layer 101, the second metal layer 102, the third metal layer 103 and the fourth metal layer 104, the materials of the five interlayer dielectric layers are the same, and the materials of the four metal layers are also the same.

[0070] While forming corresponding interlayer dielectric layers, metal layers and conductive vias on the substrate 100 in the second region II, the same interlayer dielectric layers, metal layers and conductive vias are formed on the substrate 100 in the first region I. Figure 2The same layer located in different regions is not distinguished. For example, the first electrode 210 of the high-voltage capacitor is formed synchronously with the metal layer (for example, the second metal layer 102) located in the same layer in the second region II, and the dielectric layer of the high-voltage capacitor is formed synchronously with the interlayer dielectric layer located in the same layer in the second region II (in the second region II, three interlayer dielectric layers are also formed on the second metal layer 102, then the dielectric layer of the high-voltage capacitor includes three interlayer dielectric layers, and the number of interlayer dielectric layers included in the dielectric layer of the high-voltage capacitor is the same as the number of interlayer dielectric layers on the second metal layer 102 in the second region, and is of course not limited to three layers), and the lead-out channel is formed synchronously with the metal layer and the conductive through hole located in the same layer in the second region II (that is, while the corresponding electrode of the semiconductor structure is led out in the second region II, a lead-out channel is also formed in the first region I to lead out the first metal layer 101, which is equivalent to leading out the first electrode 210).

[0071] Please refer to Figure 2 As shown, a bottom interlayer dielectric layer 110 is formed on the substrate 100, and a conductive through hole is formed in the bottom interlayer dielectric layer 110. The conductive through hole is only located in the second region II and is used to connect the electrodes of the semiconductor structure. Then, multiple first metal layers 101 located in the same layer are formed. The multiple first metal layers 101 are located in different regions. For example, the first metal layer 101 located in the first region I is used as a connecting layer between the first plate of the high-voltage capacitor and the first plate of the silicon capacitor. The first metal layer 101 located in the second region II is used to connect the conductive through hole to connect different electrodes of the semiconductor structure. Then, a first interlayer dielectric layer 111 is formed, and then multiple conductive through holes are formed in the first interlayer dielectric layer 111. Different conductive through holes connect different or the same first metal layers 101. By analogy, the same interlayer dielectric layer (or the same metal layer or the conductive through hole located in the same layer) formed in different regions of the substrate 100 is formed in the same step.

[0072] In this embodiment, a fifth interlayer dielectric layer 115 is further formed on the fourth interlayer dielectric layer 114 , and the fifth interlayer dielectric layer 115 includes a silicon oxynitride layer and a silicon nitride layer sequentially located on the fourth interlayer dielectric layer 114 to improve the withstand voltage capability of the high voltage capacitor.

[0073] In this embodiment, the material of the first plate 210 of the high-voltage capacitor is the same as the material of the second metal layer 102, and the material of the dielectric layer of the high-voltage capacitor is determined by the material of the interlayer dielectric layer of each layer. Exemplarily, the material of the first plate 210 of the high-voltage capacitor includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and the material of the dielectric layer of the high-voltage capacitor can be ethyl silicate, borophosphosilicate glass, or other suitable dielectric materials, such as low-k dielectric materials or any combination of these materials.

[0074] In step S3, please refer to Figure 3 As shown, the interlayer dielectric layer is etched to form a deep trench 121 .

[0075] In one embodiment of the present invention, a photoresist layer is formed on the top interlayer dielectric layer (i.e., the fifth interlayer dielectric layer 115) (in order to distinguish it from the subsequent photoresist layers, it is referred to as the first photoresist layer in this embodiment), the first photoresist layer is exposed and developed to form a patterned first photoresist layer 120, all the interlayer dielectric layers are etched using the patterned first photoresist layer 120 as a mask to form deep grooves 121, and then the patterned first photoresist layer 120 is removed. In one embodiment, all the interlayer dielectric layers are etched until the first metal layer 101 is exposed, that is, the fifth interlayer dielectric layer 115, the fourth interlayer dielectric layer 114, the third interlayer dielectric layer 113, the second interlayer dielectric layer 112 and the first interlayer dielectric layer 111 (i.e., all the interlayer dielectric layers located on the first metal layer 101) are etched to form deep grooves 121 that expose the first metal layer 101.

[0076] It should be noted that the deep groove 121, the lead-out channel and the first electrode 210 of the high-voltage capacitor are all located at different positions in the first area I. The position where the deep groove 121 is located has a multi-layer stacked interlayer dielectric layer, and the top of the first electrode 210 of the high-voltage capacitor also has only a multi-layer stacked interlayer dielectric layer. The position where the lead-out channel is located not only has a multi-layer stacked interlayer dielectric layer, but also each interlayer dielectric layer has a metal layer and a conductive through hole located above the metal layer to connect the first metal layer 101 to the upper surface of the top interlayer dielectric layer.

[0077] In step S4, please refer to Figure 4 and Figure 5As shown, a first electrode plate 310 of a silicon capacitor is formed on the side wall and the bottom of the deep groove 121, and the first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor; a dielectric layer 320 of a silicon capacitor is formed on the side wall and the bottom of the deep groove 121, and the dielectric layer 320 of the silicon capacitor covers the first electrode plate 310 of the silicon capacitor; a second electrode plate 330 of a silicon capacitor is formed in the deep groove 121, and the second electrode plate 330 of the silicon capacitor fills the deep groove.

[0078] In this embodiment, first, a first conductive material layer 311 is formed, and the first conductive material layer 311 covers the sidewalls and the bottom of the deep trench 121, and covers the top surface of the fifth interlayer dielectric layer 115; then, an insulating material layer 321 is formed, and the insulating material layer 321 covers the sidewalls and the bottom of the deep trench 121, and covers the top surface of the fifth interlayer dielectric layer 115, that is, the insulating material layer 321 covers the first conductive material layer 311; then, a second conductive material layer 331 is formed, and the second conductive material layer 331 fills the deep trench 121 and covers the fifth interlayer dielectric layer 115 (specifically covers the insulating material layer 321 on the fifth interlayer dielectric layer 115), forming the following. Figure 4 The structure shown.

[0079] Then, please refer to Figure 5 As shown, planarization is performed, such as chemical mechanical polishing, until the fifth interlayer dielectric layer 115 is exposed (i.e., until the top interlayer dielectric layer is exposed), and a first conductive layer covering the sidewalls and the bottom is formed in the deep groove 121, an insulating layer covering the first conductive layer and covering the sidewalls and the bottom, and a second conductive layer filling the deep groove 121. The first conductive layer serves as the first electrode 310 of the silicon capacitor, the insulating layer serves as the dielectric layer 320 of the silicon capacitor, and the second conductive layer serves as the second electrode 330 of the silicon capacitor. It should be noted that when the chemical mechanical polishing stops on the fifth interlayer dielectric layer 115, it is necessary to control the loss of the fifth interlayer dielectric layer 115 to prevent the thickness change of the fifth interlayer dielectric layer 115 from affecting the withstand voltage performance of the high-voltage capacitor.

[0080] In one embodiment of the present invention, the material of the first conductive material layer 311 includes but is not limited to titanium nitride, the material of the second conductive material layer 331 includes but is not limited to tungsten, and the insulating material layer 321 includes a silicon nitride layer or a stack composed of silicon oxide-silicon nitride-silicon oxide, that is, the material of the insulating material layer 321 includes but is not limited to silicon oxide-silicon nitride-silicon oxide (ONO) or silicon nitride, that is, in the silicon capacitor, the material of the first plate 310 of the silicon capacitor includes but is not limited to titanium nitride, the material of the second plate 330 of the silicon capacitor includes but is not limited to tungsten, and the material of the dielectric layer 320 of the silicon capacitor includes but is not limited to ONO or silicon nitride. Of course, the materials of each layer in the silicon capacitor are not limited thereto, and can also be any other suitable materials known to those skilled in the art. The first conductive material layer 311, the insulating material layer 321 and the second conductive material layer 331 can be formed by deposition processes such as atomic layer deposition process, chemical vapor deposition process, and physical vapor deposition process.

[0081] In the embodiment of the present invention, the first plate 310 and the second plate 330 of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove 121, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves 121 can be accommodated in the interlayer dielectric layer, further increasing the integration.

[0082] In addition, the dielectric layer 320 of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown of weak positions caused by dielectric defects and dielectric uniformity during operation.

[0083] In step S5, please refer to Figure 7 As shown, a second electrode plate 220 of the high voltage capacitor is formed on the top interlayer dielectric layer.

[0084] For example, first, please refer to Figure 6 As shown, a conductive material layer is formed (in order to distinguish it from the first conductive material layer and the second conductive material layer, it is referred to as the third conductive material layer 221 in this embodiment), and the third conductive material layer 221 covers the top interlayer dielectric layer, specifically covers the fifth interlayer dielectric layer 115, and of course also covers the conductive through hole 211 and the silicon capacitor in the top interlayer dielectric layer.

[0085] Then, please refer to Figure 7As shown, the third conductive material layer 221 is etched until the interlayer dielectric layer of the top layer is exposed. Specifically, a second photoresist layer is formed on the third conductive layer 221, and the second photoresist layer is exposed and developed to form a patterned second photoresist layer 130. The patterned second photoresist layer 130 is used as a mask to etch the third conductive material layer 221 until a portion of the interlayer dielectric layer of the top layer is exposed, and a portion of the third conductive material layer 221 is retained. The third conductive material layer located directly above the first electrode plate 210 of the high-voltage capacitor is retained as the second electrode plate 220 of the high-voltage capacitor, the third conductive material layer located on the lead-out channel is retained as the first lead-out terminal 212 of the first electrode plate 210 of the high-voltage capacitor and the first electrode plate 310 of the silicon capacitor, the third conductive material layer located on the second electrode plate 330 of the silicon capacitor is retained as the second lead-out terminal 332 of the second electrode plate 330 of the silicon capacitor, and the third conductive material layer on the conductive through hole in the second region II is also retained as the third lead-out terminal 140 of the electrode of the semiconductor structure. Then, the second photoresist layer 130 of the pattern is removed.

[0086] In one embodiment of the present invention, the material of the third conductive material layer 221 includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and may be any other suitable material.

[0087] In addition, in this embodiment, when etching the third conductive material layer 221 , it is necessary to control the size of the remaining third conductive material layer 221 to prevent the first electrode 310 of the silicon capacitor from being short-circuited with the second electrode 330 of the silicon capacitor.

[0088] Please refer to Figure 8 As shown, after forming the second electrode plate 220 of the high-voltage capacitor, it also includes: forming a passivation layer, the passivation layer covers the exposed top interlayer dielectric layer and exposes the lead-out terminal. In one embodiment of the present invention, please refer to Figure 8 As shown, the passivation layer includes a first passivation layer 151 and a second passivation layer 152. The material of the first passivation layer 151 includes silicon oxynitride, and the material of the second passivation layer 152 includes PI (polyimide). In other embodiments, only one passivation layer may be formed, and the passivation layer may be silicon oxynitride or PI.

[0089] In the method for manufacturing a semiconductor device provided by the present invention, a first electrode plate 210 of a high-voltage capacitor is first formed, and then at least one interlayer dielectric layer is formed on the first electrode plate 210 as a dielectric layer of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive through hole 211, and the conductive through holes 211 are interconnected and connected to the first electrode plate 210 to serve as an extraction channel of the first electrode plate 210, and then all the interlayer dielectric layers are etched to form a deep groove 121, and then the sidewalls and bottom of the deep groove 121 are formed. The first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor; a dielectric layer 320 of the silicon capacitor is formed on the sidewall and bottom of the deep groove 121, and the dielectric layer 320 of the silicon capacitor covers the first electrode plate 310 of the silicon capacitor; a second electrode plate 330 of the silicon capacitor is formed in the deep groove 121, and the second electrode plate 330 of the silicon capacitor fills the deep groove 121, and then the second electrode plate 220 of the high-voltage capacitor is formed on the interlayer dielectric layer of the top layer. The present invention integrates the production of high-voltage capacitors and silicon capacitors in one process, saves process steps, saves production costs, and improves product competitiveness.

[0090] Correspondingly, the present invention also provides a semiconductor device manufactured by the method for manufacturing the semiconductor device as described above.

[0091] Please refer to Figure 8 As shown, the semiconductor device comprises:

[0092] A first electrode plate 210 of a high voltage capacitor;

[0093] At least one interlayer dielectric layer is located on the first electrode plate 210 of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor. A conductive through hole 211 is formed in each interlayer dielectric layer. The conductive through holes 211 are interconnected and connected to the first electrode plate 210 of the high-voltage capacitor to serve as an extraction channel of the first electrode plate 210 of the high-voltage capacitor. A deep groove 121 penetrating the interlayer dielectric layer is formed in the interlayer dielectric layer.

[0094] The first electrode plate 310 of the silicon capacitor is located on the sidewall and bottom of the deep groove 121, and the first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor;

[0095] The dielectric layer 320 of the silicon capacitor is located on the sidewall and bottom of the deep trench 121 and covers the first electrode plate 310 of the silicon capacitor;

[0096] The second electrode plate 330 of the silicon capacitor is located in the deep trench 121 and fills the deep trench 121; and

[0097] The second electrode plate 220 of the high voltage capacitor is located on the top interlayer dielectric layer.

[0098] In one embodiment of the present invention, the material of the first plate 310 of the silicon capacitor includes but is not limited to titanium nitride, and the material of the second plate 330 of the silicon capacitor includes but is not limited to tungsten. The first plate 310 and the second plate 320 of the silicon capacitor are both made of conductive materials, and do not require ion implantation, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.

[0099] In one embodiment of the present invention, the material of the dielectric layer 320 of the silicon capacitor includes ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown of weak positions caused by dielectric defects and dielectric uniformity during operation.

[0100] In summary, in the semiconductor device and its manufacturing method provided by the present invention, firstly, a first electrode plate of a high-voltage capacitor is formed, and then at least one interlayer dielectric layer is formed on the first electrode plate as the dielectric layer of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive through hole, and the conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as the lead-out channel of the first electrode plate of the high-voltage capacitor, and then the interlayer dielectric layer is etched to form a deep groove, and then a first conductive layer is formed on the side wall and bottom of the deep groove as the first electrode plate of the silicon capacitor, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and an insulating layer is formed on the side wall and bottom of the deep groove, and the insulating layer covers the first conductive layer as the dielectric layer of the silicon capacitor, and a second conductive layer is formed in the deep groove, and the second conductive layer fills the deep groove as the second electrode plate of the silicon capacitor, and then a third conductive layer is formed on the top interlayer dielectric layer as the second electrode plate of the high-voltage capacitor. The present invention integrates the production of high-voltage capacitors and silicon capacitors in one process, saves process steps, saves production costs, and improves product competitiveness.

[0101] Furthermore, the first plate and the second plate of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.

[0102] In addition, the dielectric layer of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown in weak locations caused by dielectric defects and dielectric uniformity during operation.

[0103] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a first plate of a high voltage capacitor; At least one interlayer dielectric layer is formed on the first electrode plate of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive through hole, and the conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as a lead-out channel of the first electrode plate of the high-voltage capacitor; Etching the interlayer dielectric layer to form a deep groove; A first electrode plate of a silicon capacitor is formed on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor; a dielectric layer of a silicon capacitor is formed on the sidewall and bottom of the deep trench, the dielectric layer of the silicon capacitor covers the first electrode plate of the silicon capacitor; a second electrode plate of a silicon capacitor is formed in the deep trench, the second electrode plate of the silicon capacitor fills the deep trench; as well as A second electrode plate of the high voltage capacitor is formed on the top interlayer dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming a first plate of a high voltage capacitor include: Providing a substrate, and forming a bottom interlayer dielectric layer on the substrate; forming a first metal layer, wherein the first metal layer covers a portion of the bottom interlayer dielectric layer; forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the first metal layer and the bottom interlayer dielectric layer; forming a conductive through hole in the first interlayer dielectric layer connected to the first metal layer; A second metal layer is formed, wherein the second metal layer covers a portion of the first interlayer dielectric layer, and the second metal layer is connected to the first metal layer through the conductive via, and the second metal layer serves as a first electrode plate of the high-voltage capacitor.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: In a direction perpendicular to the substrate, the first electrode plate of the high-voltage capacitor covers a portion of the first metal layer.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: All the interlayer dielectric layers are etched to form deep grooves exposing the first metal layer, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor through the first metal layer.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: A metal layer is formed in each interlayer dielectric layer on the first electrode plate of the high-voltage capacitor. The metal layer connects two adjacent conductive through holes. The metal layer and the conductive through holes together constitute a lead-out channel of the first electrode plate of the high-voltage capacitor.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The substrate comprises a first region and a second region, a semiconductor structure is formed in the second region, and the high-voltage capacitor and the silicon capacitor are formed in the first region; forming a plurality of interlayer dielectric layers in the second region, and forming a metal layer and a conductive via in each interlayer dielectric layer, wherein the metal layer and the conductive via lead out corresponding electrodes of the semiconductor structure; The first electrode plate of the high-voltage capacitor is formed synchronously with the metal layer located on the same layer in the second region, the dielectric layer of the high-voltage capacitor is formed synchronously with the interlayer dielectric layer located on the same layer in the second region, and the lead-out channel is formed synchronously with the metal layer and the conductive through hole located on the same layer in the second region.

7. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of etching the interlayer dielectric layer to form a deep trench comprises: forming a photoresist layer on the top interlayer dielectric layer; Exposing and developing the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching all interlayer dielectric layers until the first metal layer is exposed; and The patterned photoresist layer is removed.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The second electrode plate of the high-voltage capacitor is formed while forming the lead-out end of the first electrode plate of the high-voltage capacitor, the lead-out end of the first electrode plate of the silicon capacitor, and the lead-out end of the second electrode plate of the silicon capacitor; The method of forming a second plate of a high voltage capacitor on a top interlayer dielectric layer comprises: forming a conductive material layer, wherein the conductive material layer covers the top interlayer dielectric layer; The conductive material layer is etched to expose a portion of the top interlayer dielectric layer, and the conductive material layer directly above the first electrode plate of the high-voltage capacitor is retained as the second electrode plate of the high-voltage capacitor, the conductive material layer on the lead-out channel is retained as the first lead-out end of the first electrode plate of the high-voltage capacitor and the first electrode plate of the silicon capacitor, and the conductive material layer on the second electrode plate of the silicon capacitor is retained as the second lead-out end of the second electrode plate of the silicon capacitor.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The materials of the first plate and the second plate of the high-voltage capacitor include copper, tungsten, aluminum, ruthenium or cobalt, and the material of the dielectric layer of the high-voltage capacitor includes ethyl silicate, borophosphosilicate glass or a low dielectric constant material; the material of the first plate of the silicon capacitor includes titanium nitride, the material of the second plate of the silicon capacitor includes tungsten, and the dielectric layer of the silicon capacitor includes a silicon nitride layer or a stack composed of silicon oxide-silicon nitride-silicon oxide.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device comprises: A first plate of a high voltage capacitor; At least one interlayer dielectric layer is located on the first electrode plate of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor. A conductive through hole is formed in each interlayer dielectric layer. The conductive through holes are interconnected and connected to the first electrode plate of the high-voltage capacitor to serve as an extraction channel for the first electrode plate of the high-voltage capacitor. A deep groove is formed in the interlayer dielectric layer and penetrates the interlayer dielectric layer. A first electrode plate of the silicon capacitor is located on the sidewall and bottom of the deep groove, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor; A dielectric layer of the silicon capacitor, located on the sidewall and bottom of the deep trench and covering the first electrode plate of the silicon capacitor; a second electrode plate of the silicon capacitor, located in the deep trench and filling the deep trench; and The second plate of the high voltage capacitor is located on the top interlayer dielectric layer.

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