Single-drive gate cascaded high-voltage SiC MOSFET power module circuit

Abstract

A single-drive gate cascaded high-voltage MOSFET module circuit includes: a MOSFET, a static voltage equalization resistor, a high-voltage capacitor, a high-voltage avalanche diode, a transient voltage suppressor (TVS) diode, a drive resistor, and a varistor (MOV). The present invention has a simple drive structure and also has excellent switching characteristics, superior dynamic and static voltage equalization effects, and low module loss.

Description

Technical Field

[0001] This invention relates to the technology of modular power electronic circuits, specifically a single-drive gate cascaded high-voltage MOSFET module circuit. Background Technology

[0002] Existing SiC MOSFET power devices have low single-chip breakdown voltage. To achieve high voltage, multiple low-voltage devices need to be cascaded. Most cascading methods use multiple trigger signals for synchronous triggering, requiring isolation of each trigger signal. This increases circuit complexity and cost, and the power density cannot reach a high level. The control mechanism is complex, and due to differences in individual parameters, there may be differences in turn-on and turn-off timing, resulting in an imbalance between the voltage and current flowing through the devices. Currently, the mainstream cascading methods mainly include passive buffering, voltage clamping, gate pulse control, and MMC multilevel circuits. However, the mainstream topologies lack novel circuit structures that are single-drive, easy to implement, and have good voltage equalization effects. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a single-drive gate cascaded high-voltage SiCMOSFET module circuit. This circuit features a simple driving structure and excellent switching characteristics, superior dynamic and static voltage equalization, and low module loss.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a single-drive gate cascaded high-voltage SiC MOSFET module circuit, comprising: three layers of SiC MOSFETs and their corresponding static voltage equalization resistors, high-voltage capacitors, high-voltage avalanche diodes, transient voltage suppressor (TVS) diodes, drive resistors, and varistor (MOV). The drain terminal of the bottom SiC MOSFET is connected to the source terminal of the top SiC MOSFET. The high-voltage terminal of each static voltage equalization resistor is connected to the anode terminal of the corresponding high-voltage avalanche diode, which is then connected to the drain terminal of the corresponding SiC MOSFET. The high-voltage terminal of each high-voltage capacitor is connected to the cathode terminal of the high-voltage avalanche diode. The cathode terminals of the TVS diodes are connected to the gate terminals of their respective SiC MOSFETs. A surface-mount drive resistor is connected in series before the gate terminal of each SiC MOSFET, and the drain terminal is connected to the high-voltage terminal of the corresponding varistor. The varistor (MOV) is connected in parallel between the drain and source terminals of each SiC MOSFET.

[0006] An accelerating capacitor is connected in parallel between the drain and source of the underlying SiC MOSFET to effectively improve the turn-on time of the module.

[0007] Technical effect

[0008] This invention simplifies the complexity of the driving system and increases the power density by controlling cascaded SiC MOSFET devices with a single-gate driver. When the power module is on, the drive is applied to the bottom SiC MOSFET, causing its drain voltage to drop, which in turn lowers the source voltage of the middle SiC MOSFET. The drive unit works in conjunction with the SiC MOSFET to allow the drive signal to be forward-biased through a high-voltage avalanche diode, gradually applied to the gates of the middle and top SiC MOSFETs, further turning on the entire module. When the power module is off, the high-voltage avalanche diode blocks the drive signal, preventing the gates of the middle and top SiC MOSFETs from receiving the drive signal, thus turning off the entire module. Compared to existing technologies, this invention effectively reduces parasitic inductance in the circuit, provides good voltage equalization, minimizes voltage and current overshoot, exhibits excellent turn-on and turn-off characteristics, improves the power density of the power module, and eliminates the need for complex isolated multi-trigger gate drives. Unlike traditional drain-source voltage equalization, gate voltage equalization electrically isolates the drive, cascaded SiC MOSFETs, and voltage equalization units, reducing mutual electrical interference. A protection unit is also applied to the gate voltage equalization side to protect the SiC MOSFET from voltage overshoot and prevent insulation breakdown. An accelerating capacitor is used to accelerate the turn-on of the SiC MOSFET, reduce tailing time, effectively reduce switching losses, and improve overall efficiency. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the circuit topology of the present invention;

[0010] In the diagram: R p1 -R p3 For varistors MOV, R l1 -R l3 For the discharge resistor, R g1 -R g3 For driving resistor, C e1 -C e3 For equalizing capacitors, D e1 -D e3 High voltage avalanche diode, D g1 -D g2 Q1-Q3 are high-voltage avalanche diodes, Q2-Z3 are high-voltage SiC MOSFETs, Z2-Z3 are transient voltage suppressor diodes (TVS), and R... e1 -R e3 Static voltage equalization resistor;

[0011] Figure 2 This is a schematic diagram of the circuit analysis for turning on the SiC MOSFET power module circuit of the present invention.

[0012] In the figure: (a), (b), (c), and (d) are schematic diagrams of the circuit analysis for turning on each layer of the SiC MOSFET power module, respectively;

[0013] Figure 3 This is a schematic diagram of the circuit analysis for turning off the SiC MOSFET power module circuit of the present invention.

[0014] In the figure: (a), (b), (c), and (d) are schematic diagrams of the circuit analysis for the turn-off of each layer of the SiC MOSFET power module;

[0015] Figure 4 This is a schematic diagram of the turn-on and turn-off of the SiC MOSFET power module circuit of the present invention;

[0016] Figure 5 This is a flowchart of the power module test for the present invention;

[0017] Figure 6 This is a waveform diagram of the actual switching of the SiC MOSFET power module circuit of the present invention. V3, V2, and V1 are the drain-to-ground voltages of Q3, Q2, and Q1, respectively.

[0018] In the figure: (a) the switching waveform of the module without accelerating capacitor, and (b) the switching waveform of the module with parallel accelerating capacitor. Detailed Implementation

[0019] like Figure 1 As shown, this embodiment relates to a single-drive gate cascaded high-voltage SiC MOSFET power module circuit, which uses three layers of 2kV SiC MOSFETs cascaded to realize a 6kV power module, including: three layers of SiC MOSFETs Q1-Q3 and their corresponding static voltage equalization resistors R. e1 -R e3 High-voltage capacitor C e1 -C e3 High-voltage avalanche diode D e1 -D e3 Transient voltage suppressor diodes (TVS) Z2-Z3, drive resistor R g1 -R g3 and varistor (MOV) R p1 -R p3 Wherein: the drain terminal of the bottom SiC MOSFET is connected to the source terminal of the top SiC MOSFET, and the static voltage equalization resistor R of each layer is connected. e1 -R e3 The high-voltage terminal and the corresponding high-voltage avalanche diode D e1 -D e3 The anode terminal is connected to the drain terminal of the corresponding SiC MOSFET, and each layer of high-voltage capacitor C e1 -C e3The high-voltage terminal is connected to the cathode of the high-voltage avalanche diode, and the cathodes of transient voltage suppressor diodes (TVS) Z2-Z3 are connected to the gates of the corresponding SiC MOSFETs, respectively. A surface-mount drive resistor R is connected in series before the gate of each SiC MOSFET. g1 -R g3 The drain terminal and the corresponding varistor R p1 -R p3 The high-voltage side is connected, and the drain-source of the bottom SiC MOSFET is connected in parallel with an accelerating capacitor C.

[0020] Voltage of the equalizing capacitor U under long-term operation C This will result in a stepped rise, which is very detrimental to the stability of the module circuit operation. Therefore, in each high-voltage capacitor C... e1 -C e3 A bleed resistor R is connected in parallel across its two ends. l1 -R l3 In each cycle, a certain amount of charge is released to slow down or even balance the charge increment in each cycle, so that a constant clamping voltage value is maintained on the high voltage capacitor.

[0021] like Figure 2-3 As shown, this is the layer-by-layer turn-on and turn-off process of the single-drive gate cascaded high-voltage SiC MOSFET power module circuit in this embodiment. The turn-on stage includes: pre-charge stage, bottom layer, middle layer and top layer turn-on stage, and the turn-off stage includes bottom layer and top layer turn-off stage, discharge voltage stage and dynamic voltage equalization stage.

[0022] like Figure 2 As shown in (a), the pre-charging stage refers to the following: all three SiC MOSFETs Q1-Q3 are in the off state. Under static conditions, the voltage equalization resistors R1-R3 serve to equalize the voltage, and each device bears 1 / 3 of the line voltage. Assuming that the capacitors initially have no charge, after the power module bears the voltage, each capacitor is gradually charged to the corresponding voltage level through the pre-amplified high-voltage avalanche diode. After the diode turns off and conducts, the power module transitions to a steady state. When a drive signal is applied to Q1, it is charged through the parasitic capacitance between the gate and source during the time t0-t1. V gs1 Gradually increasing. At time t1, V gs1 Reaching threshold voltage V th At that time, Q1 starts conducting, V ds1 It has begun to descend;

[0023] like Figure 2 As shown in (b), the underlying activation phase refers to the time V between t1 and t2. gs1 Continue to rise, C gs Continue charging, V ds1 The voltage continues to decrease, but because there is no conduction during this period, the voltage change is small. (t2-t3, when V...)gs1 Reaching Miller plateau voltage V m At that time, it began to enter the Miller platform, and for a period of time V gs1 V ds1 V remains unchanged after charging for a period of time. ds1 The voltage continues to decrease and gradually reaches 0. During this process, the entire power module circuit is not fully turned on and is still in the off state. The voltage on other MOSFETs will increase slightly, but this does not affect the analysis process of the power module.

[0024] like Figure 2 As shown in (c), the mid-layer activation phase refers to the time V between t3 and t4. gs1 V ds1 Continue to change, at time t5, V ds1 When the voltage drops below the driving voltage, the driving voltage passes through D. g2 Give C for Q2 gs During charging, Q2 continues the process of the second mode mentioned above: time t5-t6 V gs2 Rise, V ds2 The voltage drops, reaching the threshold voltage V at time t6. gs2 It then begins to decline. T6-T7 continues charging, T7-T8 enters the Miller platform V. gs2 V ds2 The voltage remains constant for a period of time. During the time interval t8-t9, the voltage of Q2 continues to decrease and gradually decreases to 0. In the same mode 2, the voltage on Q3 increases slightly.

[0025] like Figure 2 As shown in (d), the top-level activation phase refers to: V at a certain time within t8-t9. ds2 When the voltage drops below the driving voltage, the driving voltage passes through D. g3 Give C for Q3 gs During charging, Q3 continues the process of the second mode mentioned above until it reaches its threshold voltage at time t9, V ds3 It begins to decline, t9-t 10 As the voltage Q3 gradually decreases to 0, the voltage V of each MOSFET layer decreases accordingly. ds The voltage continuously decreases. During the transition from mode 1 to mode 4, the drain-source voltage of the power module gradually decreases to 0. 10 The power module will be fully activated later.

[0026] like Figure 3As shown in (a), the underlying turn-off stage refers to the following: the circuit is fully turned on and is equivalent to three SiC MOSFETs connected in parallel with a large resistor, which can be regarded as an open circuit. Since the parameters of the three SiC MOSFETs are consistent during selection, the voltage is evenly distributed across the three SiC MOSFETs, and this is also a steady state. During t1-t2, when the driving voltage changes from positive to negative, the driving diodes are all in the off state, Q1 begins to turn off, and V... gs1 It begins to descend, V ds1 It begins to rise until it passes the Miller plateau (t2-t3), and Q1 remains off during the t3-t5 time period. gs The charge on the circuit is discharged through the driving resistor. At this time, since Q2 and Q3 are still in the on state, most of the voltage is applied to both sides of Q1, and the value is greater than one-third of the line voltage.

[0027] like Figure 3 As shown in (b), the top-level shutdown phase refers to: V ds1 After rising, V gs2 Gradually bearing back pressure, Q2 begins to shut down at time t4, V ds2 Ascending, Q2 turns off at time t7, and similarly at V. ds2 After rising, V gs3 Gradually bearing reverse pressure, Q3 begins to shut down at time t6 until the power module is completely shut down at time t8;

[0028] like Figure 3 As shown in (c), the discharge voltage stage refers to: as the drain-source voltage V of the SiC MOSFET increases layer by layer... ds As the voltage of the power module gradually rises to the line voltage, the circuit is basically turned off and begins to dynamically equalize the voltage. The bottom-level SiC MOSFET Q1 first reaches 1 / 3 of the line voltage. When it continues to rise, the overshoot voltage is discharged through the dynamic voltage equalization circuit on the gate side.

[0029] like Figure 3 As shown in (d), the dynamic voltage equalization stage refers to the following: each layer discharges overshoot voltage through resistors and capacitors. Q3 eventually reaches 1 / 3 of the external power supply voltage, so discharge may not be necessary. At this point, the circuit is completely turned off. The internal process is the voltage equalization process of the three gate voltage equalization circuits. After a period of time, the power module returns to its state before being turned on: the three capacitors are all charged to one-third of the line voltage, the high-voltage avalanche diode is cut off, and the three high-voltage resistors equalize the voltage. From mode 5 to mode 8, the drain-source voltage of the cascaded module gradually rises to the external power supply voltage. After t8, the power module is completely turned off.

[0030] During the bottom and top layer turn-off phases, the voltage discharge phase, and the dynamic voltage equalization phase, the circuit undergoes a series of state transitions, forming a dynamic voltage equalization process. This entire process is dynamic and complex; through precise control and coordination, the circuit can smoothly switch between different modes, achieving voltage equalization and effective energy management. This dynamic equalization design can play a crucial role in SiC MOSFET power modules, ensuring system stability and efficiency.

[0031] like Figure 4 As shown, the layer-by-layer turn-on refers to the following: when the voltage of the bottom SiC MOSFET Q1 drops to around 0V, the voltage of the middle SiC MOSFET Q2 begins to drop; when the voltage of SiC MOSFET Q2 drops to around 0V, the voltage of the top SiC MOSFET Q3 begins to drop; and so on, until all SiC MOSFETs are turned on. The power module is also turned off layer by layer: when the voltage of the bottom MOSFET Q1 rises to a predetermined voltage, the voltage of the middle SiC MOSFET Q2 begins to rise, until the predetermined voltage is reached, then the voltage of the top SiC MOSFET Q3 begins to rise; and so on, until all SiC MOSFETs are turned off.

[0032] Through specific experiments, with a bus voltage of 5kV, a drive voltage of 25V, a drive resistor of 5Ω, and a current of 25A, the turn-off times for resistive and inductive loads were 190ns and 90ns, respectively, and the turn-on times were 150ns and 90ns, respectively. Under actual double-pulse testing, considering parasitic inductance and capacitance parameters in the circuit, the turn-on and turn-off times will vary slightly. The actual turn-off time is 100ns, and the turn-on time is 50ns, achieving a fast switching effect.

[0033] Accelerating capacitors are used to address the "tailing" time caused by turn-on delay. The drive exhibits typical RC charging characteristics as it changes over time, resulting in a delay in reaching the turn-on voltage. The drive cannot quickly reach the top-level SiC MOSFET, manifesting as a relatively long "tailing" time during turn-on, approximately 300ns. After adding parallel accelerating capacitors, the turn-on "tailing" is significantly improved, with the "tailing" time reduced to around 150ns. The turn-on time of the power module is approximately 50ns, and the turn-off time is approximately 100ns.

[0034] like Figure 6As shown in (a) and (b), the waveforms of the voltages of each transistor were obtained by constructing the power module and measuring them. The technical information described is as follows: The power module's turn-on process is the same as the analysis. When the voltage of the bottom SiC MOSFET Q1 drops to a certain value, the middle SiC MOSFET Q2 can be turned on. After the voltage of the middle SiC MOSFET Q2 has dropped to a certain value, the top SiC MOSFET Q3 starts to turn on. During the voltage drop of Q1, the voltage across Q2 and Q3 will increase, but this does not affect the overall turn-on of the module. The module turn-on time is 50ns. Due to the typical RC charging characteristics of SiC MOSFET drive over time, there will be a delay in reaching the turn-on voltage. The drive cannot be quickly delivered to the top SiC MOSFET, resulting in a relatively long "tailing" during turn-on, with a tailing time of approximately 300ns. When the module is turned off, the bottom SiC MOSFET Q1 turns off first, and after turning off, there will be a period of overshoot. Q2 and Q3 turn off sequentially, with a turn-off time of 100ns. After adding a parallel accelerating capacitor, the turn-on "tail" was significantly improved, with the "tail" time reduced to about 150ns. The turn-on time of the power module was about 50ns, and the turn-off time was about 100ns.

[0035] When the applied voltage is 2kV and the driving voltage is 20V, the power module circuit is tested using a dual-pulse load, and the turn-on and turn-off times are 50ns and 100ns, respectively.

[0036] Compared with existing technologies, this invention applies a highly efficient voltage equalization and protection unit on the gate side. The voltage equalization unit clamps the voltage of the high-voltage capacitor through a high-voltage avalanche diode, maintaining the steady-state voltage of the power module at a constant preset voltage. Each time the module is turned on, the voltage on a single SiC MOSFET is clamped by the voltage equalization unit, stabilizing the dynamic voltage of the power module. Furthermore, the high-voltage capacitor does not require repeated charging and discharging, thus reducing power module losses and effectively improving the dynamic voltage balance problem in the power module. In static off state, the high-voltage avalanche diode isolates the high-voltage capacitor from the static voltage equalization resistor, effectively cutting off the connection between the high-voltage capacitor and the circuit. The topology only involves the cascaded voltage equalization resistor and the SiC MOSFET. Since the resistance of the selected voltage equalization resistor is much smaller than the turn-off resistance of the SiC MOSFET, the static voltage division of the SiC MOSFET is determined by the voltage equalization resistor. The voltage equalization unit ensures uniform voltage distribution across all devices during steady and transient states. A varistor (MOV) is connected in parallel across the voltage equalization resistor. When a fault occurs in the cascaded module, specifically when the voltage across a SiC MOSFET exceeds its rated value, causing an overshoot, the voltage across the capacitor will charge to the corresponding level. This voltage will break down the MOV, which, after being broken down by the high voltage, will have a low resistance value, allowing current to be discharged through it. No new current will flow through the capacitor, and its clamping voltage will not rise, further protecting the corresponding SiC MOSFET. Adding an accelerating capacitor in parallel across the high-voltage avalanche diode at the gate effectively improves the module's turn-on time. During module turn-off, the accelerating capacitor charges, effectively acting as part of the voltage equalization capacitor, accumulating energy. During module turn-on, since the accelerating capacitor lacks the clamping effect of the reverse high-voltage avalanche diode, it can discharge through the gate drive resistor, accelerating the SiC MOSFET's conduction, effectively reducing switching losses and improving overall efficiency.

[0037] In summary, this device has a simple structure, fast turn-on and turn-off speeds, and can significantly reduce turn-on losses and improve the overall efficiency of the power module.

[0038] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A single-drive gate cascaded high-voltage SiC MOSFET power module circuit, characterized in that, include: The three-layer SiC MOSFETs consist of a static voltage equalization resistor, a high-voltage capacitor, a high-voltage avalanche diode, a transient voltage suppressor diode (TVS), a drive resistor, and a varistor. Specifically: the drain of the bottom-layer SiC MOSFET is connected to the source of the middle-layer SiC MOSFET; the high-voltage terminal of each static voltage equalization resistor is connected to the anode of the corresponding high-voltage avalanche diode, which in turn is connected to the drain of the corresponding SiC MOSFET; the high-voltage terminal of each high-voltage capacitor is connected to the cathode of the high-voltage avalanche diode; the cathodes of the three transient voltage suppressor diodes (TVS) are connected to the gates of the corresponding SiC MOSFETs; a surface-mount drive resistor is connected in series before the gate of each SiC MOSFET; the drain of each SiC MOSFET is connected to the high-voltage terminal of the corresponding varistor; and the varistor (MOV) is connected in parallel between the drain and source of each SiC MOSFET. A discharge resistor is connected in parallel across each high-voltage capacitor to discharge a certain amount of charge in each cycle to slow down or even balance the charge increment in each cycle, so that the high-voltage capacitor maintains a constant clamping voltage value. In the static cutoff state, the high-voltage avalanche diode isolates the high-voltage capacitor from the static voltage equalization resistor, which is equivalent to cutting off the connection between the high-voltage capacitor and the circuit. In the topology, only the voltage equalization resistor and the SiC MOSFET are cascaded. Since the resistance value of the selected voltage equalization resistor is much smaller than the turn-off resistance of the SiC MOSFET, the static voltage division of the SiC MOSFET is determined by the voltage equalization resistor at this time. Accelerating capacitors are connected in parallel on both sides of the high-voltage avalanche diode; This includes: pre-charging phase, bottom layer, middle layer and top layer turn-on phase, bottom layer and top layer turn-off phase, voltage discharge phase and dynamic voltage equalization phase; Layer-by-layer turn-on refers to the process where the voltage of the bottom, middle, and top SiC MOSFETs decreases sequentially until all SiC MOSFETs are turned on. Layer-by-layer turn-off refers to the process where the voltages of the bottom, middle, and top SiC MOSFETs increase sequentially until all SiC MOSFETs are turned off. The pre-charging stage refers to the following: all SiC MOSFETs in the circuit are in the off state. Under static conditions, the voltage equalization resistors play a voltage equalization role, and each device bears 1 / 3 of the line voltage. Initially, the capacitors have no charge. After the module bears the voltage, each capacitor is gradually charged to the corresponding voltage level through the front-mounted high-voltage avalanche diode. After the diode is turned off and turned on, the module transitions to a steady state. When a drive signal is applied to the bottom SiC MOSFET, it is charged through the parasitic capacitance between the gate and source during the time t0-t1, and Vgs1 gradually rises. At time t1, when Vgs1 reaches the threshold voltage Vth, the bottom MOSFET begins to conduct, and Vds1 begins to decrease. The aforementioned bottom-level turn-on phase refers to the following: during time t1-t2, Vgs1 continues to rise, Cgs continues to charge, and Vds1 continues to fall. However, since there is no conduction during this period, the voltage change is small. During time t2-t3, when Vgs1 reaches the Miller plateau voltage Vm, it begins to enter the Miller plateau. For a period of time, Vgs1 and Vds1 remain unchanged. After continuing to charge for a period of time, Vds1 continues to fall and gradually reaches 0. During this period, since the entire power module circuit is not fully turned on and is still in the off state, the voltage shared on other MOSFETs will increase slightly, which does not affect the module's analysis process. The aforementioned middle-layer turn-on phase refers to the following: during time t3-t4, Vgs1 and Vds1 continue to change. At time t5, after Vds1 falls below the driving voltage, the driving voltage charges the Cgs of the middle-layer SiC MOSFET. At this time, the middle-layer SiC MOSFET continues the process of the aforementioned bottom-layer turn-on phase. During time t5-t6, Vgs2 rises and Vds2 falls. At time t6, after reaching the threshold voltage Vgs2, it begins to fall. During time t6-t7, charging continues. During time t7-t8, the Miller plateau is reached, and Vgs2 and Vds2 remain unchanged for a period of time. During time t8-t9, the voltage of the middle-layer MOSFET continues to decrease and gradually decreases to 0. Similar to the bottom-layer turn-on phase, the voltage on the top-layer SiC MOSFET is slightly increased. The aforementioned top-level turn-on phase refers to the following: after Vds2 falls below the driving voltage at a certain moment between t8 and t9, the driving voltage charges the Cgs of the top-level SiC MOSFET. At this time, the top-level SiC MOSFET continues the aforementioned bottom-level turn-on phase process until it reaches its threshold voltage at t9. Vds3 then begins to decrease. During the time interval t9-t10, the voltage of the top-level SiC MOSFET gradually decreases to 0, and the voltage Vds of each layer of SiC MOSFET continues to decrease. The aforementioned bottom-layer turn-off stage refers to the following: the circuit is fully turned on and is equivalent to three SiC MOSFETs connected in parallel with a large resistor, which can be regarded as an open circuit. Since the parameters of the three SiC MOSFETs are consistent during selection, i.e., the steady state of voltage distribution; when the driving voltage changes from positive to negative during t1-t2, the driving diodes are all in the off state, the bottom-layer SiC MOSFET begins to turn off, Vgs1 begins to decrease, and Vds1 begins to rise until the Miller plateau is passed for t2-t3. During t3-t5, the bottom-layer SiC MOSFET continues to turn off, and the charge on Cgs is discharged through the driving resistor. At this time, since the middle-layer SiC MOSFET and the top-layer SiC MOSFET are still in the on state, most of the voltage is applied to both sides of the bottom-layer SiC MOSFET, and the value is greater than one-third of the line voltage.

2. The single-drive gate cascaded high-voltage SiC MOSFET power module circuit according to claim 1, characterized in that, The aforementioned top-level turn-off stage refers to the following: after Vds1 rises, Vgs2 gradually bears reverse voltage, and at time t4, the middle-layer SiC MOSFET begins to turn off. Vds2 rises, and at time t7, the middle-layer SiC MOSFET turns off. Similarly, after Vds2 rises, Vgs3 gradually bears reverse voltage, and at time t6, the top-level MOSFET begins to turn off until time t8 when the module is completely turned off.

3. The single-drive gate cascaded high-voltage SiC MOSFET power module circuit according to claim 2, characterized in that, The aforementioned voltage discharge stage refers to the following: as the drain-source voltage Vds of the MOSFETs rises layer by layer, the voltage of the cascaded module gradually rises to the line voltage. At this point, the circuit is basically turned off and begins to dynamically equalize the voltage. The bottom SiC MOSFET first reaches 1 / 3 of the line voltage. When it continues to rise, the overshoot voltage is discharged through the dynamic voltage equalization circuit on the gate side.

4. The single-drive gate cascaded high-voltage SiC MOSFET power module circuit according to claim 3, characterized in that, The dynamic voltage equalization stage refers to the following: each layer discharges overshoot voltage through resistors and capacitors. The top SiC MOSFET eventually reaches 1 / 3 of the external power supply voltage, so discharge may not be necessary. At this point, the circuit is completely turned off. The internal process is the voltage equalization process of the three gate voltage equalization circuits. After a period of time, the cascaded module returns to the state before it is turned on: the three capacitors are all charged to one-third of the line voltage, the high-voltage avalanche diode is cut off, and the three high-voltage resistors equalize the voltage.

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