Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a base structure having a capacitor region and an adjacent logic region, a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer; a first etch-stop layer located in the capacitor region and covering at least the top of the conductive portion; a second etch-stop layer located in the logic region and covering the top of the first insulating layer; wherein the first etch-stop layer and the second etch-stop layer are made of the same material and are isolated from each other by a protective layer; or, the first etch-stop layer and the second etch-stop layer are made of different materials and a contact interface is formed between the first etch-stop layer and the second etch-stop layer; a first stacked structure covering the layer where the first etch-stop layer and the second etch-stop layer are located; and a slit opening penetrating the first stacked structure and exposing the second etch-stop layer. The semiconductor structure of the present invention improves structural reliability.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of mobile consumer electronics, users are placing higher demands on device miniaturization, functional integration, and large-capacity storage space. For example, devices like smartphones and tablets need to integrate more functional modules, such as processors, memory, and sensors, within a limited space while also meeting user demands for large-capacity storage. To achieve this goal, high-density packaging technology has become critical. However, traditional packaging methods are gradually facing bottlenecks in terms of space utilization and performance improvement, resulting in the emergence of various types of "misaligned" structures during the design process.

[0003] Currently, in the design of capacitor structures, electrode column accommodating holes are formed on a structure where silicon oxide layers and silicon nitride layers are alternately stacked. The centerline of the electrode column prepared in the electrode column accommodating hole does not coincide with the centerline of the source and drain, but rather there is a "misaligned" structure between the two. In the etching process of the electrode column accommodating hole, an aluminum oxide layer is required as an etch stop layer. The bottom size of the electrode column accommodating hole will shrink in the etch stop layer and fall directly above the conductive part. A slit opening is then etched through the silicon oxide layer-silicon nitride layer stacking structure. Acid pickling is used through the slit opening to remove the silicon nitride in the silicon oxide layer-silicon nitride layer stacking structure. During the pickling process, the acid will contact the aluminum oxide etch stop layer and undergo a chemical reaction, greatly increasing the probability of structural collapse of the semiconductor structure.

[0004] For this reason, the reliability of semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the reliability of the semiconductor structure.

[0006] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate structure, the substrate structure having a capacitor region and a logic region adjacent thereto, the substrate structure comprising a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer, the conductive portions being located in the capacitor region, and the first insulating layer exposing the top surface of the conductive portions; a first etch stop layer being located in the capacitor region and at least covering the top of the conductive portions; a second etch stop layer being located in the logic region and covering the top of the first insulating layer, and the second etch stop layer and the first etch stop layer being located in the same layer and the top surfaces of the two being flush; wherein the first etch stop layer The etch-stop layer and the second etch-stop layer are made of the same material, and the first etch-stop layer and the second etch-stop layer are isolated from each other by a protective layer; or, the first etch-stop layer and the second etch-stop layer are made of different materials, and a contact interface is formed between the first etch-stop layer and the second etch-stop layer; a first stacking structure, covering the layer where the first etch-stop layer and the second etch-stop layer are located; a plurality of first electrode columns, each first electrode column is arranged through the first stacking structure and the first etch-stop layer and is in contact with the corresponding conductive part; a slit opening, penetrating the first stacking structure and exposing the second etch-stop layer.

[0007] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate structure, the substrate structure having a capacitor region and a logic region adjacent thereto, the substrate structure comprising a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer, the conductive portions being located in the capacitor region, and the first insulating layer exposing the top surface of the conductive portions; forming an etch stop structure on the substrate structure, the etch stop structure comprising: a first etch stop layer located in the capacitor region and covering at least the top of the conductive portion; a second etch stop layer located in the logic region and covering the top of the first insulating layer, the first etch stop layer and the second etch stop layer being located in the same layer and having their top surfaces flush with each other ; wherein, the first etch stop layer and the second etch stop layer are made of the same material, and the first etch stop layer and the second etch stop layer are isolated from each other by a protective layer; or, the first etch stop layer and the second etch stop layer are made of different materials, and a contact interface is formed between the first etch stop layer and the second etch stop layer; a first stacking structure is formed on the etch stop structure; a plurality of first electrode column accommodating holes are formed through the first stacking structure, and the first electrode column accommodating holes expose the conductive portion; a first electrode column is prepared in the first electrode column accommodating hole, and the first electrode column is in contact and connected with the conductive portion; a slit opening is formed through the first stacking structure, and the slit opening exposes the second etch stop layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure and formation method provided by the embodiments of the present invention configure the etch stop layer structure to include a first etch stop layer and a second etch stop layer. When the materials of the first etch stop layer and the second etch stop layer are the same, a protective layer is used to isolate the first etch stop layer and the second etch stop layer; alternatively, when the materials of the first etch stop layer and the second etch stop layer are different, a contact interface is formed between the first etch stop layer and the second etch stop layer. In the subsequent process of pickling the first stack structure through the slit opening, the pickling liquid can also chemically react with the first etch stop layer. When the materials of the first etch stop layer and the second etch stop layer are the same, a protective layer is set between the first etch stop layer and the second etch stop layer, so that the protective layer protects the side wall of the first etch stop layer in the capacitor area, reduces the probability of contact between the pickling liquid and the first etch stop layer, and thus reduces the probability of damage to the first etch stop layer in the capacitor area; or, when the materials of the first etch stop layer and the second etch stop layer are different, a contact interface is formed between the first etch stop layer and the second etch stop layer, so that the second etch stop layer protects the side wall of the first etch stop layer in the capacitor area, reduces the probability of contact between the pickling liquid and the first etch stop layer in the subsequent pickling process, thereby reducing the probability of damage to the first etch stop layer in the capacitor area, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 6 A schematic structural diagram corresponding to each step of a method for forming a semiconductor structure is shown;

[0011] Figure 7 shows a schematic structural diagram corresponding to the first embodiment of the semiconductor structure of the present invention;

[0012] Figure 8 shows a schematic structural diagram corresponding to the second embodiment of the semiconductor structure of the present invention;

[0013] Figure 9 shows a structural schematic diagram corresponding to the third embodiment of the semiconductor structure of the present invention;

[0014] Figures 10 to 18 It shows a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figures 19 to 22 A schematic structural diagram showing the corresponding steps of the second embodiment of the method for forming a semiconductor structure of the present invention is shown;

[0016] Figures 23 to 27 A schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention is shown. DETAILED DESCRIPTION

[0017] Currently, the reliability of semiconductor structures still needs to be improved. This article analyzes the reasons why its performance needs to be improved by combining a method for forming a semiconductor structure.

[0018] refer to Figure 1 , providing a base structure 12, the base structure 12 having a capacitor area 10A and a logic area 10B adjacent thereto, the base structure 12 includes a first insulating layer 10 and a plurality of conductive portions 11 spaced apart and embedded in the first insulating layer 10, the conductive portions 11 being located in the capacitor area 10A, and the first insulating layer 10 exposing the top surface of the conductive portions 11.

[0019] refer to Figure 2 An etch stop layer 13 covering the first insulating layer 10 and the conductive portion 11 is formed on top of the base structure 12 of the capacitor region 10A and the logic region 10B. The etch stop layer 13 is made of aluminum oxide.

[0020] refer to Figure 3 A first stacked structure 16 is formed on the etch stop layer 13 . The first stacked structure 16 includes a silicon oxide layer 17 and a silicon nitride layer 18 that are alternately and cyclically deposited in sequence, and the uppermost layer of the first stacked structure 16 is the silicon oxide layer 17 .

[0021] refer to Figure 4 , forming a plurality of first electrode pillars 20 penetrating and embedded in the first stacked structure 16 and the etch stop layer 13 in the capacitor region 10A, and the first electrode pillars 20 are in contact with and connected to the conductive portion 11;

[0022] refer to Figure 5 A slit opening 60 is formed in the logic region 10B and penetrates the first stacked structure 16 . The slit opening 60 exposes the etch stop layer 13 .

[0023] refer to Figure 6 The silicon nitride layer 18 is removed by acid etching through the slit opening 60 .

[0024] It has been found that in the subsequent process of removing the silicon nitride layer 18 by pickling through the slit opening 60, the pickling solution will also chemically react with the aluminum oxide etch stop layer 13, causing the etch stop layer 13 of the capacitor region 10A to be hollowed out by the pickling solution (e.g., Figure 6 As shown in FIG, the semiconductor structure is damaged, thereby increasing the risk of structural collapse and affecting the reliability of the semiconductor structure.

[0025] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate structure, the substrate structure having a capacitor region and a logic region adjacent thereto, the substrate structure comprising a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer, the conductive portions being located in the capacitor region, and the first insulating layer exposing the top surface of the conductive portions; a first etch stop layer being located in the capacitor region and at least covering the top of the conductive portions; a second etch stop layer being located in the logic region and covering the top of the first insulating layer, and the second etch stop layer and the first etch stop layer being located in the same layer and the top surfaces of the two being flush; wherein the first etch stop layer The etch-stop layer and the second etch-stop layer are made of the same material, and the first etch-stop layer and the second etch-stop layer are isolated from each other by a protective layer; or, the first etch-stop layer and the second etch-stop layer are made of different materials, and a contact interface is formed between the first etch-stop layer and the second etch-stop layer; a first stacking structure, covering the layer where the first etch-stop layer and the second etch-stop layer are located; a plurality of first electrode columns, each first electrode column is arranged through the first stacking structure and the first etch-stop layer and is in contact with the corresponding conductive part; a slit opening, penetrating the first stacking structure and exposing the second etch-stop layer.

[0026] In a semiconductor structure provided by an embodiment of the present invention, a first etch-stop layer is located in a capacitor region and covers at least the top of a conductive portion, a second etch-stop layer is located in a logic region and covers the top of a first insulating layer, and the second etch-stop layer and the first etch-stop layer are located in the same layer and their top surfaces are flush with each other, the first etch-stop layer and the second etch-stop layer are made of the same material, and the first etch-stop layer and the second etch-stop layer are isolated from each other by a protective layer; or, the first etch-stop layer and the second etch-stop layer are made of different materials, and a contact interface is formed between the first etch-stop layer and the second etch-stop layer. In the subsequent process of pickling the first stack structure through the slit opening, the pickling liquid can also chemically react with the first etch stop layer. To this end, when the materials of the first etch stop layer and the second etch stop layer are the same, a protective layer is set between the first etch stop layer and the second etch stop layer, so that the protective layer protects the side wall of the first etch stop layer in the capacitor area, reduces the probability of the pickling liquid contacting the first etch stop layer, and thus reduces the probability of the first etch stop layer in the capacitor area being damaged; or, when the materials of the first etch stop layer and the second etch stop layer are different, a contact interface is formed between the first etch stop layer and the second etch stop layer, so that the second etch stop layer protects the side wall of the first etch stop layer in the capacitor area, reduces the probability of the pickling liquid contacting the first etch stop layer in the subsequent pickling process, and thus reduces the probability of the first etch stop layer in the capacitor area being damaged, thereby improving the reliability of the semiconductor structure.

[0027] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 7 FIG. 4 shows a structural schematic diagram corresponding to the first embodiment of the semiconductor structure of the present invention.

[0028] The semiconductor structure includes: a base structure 402, the base structure 402 having a capacitor region 400A and an adjacent logic region 400B, the base structure 402 including a first insulating layer 400 and a plurality of conductive portions 401 spaced apart and embedded in the first insulating layer 400, the conductive portions 401 being located in the capacitor region 400A, and the first insulating layer 400 exposing the top surface of the conductive portions 401; a first etch stop layer 404 being located in the capacitor region 400A and covering at least the top of the conductive portion 401; a second etch stop layer 405 being located in the logic region 400B and covering the top of the first insulating layer 400, and the second etch stop layer 405 and the first etch stop layer 404 being interlocked. 04 are located in the same layer and the top surfaces of the two are flush; wherein, the first etch stop layer 404 and the second etch stop layer 405 are made of the same material, and the first etch stop layer 404 and the second etch stop layer 405 are isolated by a protective layer 409; a first stacking structure 410, covering the layer where the first etch stop layer 404 and the second etch stop layer 405 are located; a plurality of first electrode columns 428, each first electrode column 428 is arranged through the first stacking structure 410 and the first etch stop layer 404 and is in contact with the corresponding conductive part 401; a slit opening 430, penetrating the first stacking structure 410 and exposing the second etch stop layer 405.

[0029] Specifically, in the subsequent process of pickling the first stack structure 410 through the slit opening 430, the pickling solution can also chemically react with the first etch stop layer 404 and the second etch stop layer 405. To this end, a protective layer 409 is set between the first etch stop layer 404 and the second etch stop layer 405, so that the protective layer 409 protects the side wall of the first etch stop layer 404 of the capacitor area 400A, reduces the probability of the pickling solution contacting the first etch stop layer 404, thereby reducing the probability of the first etch stop layer 404 in the capacitor area 400A being damaged, and reduces the risk of the semiconductor structure collapsing due to damage to the first etch stop layer 404 in the capacitor area 400A, thereby improving the reliability of the semiconductor structure.

[0030] Specifically, the substrate structure 402 provides a process platform for forming a semiconductor structure.

[0031] As an example, the semiconductor structure is a capacitor structure.

[0032] In the capacitor structure, the capacitor region 400A is used as a region for storing data, and the logic region 400B is used as a region for controlling data read and write operations.

[0033] It should be noted that the first insulating layer 400 is used to electrically isolate adjacent conductive parts 401 .

[0034] The first insulating layer 400 exposes the top surface of the conductive part 401 . In the subsequent process of forming the first electrode column 428 , the first electrode column 428 will penetrate the subsequently formed first stacked structure 410 and the first etch stop layer 404 , thereby enabling the first electrode layer to contact and connect with the conductive part 401 .

[0035] As an example, the material of the first insulating layer 400 includes silicon oxide.

[0036] In other embodiments, the material of the first insulating layer 400 may also be other insulating materials, which is not limited here.

[0037] Specifically, the conductive portion 401 is used to electrically connect to the first electrode column 428 formed subsequently.

[0038] As an example, in a 1T1C (one transistor and one capacitor) memory, the conductive portion 401 may be used as a drain.

[0039] In other embodiments, the conductive portion 401 may also be other conductive film layers, which is not further limited herein.

[0040] As an example, the material of the conductive portion 401 includes tungsten. In other embodiments, the material of the conductive portion may also be other conductive materials, which is not limited here.

[0041] Specifically, the first etch stop layer 404 and the second etch stop layer 405 are made of the same material. By setting a protective layer 409 between the first etch stop layer 404 and the second etch stop layer 405, the protective layer 409 protects the side wall of the first etch stop layer 404 of the capacitor area 400A, reducing the probability of the pickling solution contacting the first etch stop layer 404 during the subsequent pickling process, thereby reducing the probability of the first etch stop layer 404 in the capacitor area 400A being damaged, reducing the risk of the semiconductor structure collapsing due to damage to the first etch stop layer 404 in the capacitor area 400A, and thereby improving the reliability of the semiconductor structure.

[0042] It should be noted that in the method for forming the semiconductor structure, the first etch stop layer 404 serves as an etch stop during the formation of the first electrode pillar 428 , and the second etch stop layer 405 serves as an etch stop during the formation of the slit opening 430 .

[0043] It should also be noted that the first etch stop layer 404 and the second etch stop layer 405 are obtained by patterning the etch stop material layer. Therefore, the first etch stop layer 404 and the second etch stop layer 405 are made of the same material. In the subsequent pickling process, the pickling solution can also chemically react with the first etch stop layer 404. By setting a protective layer 409 between the first etch stop layer 404 and the second etch stop layer 405, even if the pickling solution removes the second etch stop layer 405, the protective layer 409 covers the side wall of the first etch stop layer 404, so that the protective layer 409 can prevent the pickling solution from contacting the first etch stop layer 404, thereby greatly reducing the probability of the first etch stop layer 404 being hollowed out, thereby improving the stability of the semiconductor structure of the capacitor area 400A.

[0044] Specifically, the top surface of the protection layer 409 is flush with the top surface of the first etch stop layer 404 , so that the protection layer 409 can completely cover the sidewalls of the first etch stop layer 404 , reducing the probability of the first etch stop layer 404 contacting the pickling solution.

[0045] In this embodiment, the first etch stop layer 404 covers the surface of the capacitor region 400A of the substrate structure 402 , so that the first etch stop layer 404 serves as an etching stop during the process of forming the first electrode pillar 428 .

[0046] As an example, when the first etch stop layer 404 and the second etch stop layer 405 are made of the same material, the material of the first etch stop layer 404 and the second etch stop layer 405 includes aluminum oxide.

[0047] Specifically, there is an etching selectivity ratio between aluminum oxide and the material selected for the first stacked structure 410. In the step of forming the first electrode column 428, aluminum oxide can act as an etching stop. At the same time, aluminum oxide has a lower dielectric constant, which can reduce signal delay and interference. Moreover, aluminum oxide has good adhesion to metal materials, so that a stable interface can be formed between aluminum oxide and the first electrode column 428.

[0048] In this embodiment, the material of the protection layer 409 is silicon oxide.

[0049] Specifically, silicon oxide can protect the first etch stop layer 404 . In the subsequent pickling process, the pickling solution cannot easily remove silicon oxide, so silicon oxide can block the pickling solution.

[0050] In other embodiments, the material of the protective layer may also be other acid-resistant materials, which is not limited here.

[0051] It should be noted that the first stacked structure 410 provides a process basis for the subsequent arrangement of a capacitor structure.

[0052] In this embodiment, the first stacked structure 410 includes silicon oxide layers 4101 and silicon nitride layers 4102 alternately and cyclically deposited on the first etch stop layer 404 and the second etch stop layer 405 , and the uppermost layer of the first stacked structure 410 is the silicon oxide layer 4101 .

[0053] Specifically, after the silicon nitride layer 4102 is subsequently pickled, a capacitor dielectric layer and a second electrode layer will be formed in the space released by the silicon nitride layer 4102. Correspondingly, the silicon oxide layer 4101 electrically isolates the adjacent capacitor unit array layers. In addition, the top layer of the first stacked structure 410 is the silicon oxide layer 4101, so that the top silicon oxide layer 4101 protects the subsequently formed capacitors. At the same time, the bottom layer of the first stacked structure 410 is also the silicon oxide layer 4101, so that the bottom silicon oxide layer 4101 can protect the top of the first etch stop layer 404, thereby reducing the probability of the pickling solution contacting the top of the first etch stop layer 404, and thus reducing the probability of the top of the first etch stop layer 404 being damaged.

[0054] Specifically, the first electrode pillar 428 can form a capacitor unit array layer together with the capacitor dielectric layer and the second electrode layer subsequently formed in the space released by the silicon nitride layer 4102 .

[0055] As an example, the material of the first electrode column 428 includes tungsten. In other embodiments, the material of the first electrode column may also be other electrode materials, which is not limited here.

[0056] It should be noted that, in the present invention, the slit opening 430 is formed after the first electrode column 428 is formed, so that the formed first electrode column 428 can provide structural support for removing all the silicon nitride layer 4102 by pickling.

[0057] Specifically, the slit opening 430 provides a process window for subsequent acid washing to remove the silicon nitride layer 4102 , allowing the acid washing solution to enter the silicon nitride layer 4102 through the slit opening 430 and remove the silicon nitride layer 4102 .

[0058] It should be noted that, during the formation of the slit opening 430 , using the second etch stop layer 405 as the etching stop position can reduce the probability of the slit opening 430 penetrating the base structure 402 and reduce the risk of the slit opening 430 damaging the film layer below the base structure 402 .

[0059] Figure 8 FIG. 4 shows a structural schematic diagram corresponding to the second embodiment of the semiconductor structure of the present invention.

[0060] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The differences between the embodiment of the present invention and the first embodiment are as follows:

[0061] refer to Figure 8 The first etch stop layer 504 and the second etch stop layer 509 are made of different materials, and a contact interface is formed between the first etch stop layer 504 and the second etch stop layer 509 .

[0062] Specifically, a contact interface is formed between the first etch stop layer 504 and the second etch stop layer 509. During the subsequent pickling process of the first stack structure 510 through the slit opening 530, the pickling solution can also chemically react with the first etch stop layer 504. Since the materials of the first etch stop layer 504 and the second etch stop layer 509 are different, the second etch stop layer 509 in the logic area 500B protects the side wall of the first etch stop layer 504 in the capacitor area 500A, reducing the probability of the pickling solution contacting the first etch stop layer 504 during the subsequent pickling process, thereby reducing the probability of the first etch stop layer 504 in the capacitor area 500A being damaged.

[0063] In this embodiment, the material of the first etch stop layer 504 is aluminum oxide, and the material of the second etch stop layer 509 is amorphous silicon.

[0064] Specifically, there is an etching selectivity ratio between the aluminum oxide selected for the first etch stop layer 504 and the material selected for subsequently forming the first stacked structure 510. In the subsequent step of setting the first electrode column 528, the aluminum oxide can serve as an etching stop. At the same time, aluminum oxide has a lower dielectric constant, which can reduce signal delay and interference. Moreover, aluminum oxide has good adhesion to metal materials, so that a stable interface can be formed between aluminum oxide and the first electrode column 528.

[0065] It should be noted that the second etch stop layer 509 is made of amorphous silicon, which is an acid-resistant material and is not easily removed by acid wet etching. It can protect the first etch stop layer 504. At the same time, there is an etching selectivity ratio between amorphous silicon and the silicon nitride layer and the silicon oxide layer, so that the second etch stop layer 509 can play an etching stop role in the process of forming the slit opening 530.

[0066] Figure 9 FIG. 4 shows a structural schematic diagram corresponding to the third embodiment of the semiconductor structure of the present invention.

[0067] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The differences between the embodiment of the present invention and the first embodiment are as follows:

[0068] refer to Figure 9The first etch stop layer 640 includes a plurality of first etch stop unit layers 604 arranged at intervals, and each first etch stop unit layer 604 covers the top of the corresponding conductive portion 601 .

[0069] It should be noted that each first etch stop unit layer 604 corresponds to covering the top of a conductive part 601, which means that in the method of forming a semiconductor structure, in the process of patterning to obtain the first etch stop layer 640, a photolithography mask plate for patterning the conductive part 601 can be used, that is, the same photolithography mask plate is used to form the conductive part 601 and the first etch stop layer 640, which can reduce the number of photolithography mask plates used and reduce the cost of using the photolithography mask plates.

[0070] In this embodiment, the semiconductor structure also includes: a second insulating layer 610, covering the top of the base structure 602 exposed by the multiple first etch stop unit layers 604, and the second insulating layer 610 is flush with the top of the first etch stop layer 640, that is, the multiple first etch stop unit layers 604 are embedded in the second insulating layer 610 at intervals.

[0071] In this embodiment, the second insulating layer 610 and the protective layer 609 are integrally formed.

[0072] Specifically, the second insulating layer 610 and the protective layer 609 are integrally formed, which means that in the method for forming the semiconductor structure, the second insulating layer 610 and the protective layer 609 are formed in the same step, that is, in the process of forming the second etch stop layer, the insulating material between the second etch stop layer and the first etch stop layer 640 is used as the protective layer 609, so that the protective layer 609 protects the side wall of the first etch stop layer 640, thereby reducing the risk of the first etch stop layer 640 being removed by the pickling solution.

[0073] As an example, the material of the second insulating layer 610 is silicon oxide.

[0074] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure. Figures 10 to 18 The following is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention.

[0075] refer to Figure 10 , providing a base structure 102, the base structure 102 having a capacitor area 100A and an adjacent logic area 100B, the base structure 102 includes a first insulating layer 100 and a plurality of conductive parts 101 spaced apart and embedded in the first insulating layer 100, the conductive parts 101 are located in the capacitor area 100A, and the first insulating layer 100 exposes the top surface of the conductive parts 101.

[0076] Specifically, the substrate structure 102 provides a process platform for subsequent semiconductor structure formation methods.

[0077] As an example, the semiconductor structure is a capacitor structure.

[0078] In the capacitor structure, the capacitor region 100A is used as a region for storing data, and the logic region 100B is used as a region for controlling data read and write operations.

[0079] It should be noted that the first insulating layer 100 is used to electrically isolate adjacent conductive parts 101 .

[0080] The first insulating layer 100 exposes the top surface of the conductive part 101 . In the subsequent process of forming the first electrode column, the first electrode column will penetrate the subsequently formed first stacked structure and the first etch stop layer, so that the first electrode layer can be in contact with the conductive part 101 .

[0081] As an example, the material of the first insulating layer 100 is silicon oxide.

[0082] In other embodiments, the material of the first insulating layer 100 may also be other insulating materials, which is not limited here.

[0083] Specifically, the conductive portion 101 is used to electrically connect to a first electrode column formed subsequently.

[0084] As an example, in a 1T1C (one transistor and one capacitor) capacitor, the conductive portion 101 is used as a drain.

[0085] In other embodiments, the conductive portion 101 may also be other conductive film layers, which is not further limited herein.

[0086] As an example, the material of the conductive part 101 is tungsten.

[0087] refer to Figures 11 to 13B An etch-stop structure is formed on the substrate structure 102, and the etch-stop structure includes: a first etch-stop layer 104, covering the upper surface of the substrate structure 102 in the capacitor area 100A; a second etch-stop layer 105, located in the logic area 100B and covering the top of the first insulating layer 100, the first etch-stop layer 104 and the second etch-stop layer 105 are located in the same layer and the top surfaces of the two are flush; wherein the first etch-stop layer 104 and the second etch-stop layer 105 are made of the same material, and the first etch-stop layer 104 and the second etch-stop layer 105 are isolated by a protective layer 109.

[0088] Specifically, the first etch stop layer 104 and the second etch stop layer 105 are made of the same material. By setting a protective layer 109 between the first etch stop layer 104 and the second etch stop layer 105, the protective layer 109 protects the side wall of the first etch stop layer 104 of the capacitor area 100A, reducing the probability of the pickling solution contacting the first etch stop layer 104 during the subsequent pickling process, thereby reducing the probability of the first etch stop layer 104 in the capacitor area 100A being damaged, reducing the risk of the semiconductor structure collapsing due to damage to the first etch stop layer 104 in the capacitor area 100A, and thereby improving the reliability of the semiconductor structure.

[0089] In this embodiment, the step of forming an etch stop structure on the base structure 102 includes: Figure 11 As shown, an etch stop material layer 103 is formed on the substrate structure 102 to cover the entire surface; Figure 12 As shown, the etch stop material layer 103 is patterned to form a first etch stop layer 104 and a second etch stop layer 105 isolated from each other. The first etch stop layer 104 covers the surface of the capacitor region 100A of the substrate structure 102, and the second etch stop layer 105 covers the surface of the logic region 100B of the substrate structure 102. Figure 13A As shown, the groove formed by the patterned first etch stop layer 104 and the second etch stop layer 105 is filled with protective material and flattened to form a protective layer 109. The top surface of the protective layer 109 is flush with the top surfaces of the first etch stop layer 104 and the second etch stop layer 105, and the first etch stop layer 104 and the second etch stop layer 105 are isolated by the protective layer 109.

[0090] As an example, the step of patterning the etch stop material layer 103 to form a first etch stop layer 104 and a second etch stop layer 105 isolated from each other includes: removing the etch stop material layer 103 at the junction of the capacitor area 100A and the logic area 100B, using the remaining etch stop material layer 103 located in the capacitor area 100A as the first etch stop layer 104, and using the remaining etch stop material layer 103 located in the logic area 100B as the second etch stop layer 105.

[0091] In this embodiment, the etch stop material layer 103 at the interface between the capacitor region 100A and the logic region 100B is removed by a selective etching process.

[0092] The first etch stop layer 104 serves as an etch stop in the subsequent process of forming the first electrode pillar, and the second etch stop layer 105 serves as an etch stop in the subsequent process of forming the slit opening.

[0093] It should be noted that the first etch stop layer 104 and the second etch stop layer 105 are obtained by patterning the etch stop material layer 103. Therefore, the materials of the first etch stop layer 104 and the second etch stop layer 105 are the same. In the subsequent pickling process, the pickling solution can also chemically react with the first etch stop layer 104. By setting a protective layer 109 between the first etch stop layer 104 and the second etch stop layer 105, even if the pickling solution removes the second etch stop layer 105, the protective layer 109 covers the side wall of the first etch stop layer 104, so that the protective layer 109 can prevent the pickling solution from contacting the first etch stop layer 104, thereby greatly reducing the probability of the first etch stop layer 104 being hollowed out, thereby improving the stability of the semiconductor structure of the capacitor area 100A.

[0094] As an example, the planarization process includes a chemical mechanical polishing process.

[0095] In this embodiment, the material of the first etch stop layer 104 and the second etch stop layer 105 is aluminum oxide.

[0096] Specifically, there is an etching selectivity ratio between aluminum oxide and the material selected for subsequently forming the first stacking structure. In the subsequent step of forming the first electrode column accommodating hole, aluminum oxide can serve as an etching stop. At the same time, aluminum oxide has a lower dielectric constant, which can reduce signal delay and interference. Moreover, aluminum oxide has good adhesion to metal materials, so that aluminum oxide can form a stable interface with the first electrode column.

[0097] In this embodiment, the material of the protection layer 109 is silicon oxide.

[0098] Specifically, silicon oxide can protect the first etch stop layer 104 . In the subsequent pickling process, the pickling solution cannot easily remove silicon oxide, so silicon oxide can block the pickling solution.

[0099] In this embodiment, Figure 13B As shown, the protective layer 109 and the first silicon oxide layer 1101 in the first stacked structure formed subsequently are integrally formed.

[0100] Specifically, the protective layer 109 and the first silicon oxide layer in the subsequently formed first stacked structure are integrally formed, which can reduce the deposition steps in forming the first stacked structure and reduce process costs.

[0101] In this embodiment, the grooves enclosed by the patterned first etch stop layer 104 and the second etch stop layer 105 are filled with a protective material and planarized to form a protective material layer. The protective material layer includes a protective layer 109 and a first silicon oxide layer 1101 .

[0102] Continue to refer Figures 13A to 14B , a first stacked structure 110 is formed on the etch stop structure.

[0103] It should be noted that the first stacked structure 110 provides a process basis for subsequently forming a capacitor structure.

[0104] As an example, the first stacked structure 110 includes a silicon oxide layer 1101 and a silicon nitride layer 1102 that are alternately and cyclically deposited on the etch stop structure, and the uppermost layer of the first stacked structure 110 is the silicon oxide layer 1101 .

[0105] Specifically, after the silicon nitride layer 1102 is subsequently pickled, a capacitor dielectric layer and a second electrode layer will be formed in the space released by the silicon nitride layer 1102. Correspondingly, the silicon oxide layer 1101 electrically isolates the adjacent capacitor unit array layer. In addition, the top layer of the first stacked structure 110 is the silicon oxide layer 1101, so that the top silicon oxide layer 1101 protects the subsequently formed capacitor structure. At the same time, the bottom layer of the first stacked structure 110 is also the silicon oxide layer 1101, so that the bottom silicon oxide layer 1101 can protect the top of the first etch stop layer 104, thereby reducing the probability of the pickling solution contacting the top of the first etch stop layer 104, and thus reducing the probability of the top of the first etch stop layer 104 being damaged.

[0106] As an example, the process of forming the first stacked structure 110 includes a thin film deposition process.

[0107] refer to Figures 15 and 16 , forming a first electrode column accommodating hole 126 that penetrates the first stacked structure 110 and the first etch stop layer 104, and the first electrode column accommodating hole 126 exposes the conductive part 101; preparing a first electrode column 128 in the first electrode column accommodating hole 126, and the first electrode column 128 is in contact with and connected to the conductive part 101.

[0108] Specifically, the first electrode pillar 128 can form a capacitor structure with the capacitor dielectric layer and the second electrode layer subsequently formed in the space released by the silicon nitride layer 1102 .

[0109] In this embodiment, the process of forming the first electrode column receiving hole 126 includes a dry etching process.

[0110] In this embodiment, after the first electrode pillars 128 are formed, slit openings are formed through the first stacked structure 110 .

[0111] refer to Figure 17 , a slit opening 130 is formed penetrating the first stacked structure 110 , and the slit opening 130 exposes the second etch stop layer 105 .

[0112] Specifically, the slit opening 130 provides a process window for subsequent acid washing to remove the silicon nitride layer 1102 , allowing the acid washing solution to enter the silicon nitride layer 1102 through the slit opening 130 and remove the silicon nitride layer 1102 .

[0113] In this embodiment, the step of forming the slit opening 130 includes: patterning the first stacked structure 110 with the second etch stop layer 105 as the etching stop position, and forming the slit opening 130 penetrating the first stacked structure 110 on top of the second etch stop layer 105 .

[0114] Specifically, using the second etch stop layer 105 as the etching stop position can reduce the probability of the slit opening 130 penetrating the base structure 102 , thereby reducing the risk of the slit opening 130 damaging the film layer below the base structure 102 .

[0115] As an example, the process of forming the slit opening 130 includes a dry etching process.

[0116] refer to Figure 18 After forming the slit opening 130 , the above-mentioned forming method further includes: performing acid washing to remove all silicon nitride layers 1102 in the first stacked structure 110 through the slit opening 130 .

[0117] Specifically, acid washing and removal of the silicon nitride layer 1102 can release the space occupied by the silicon nitride layer 1102 , which is beneficial for the subsequent formation of a capacitor dielectric layer and a second electrode layer in the space released by the silicon nitride layer 1102 to form a capacitor structure.

[0118] In this embodiment, while all the silicon nitride layers 1102 in the first stacked structure 110 are removed by acid etching through the slit openings 130 , the second etch stop layer 105 is also partially or completely removed by acid etching.

[0119] Specifically, the first etch stop layer and the second etch stop layer are made of the same material, which includes aluminum oxide. A chemical reaction occurs between the pickling solution and the aluminum oxide, thereby partially or completely removing the second etch stop layer 105 .

[0120] As an example, during the process of performing acid washing to remove all silicon nitride layers 1102 in the first stacked structure 110 , the acid washing solution includes phosphoric acid.

[0121] Figures 19 to 22 A schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention is shown.

[0122] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The differences between the embodiment of the present invention and the first embodiment are as follows:

[0123] refer to Figures 19 to 22 The first etch stop layer 204 and the second etch stop layer 209 are made of different materials, and a contact interface is formed between the first etch stop layer 204 and the second etch stop layer 209 .

[0124] Specifically, a contact interface is formed between the first etch stop layer 204 and the second etch stop layer 209. In the subsequent process of pickling the first stack structure through the slit opening, the pickling solution can also chemically react with the first etch stop layer 204. Since the materials of the first etch stop layer 204 and the second etch stop layer 209 are different, the second etch stop layer 209 protects the side wall of the first etch stop layer 204 of the capacitor area 200A, reducing the probability of the pickling solution contacting the first etch stop layer 204 during the subsequent pickling process, thereby reducing the probability of the first etch stop layer 204 of the capacitor area 200A being damaged.

[0125] As an example, the step of forming an etch stop structure on the base structure 202 includes: Figure 19 As shown, an etch stop material layer 203 is formed on the base structure 202 to cover the entire surface; Figure 20 As shown, the etch stop material layer 203 is patterned to form a first etch stop layer 204 and a second etch stop layer receiving groove 205 that are isolated from each other; Figures 21 to 22 As shown, a second etch stop material layer 208 is filled into the second etch stop layer accommodating groove 205 and the surface is planarized to form a second etch stop layer 209; wherein, the materials of the first etch stop layer 204 and the second etch stop layer 209 are different, and a contact interface is formed between the first etch stop layer 204 and the second etch stop layer 209.

[0126] Specifically, the second etch stop layer receiving groove 205 provides a space for filling the second etch stop layer 209 .

[0127] In this embodiment, the steps of forming the first etch stop layer 204 and the second etch stop layer accommodating groove 205 isolated from each other include: forming a patterned mask layer on the top of the etch stop material layer 203, the mask layer exposing the top surface of the etch stop material layer 203 in the logic area 200B; using the mask layer as a mask, patterning the etch stop material layer 203, removing the etch stop material layer 203 in the logic area 200B, forming the second etch stop layer accommodating groove 205 in the logic area 200B, and using the remaining etch stop material layer 203 located in the capacitor area 200A as the first etch stop layer 204.

[0128] In this embodiment, the step of performing surface planarization processing on the second etch stop material layer 208 includes: using the top surface of the first etch stop layer 204 as a stop position, and performing planarization processing on the second etch stop material layer 208 higher than the top surface of the first etch stop layer 204 .

[0129] In this embodiment, the material of the first etch stop layer 204 includes aluminum oxide, and the material of the second etch stop layer 209 includes amorphous silicon.

[0130] Specifically, there is an etching selectivity ratio between the aluminum oxide selected for the first etch stop layer 204 and the material selected for subsequently forming the first stacked structure. In the subsequent step of forming the first electrode column accommodating hole, the aluminum oxide can act as an etching stop. At the same time, aluminum oxide has a lower dielectric constant, which can reduce signal delay and interference. Moreover, aluminum oxide has good adhesion to metal materials, so that a stable interface can be formed between aluminum oxide and the first electrode column.

[0131] It should be noted that the second etch stop layer 209 is made of acid-resistant amorphous silicon, which can protect the first etch stop layer 204 during the subsequent acid washing process. At the same time, there is an etching selectivity ratio between amorphous silicon and the silicon nitride layer and the silicon oxide layer, so that the second etch stop layer 209 can play an etching stop role in the process of forming the slit opening.

[0132] Figures 23 to 27 A schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention is shown.

[0133] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The differences between the embodiment of the present invention and the first embodiment are as follows:

[0134] refer to Figures 23 to 27 , forming an etch stop structure on the base structure 302, including the following steps: Figure 23 As shown, an etch stop material layer 303 is formed on the base structure 302 to cover the entire surface; Figure 24 As shown, the etch stop material layer 303 is patterned to form a first etch stop layer 360, the first etch stop layer 360 includes a plurality of first etch stop unit layers 304, and each first etch stop unit layer 304 covers the top of a conductive portion 301; Figure 25 As shown, a second insulating material layer is filled into the isolation grooves between the plurality of patterned first etch stop unit layers 304 and the surface is planarized to form a second insulating layer 308, the top surface of the second insulating layer 308 being flush with the top surface of the first etch stop layer 360; Figure 26 As shown, a second etch stop layer receiving groove 312 is formed through the second insulating layer 308; Figure 27 As shown, a second etch stop material layer 303 is filled into the second etch stop layer accommodating groove 312 and the surface is flattened to form a second etch stop layer 313, and a second insulating material layer between the second etch stop layer 313 and the first etch stop layer 360 is used as a protective layer 320; wherein, the first etch stop layer 360 and the second etch stop layer 313 are made of the same material.

[0135] It should be noted that each first etch stop unit layer 304 corresponds to covering the top of a conductive part 301, which means that in the process of patterning the etch stop material layer 303 to form the first etch stop layer 360, a photolithography mask plate for patterning the conductive part 301 can be used, that is, the same photolithography mask plate is used to form the conductive part 301 and the first etch stop layer 360, which can reduce the number of photolithography mask plates used and reduce the cost of using the photolithography mask plates.

[0136] Specifically, the second insulating layer 308 is used to electrically isolate adjacent first etch stop unit layers 304 , thereby reducing the risk of electrical leakage between adjacent first etch stop unit layers 304 .

[0137] The second insulating layer 308 covers the top of the first insulating layer 300 in the capacitor region.

[0138] The second etch stop layer receiving groove 312 provides a space for forming a second etch stop layer 313 .

[0139] It should be noted that in the process of forming the second etch stop layer 313, the second insulating material layer between the second etch stop layer 313 and the first etch stop layer 360 is used as a protective layer 320, so that the protective layer 320 protects the side wall of the first etch stop layer 360 and reduces the risk of the first etch stop layer 360 being removed by the pickling solution.

[0140] As an example, the material of the second insulating layer 308 includes silicon oxide.

[0141] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate structure having a capacitor region and an adjacent logic region, the capacitor region and the logic region being used as a capacitor unit array region, the substrate structure comprising a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer, the conductive portions being located in the capacitor region, and the first insulating layer exposing top surfaces of the conductive portions; a first etch stop layer, located in the capacitor region and covering at least a top portion of the conductive portion; a second etch-stop layer, located in the logic area and covering a top portion of the first insulating layer, wherein the second etch-stop layer and the first etch-stop layer are located in the same layer and top surfaces of the second etch-stop layer and the first etch-stop layer are flush with each other; a first stacked structure covering the layer where the first etch stop layer and the second etch stop layer are located; a plurality of first electrode columns, each of the first electrode columns being disposed through the first stacked structure and the first etch-stop layer and being in contact with and connected to the corresponding conductive portion; a slit opening penetrating the first stacked structure and exposing the second etch stop layer; In which, the first etch stop layer and the second etch stop layer are made of the same material, and the first etch stop layer and the second etch stop layer are isolated by a protective layer, so that the protective layer protects the side wall of the first etch stop layer during the process of pickling the first stack structure through the slit opening; or, the first etch stop layer and the second etch stop layer are made of different materials, and a contact interface is formed between the first etch stop layer and the second etch stop layer, so that the second etch stop layer protects the side wall of the first etch stop layer during the process of pickling the first stack structure through the slit opening.

2. The semiconductor structure according to claim 1, wherein The first stacked structure includes a silicon oxide layer and a silicon nitride layer that are alternately and cyclically deposited on the layer where the first etch stop layer and the second etch stop layer are located, and the uppermost layer of the first stacked structure is a silicon oxide layer.

3. The semiconductor structure according to claim 1, wherein: The first etch stop layer and the second etch stop layer are made of the same material, that is, aluminum oxide, and the protective layer is made of silicon oxide.

4. The semiconductor structure according to claim 1, wherein The first etch stop layer and the second etch stop layer are made of different materials. The first etch stop layer is made of aluminum oxide, and the second etch stop layer is made of amorphous silicon.

5. The semiconductor structure according to claim 1, wherein The first etch stop layer covers the surface of the capacitor region of the substrate structure.

6. The semiconductor structure according to claim 1, wherein The first etch stop layer includes a plurality of first etch stop unit layers arranged at intervals, each of the first etch stop unit layers covering the top of the corresponding conductive portion; The semiconductor structure further includes: a second insulating layer covering the top of the base structure exposed by the plurality of first etch stop unit layers, the second insulating layer being flush with the top of the first etch stop layer, that is, the plurality of first etch stop unit layers are spaced and embedded in the second insulating layer.

7. The semiconductor structure according to claim 6, wherein: The second insulating layer and the protective layer are integrally formed; The material of the second insulating layer includes silicon oxide.

8. A method for forming a semiconductor structure, characterized in that: include: A substrate structure is provided, the substrate structure having a capacitor region and an adjacent logic region, the capacitor region and the logic region being used as a capacitor unit array region, the substrate structure comprising a first insulating layer and a plurality of conductive portions spaced apart and embedded in the first insulating layer, the conductive portions being located in the capacitor region, and the first insulating layer exposing top surfaces of the conductive portions; An etch stop structure is formed on the base structure, wherein the etch stop structure comprises: a first etch stop layer, located in the capacitor region and covering at least a top portion of the conductive portion; a second etch-stop layer, located in the logic area and covering a top portion of the first insulating layer, wherein the first etch-stop layer and the second etch-stop layer are located in the same layer and top surfaces of the first etch-stop layer and the second etch-stop layer are flush with each other; forming a first stacked structure on the etch stop structure; forming a plurality of first electrode column accommodating holes penetrating the first stack structure, wherein the first electrode column accommodating holes expose the conductive portion; Preparing a first electrode column in the first electrode column accommodating hole, wherein the first electrode column is in contact with and connected to the conductive portion; forming a slit opening penetrating the first stack structure, wherein the slit opening exposes the second etch stop layer; In which, the first etch stop layer and the second etch stop layer are made of the same material, and the first etch stop layer and the second etch stop layer are isolated by a protective layer, so that the protective layer protects the side wall of the first etch stop layer during the process of pickling the first stack structure through the slit opening; or, the first etch stop layer and the second etch stop layer are made of different materials, and a contact interface is formed between the first etch stop layer and the second etch stop layer, so that the second etch stop layer protects the side wall of the first etch stop layer during the process of pickling the first stack structure through the slit opening.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming an etch stop structure on the base structure comprises: forming an etch stop material layer covering the entire surface of the substrate structure; Patterning the etch stop material layer to form a first etch stop layer and a second etch stop layer isolated from each other, wherein the first etch stop layer covers the surface of the capacitor region of the substrate structure, and the second etch stop layer covers the surface of the logic region of the substrate structure; The groove formed by the patterned first etch stop layer and the second etch stop layer is filled with protective material and flattened to form a protective layer, the top surface of the protective layer is flush with the top surfaces of the first etch stop layer and the second etch stop layer, and the first etch stop layer and the second etch stop layer are isolated by the protective layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The first stacked structure includes a silicon oxide layer and a silicon nitride layer that are alternately and cyclically deposited on the etch stop structure. The protective layer is made of silicon oxide. The protective layer and the first silicon oxide layer in the first stacked structure are integrally formed. The forming method includes: The grooves formed by the patterned first etch stop layer and the second etch stop layer are filled with a protective material and planarized to form a protective material layer. The protective material layer includes the protective layer and the first silicon oxide layer.

11. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming an etch stop structure on the base structure comprises: forming an etch stop material layer covering the entire surface of the substrate structure; Patterning the etch stop material layer to form a first etch stop layer and a second etch stop layer receiving groove isolated from each other; Filling the second etch stop layer receiving groove with a second etch stop material layer and performing surface planarization treatment to form a second etch stop layer; The first etch stop layer and the second etch stop layer are made of different materials, and a contact interface is formed between the first etch stop layer and the second etch stop layer.

12. The method for forming a semiconductor structure according to claim 8, wherein: Forming an etch stop structure on the substrate structure comprises the following steps: forming an etch stop material layer covering the entire surface of the substrate structure; Patterning the etch stop material layer to form a first etch stop layer, wherein the first etch stop layer includes a plurality of first etch stop unit layers, and each of the first etch stop unit layers covers a top portion of the conductive portion; Filling the isolation trenches between the patterned first etch stop unit layers with a second insulating material layer and performing surface planarization to form a second insulating layer, wherein the top surface of the second insulating layer is flush with the top surface of the first etch stop layer; forming a second etch stop layer accommodating groove penetrating the second insulating layer; Filling the second etch stop layer receiving groove with a second etch stop material layer and performing surface planarization treatment to form a second etch stop layer, and using the second insulating material layer between the second etch stop layer and the first etch stop layer as the protective layer; The first etch stop layer and the second etch stop layer are made of the same material.

13. The method for forming a semiconductor structure according to claim 8, wherein: The first stacked structure includes a silicon oxide layer and a silicon nitride layer that are alternately and cyclically deposited on the etch stop structure, and the uppermost layer of the first stacked structure is the silicon oxide layer; After forming the slit opening, the forming method further includes: performing acid washing to remove all silicon nitride layers in the first stacked structure through the slit opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The first etch stop layer and the second etch stop layer are made of the same material, the first etch stop layer and the second etch stop layer include aluminum oxide, and the protective layer includes silicon oxide; While all silicon nitride layers in the first stacked structure are removed by acid etching through the slit opening, the second etch stop layer is also partially or completely removed by acid etching.

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