Groove type MOSFET structure and manufacturing method thereof

Abstract

The invention provides a trench type MOSFET structure and a manufacturing method, and the manufacturing method comprises the steps: providing a first conductive type substrate, forming a first conductive type epitaxial layer on the substrate, and forming a second conductive type well region at one side, far away from the substrate, of the epitaxial layer; a first groove is formed in the epitaxial layer, the first groove is located in the terminal area, and the first groove vertically penetrates through the epitaxial layer and extends into the substrate; insulating layers are formed on the side walls and the bottoms of the first grooves, first through holes are formed in the bottoms of the insulating layers, and the first through holes are exposed out of the substrate; and filling a conductive layer in the first groove, wherein the bottom end of the conductive layer extends into the first through hole and is electrically connected with the substrate. The first groove penetrating through the epitaxial layer is formed in the terminal region, so that the drain end of the device can be led out from the front surface, and the application range of the device is expanded; in addition, thick insulating layers are arranged on the side wall and the bottom of the first groove, the electric field concentration effect of a terminal area can be relieved, reverse breakdown working stability is improved, and the terminal size is remarkably reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a trench MOSFET structure and a manufacturing method. Background Art

[0002] MOSFET, or metal oxide semiconductor field effect transistor, has the advantages of high input impedance, low driving power, faster switching speed, better frequency characteristics and higher thermal stability. It has always occupied a very important position in semiconductor power devices.

[0003] Conventional trench MOSFET structure such as Figure 1 As shown, an epitaxial layer 2 is formed on the substrate 1, and the trenches in the cell area 001 and the trenches in the terminal area 002 have the same structure. ) After isolation, the trench located in the cell area 001 is filled with polysilicon to form a gate polysilicon layer 8, and the trench located in the terminal area 002 is filled with a conductive layer 13 as a floating electrode, wherein the source metal layer 15 and the gate metal layer 17 are formed on the front side of the device, and the drain metal layer 14 is formed on the back side of the device. Figure 2 As shown, it is shown as Figure 1 The schematic diagram of the electric field line distribution of the MOSFET structure terminal during reverse breakdown is shown. The electric field and potential of the terminal trench silicon dioxide dielectric layer are relatively concentrated. As the rated voltage of the device increases, reverse breakdown instability is prone to occur, resulting in abnormal reverse breakdown operation of the device. In addition, with the urgent market demand for new energy, automotive electronics and other fields, the integration requirements of semiconductor devices are getting higher and higher, and the packaging requirements for IC and power devices are also increasing. The drain end of the conventional trench MOSFET is led out from the back of the device, and in the process of IC sealing, some packages require the drain end of the MOSFET to be led out from the front of the device, which has certain restrictions on the integrated packaging of the device; the conventional planar MOSFET can lead the source and drain ends of the device from the front of the device, but its on-resistance (Rsp) is large, which limits its application.

[0004] Therefore, how to provide a trench MOSFET structure and manufacturing method to lead the drain end out from the front of the device to expand its application, alleviate the electric field concentration in the terminal area and improve the reverse breakdown working stability has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a trench MOSFET structure and a manufacturing method for solving the problems in the prior art that the drain terminal of the trench MOSFET is led out from the back side, which limits its application, and the electric field concentration in the terminal area leads to unstable reverse breakdown.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a trench MOSFET structure, wherein the trench MOSFET structure includes a cell region and a terminal region located outside the cell region, and the manufacturing method includes the following steps:

[0007] Providing a first conductive type substrate, forming a first conductive type epitaxial layer on the substrate, and forming a second conductive type well region on a side of the epitaxial layer away from the substrate;

[0008] Forming a first trench in the epitaxial layer, wherein the first trench is located in the terminal region, and the first trench vertically penetrates the epitaxial layer and extends into the substrate;

[0009] forming an insulating layer on the sidewall and the bottom of the first trench, and forming a first through hole at the bottom of the insulating layer, wherein the first through hole exposes the substrate;

[0010] A conductive layer is filled in the first trench, and a bottom end of the conductive layer extends into the first through hole to be electrically connected to the substrate.

[0011] Optionally, after forming the conductive layer, the method further includes the following steps: forming a source metal layer and a drain metal layer above the epitaxial layer, wherein the drain metal layer is electrically connected to the top of the conductive layer.

[0012] Optionally, before forming the insulating layer on the sidewall and the bottom of the first trench, the method further includes the following steps:

[0013] forming a second trench in the epitaxial layer, wherein the second trench is located in the cell region, and a depth of the second trench is greater than a depth of the well region and less than a thickness of the epitaxial layer;

[0014] forming a gate oxide layer on the sidewall and bottom of the second trench, and forming a gate polysilicon layer in the second trench;

[0015] A first conductive type source region is formed in a well region located in the cell region, wherein the source metal layer is electrically connected to the source region.

[0016] Optionally, the thickness of the insulating layer is not less than

[0017] Optionally, there are multiple first grooves, and the multiple first grooves are spaced apart by a preset distance in the horizontal direction and are arranged in a ring outside the cell area.

[0018] The present invention further provides a trench MOSFET structure, wherein the trench MOSFET structure is divided into a cell region and a terminal region located outside the cell region, comprising:

[0019] a first conductive type substrate;

[0020] An epitaxial layer of a first conductivity type is located above the substrate, and a side of the epitaxial layer away from the substrate has a well region of a second conductivity type;

[0021] A first trench, located in the terminal region, wherein the first trench vertically penetrates the epitaxial layer and extends into the substrate;

[0022] an insulating layer, located on the sidewall and bottom of the first groove, wherein a first through hole is provided at the bottom of the insulating layer, and the first through hole exposes the substrate;

[0023] A conductive layer is located in the first groove, and a bottom end of the conductive layer extends into the first through hole to be electrically connected to the substrate.

[0024] Optionally, a leakage metal layer is further included, wherein the leakage metal layer is located above the epitaxial layer, and the leakage metal layer is electrically connected to the top of the conductive layer.

[0025] Optionally, it also includes:

[0026] A second trench is located in the epitaxial layer of the cell region, wherein a depth of the second trench is greater than a depth of the well region and less than a thickness of the epitaxial layer;

[0027] a gate oxide layer, located on the sidewall and bottom of the second trench;

[0028] a gate polysilicon layer, located in the second trench;

[0029] A first conductive type source region, located in the well region of the cell region;

[0030] A source metal layer is located above the epitaxial layer, and the source metal layer is electrically connected to the source region.

[0031] Optionally, the thickness of the insulating layer is not less than

[0032] Optionally, there are multiple first grooves, and the multiple first grooves are spaced apart by a preset distance in the horizontal direction and are arranged in a ring outside the cell area.

[0033] As described above, in the trench MOSFET structure and manufacturing method of the present invention, by setting a first trench penetrating the epitaxial layer in the terminal area, the device drain terminal can be led out from the front side, thereby expanding its application range; and, setting a thick insulating layer on the sidewall and bottom of the first trench can alleviate the electric field concentration effect in the terminal area and improve the reverse breakdown working stability; in addition, since the number of first trenches in the terminal area is small, the terminal size can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1Shown is a schematic diagram of the structure of a conventional trench MOSFET.

[0035] Figure 2 Display as Figure 1 The schematic diagram of the electric field line distribution at the terminal of the MOSFET structure during reverse breakdown is shown.

[0036] Figure 3 Shown is a flow chart of the method for manufacturing the trench MOSFET structure of the present invention.

[0037] Figure 4 It is a schematic diagram showing the method for manufacturing a trench MOSFET structure of the present invention, wherein an epitaxial layer is formed on a substrate, and a well region is formed on a side of the epitaxial layer away from the substrate.

[0038] Figure 5 It is a schematic diagram showing the formation of a first trench and a second trench in the method for manufacturing a trench MOSFET structure of the present invention.

[0039] Figure 6 It is a schematic diagram showing the formation of a gate oxide layer in the method for manufacturing a trench MOSFET structure of the present invention.

[0040] Figure 7 It is a schematic diagram showing the formation of a polysilicon material layer in the method for manufacturing a trench MOSFET structure of the present invention.

[0041] Figure 8 It is a schematic diagram showing the formation of a gate polysilicon layer and a source region in the method for manufacturing a trench MOSFET structure of the present invention.

[0042] Fig. 9 It is a schematic diagram showing the formation of an insulating layer and the formation of a first through hole at the bottom of the insulating layer in the method for manufacturing a trench MOSFET structure of the present invention.

[0043] Fig.10 It is a schematic diagram showing the formation of a source metal layer and a drain metal layer in the method for manufacturing a trench MOSFET structure of the present invention.

[0044] Fig.11 Shown is a schematic layout diagram of the trench MOSFET structure of the present invention.

[0045] Fig.12 It is a schematic diagram showing the electric field line distribution of the MOSFET structure terminal of the present invention during reverse breakdown.

[0046] Component number description

[0047] 001 Cell Area

[0048] 002 Terminal Area

[0049] 1 Base

[0050] 2 Epitaxial layer

[0051] 3 Well region

[0052] 4 First groove

[0053] 5 Second groove

[0054] 6 Gate Oxide Layer

[0055] 7 Polysilicon material layer

[0056] 8 Gate polysilicon layer

[0057] 9 Source area

[0058] 10 Insulation layer

[0059] 11 First through hole

[0060] 12 Second through hole

[0061] 13 Conductive layer

[0062] 14 Leaky Metal Layer

[0063] 15 Source Metal Layer

[0064] 16 Passivation layer

[0065] 17 Gate metal layer

[0066] 18 Drain pad

[0067] 19 Source pad

[0068] 20 Gate terminal pad

[0069] 21 Third Groove

[0070] Steps S1 to S4 DETAILED DESCRIPTION

[0071] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] See also Figures 1 to 12It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0073] This embodiment provides a method for manufacturing a trench MOSFET structure. Figure 3 , shown as a flow chart of the production method, comprising the following steps:

[0074] S1: providing a first conductive type substrate, forming a first conductive type epitaxial layer on the substrate, and forming a second conductive type well region on a side of the epitaxial layer away from the substrate;

[0075] S2: forming a first trench in the epitaxial layer, wherein the first trench is located in the terminal region, and the first trench vertically penetrates the epitaxial layer and extends into the substrate;

[0076] S3: forming an insulating layer on the sidewall and the bottom of the first trench, and forming a first through hole at the bottom of the insulating layer, wherein the first through hole exposes the substrate;

[0077] S4: filling a conductive layer in the first trench, wherein a bottom end of the conductive layer extends into the first through hole to be electrically connected to the substrate.

[0078] First, see Figure 4 , perform step S1: provide a first conductive type substrate 1, form a first conductive type epitaxial layer 2 on the substrate 1, and form a second conductive type well region 3 on a side of the epitaxial layer 2 away from the substrate 1.

[0079] As an example, the trench MOSFET structure includes a cell region 001 and a terminal region 002 located at the periphery of the cell region 001 .

[0080] As an example, the substrate 1 can be a silicon substrate, a germanium substrate, a III-V group element compound substrate, a silicon carbide substrate, or a diamond substrate or other semiconductor material substrates known to those skilled in the art; the epitaxial layer 2 can be the same material as the substrate 1 (homoepitaxy), or a different material (heteroepitaxy), which can be selected according to needs.

[0081] As an example, the first conductivity type is N type, and the second conductivity type is P type. In other examples, the first conductivity type may be P type, and the second conductivity type may be N type.

[0082] As an example, the well region 3 located in the cell region 001 is used as a device body region, and the well region 3 located in the terminal region 002 is used as a field limiting ring.

[0083] Next, see Figure 5 , perform step S2: forming a first trench 4 in the epitaxial layer 2, wherein the first trench 4 is located in the terminal area 002, and the first trench 4 vertically penetrates the epitaxial layer 2 and extends into the substrate 1.

[0084] As an example, the first groove 4 is formed by etching. The process of forming the first groove 4 also includes the step of forming a second groove 5 in the epitaxial layer 2. The second groove 5 is located in the cell area 001. The depth of the second groove 5 is greater than the depth of the well area 3 and less than the thickness of the epitaxial layer 2.

[0085] As an example, because the depth of the first trench 4 is greater than the depth of the second trench 5, the characteristic dimension CD (opening width) of the first trench 4 is set to be greater than the characteristic dimension CD of the second trench 5, so as to facilitate deep trench etching of the first trench 4. Of course, a mask layer can also be added to perform deep trench etching on the terminal area 002 alone.

[0086] Next, see Fig. 9 , executing step S3: forming an insulating layer 10 on the sidewall and the bottom of the first trench 4 , and forming a first through hole 11 at the bottom of the insulating layer 10 , wherein the first through hole 11 exposes the substrate 1 .

[0087] As an example, before forming the insulating layer 10 on the sidewall and the bottom of the first trench 4, the following steps are also included:

[0088] (a) If Figure 6 As shown, a gate oxide layer 6 is formed on the sidewalls and bottom of the second trench 5, wherein the gate oxide layer 6 is also formed on the upper surface of the epitaxial layer 2 and the sidewalls and bottom of the first trench 4;

[0089] (ii) Figure 7 As shown, a polysilicon material layer 7 is formed in the second trench 5, wherein the polysilicon material layer 7 is also formed above the epitaxial layer 2 and in the second trench 4;

[0090] (III) Figure 8As shown, the polysilicon material layer 7 located above the epitaxial layer 2 and the polysilicon material layer 7 located in the first groove 4 are removed by etching, and the polysilicon material layer 7 in the second groove 5 is retained as the gate polysilicon layer 8; wherein, the polysilicon material layer 7 inside the first groove 4 can be completely etched by adopting an isotropic etching process without adding an additional photomask; in addition, after the etching of the polysilicon material layer 7 is completed, an ion implantation process is adopted to form a first conductive type source region 9 in the well region 3 in the cell region 001;

[0091] As an example, after forming the source region 9 , the insulating layer 10 is formed on the sidewalls and bottom of the first trench 4 , wherein the insulating layer 10 is made of silicon oxide, and the gate oxide layer 6 located on the sidewalls and bottom of the first trench 4 can serve as a part of the insulating layer 10 .

[0092] As an example, the thickness of the insulating layer 10 is not less than That is, a thick oxide layer is formed on the bottom and sidewalls of the first trench 4. In this embodiment, the thickness of the insulating layer 10 is set to Specifically, an interlayer dielectric (ILD) deposition process is used to realize the sidewalls and bottom thick oxide layer of the terminal deep trench, that is, the insulating layer 10 is also formed on the epitaxial layer 2 as an interlayer dielectric layer.

[0093] As an example, the process of forming the first through hole 11 by etching process also includes the step of forming the second through hole 12 , where the second through hole 12 is located in the cell region 001 and in the insulating layer 10 and extends into the source region 9 .

[0094] Next, see Fig.10 , executing step S4: filling the first trench 4 with a conductive layer 13 , wherein the bottom end of the conductive layer 13 extends into the first through hole 11 and is electrically connected to the substrate 1 .

[0095] As an example, the conductive layer 13 is used as a conductive plug to subsequently lead the drain metal layer 14 to the front side of the device.

[0096] As an example, the following steps are also included: forming a drain metal layer 14 (device drain terminal) and a source metal layer 15 (device source terminal) above the epitaxial layer 2, wherein the drain metal layer 14 is electrically connected to the substrate 1 through the conductive layer 13, and the source metal layer 15 extends into the second through hole 12 and is electrically connected to the source region 9; preferably, the source metal layer 15 penetrates the source region 9 and extends into the body region, which can prevent parasitic transistors from being generated between the substrate 1, the body region and the source region 9, and the source and drain are only equivalent to a body diode, thereby improving device performance.

[0097] As an example, a gate metal layer (not shown) is further formed above the epitaxial layer 2 , and the gate metal layer is electrically connected to the gate polysilicon 8 through trenches and contact vias.

[0098] As an example, after forming the drain metal layer 14, the source metal layer 15 and the gate metal layer, the step of forming a passivation layer 16 is also included, and the passivation layer 16 covers the drain metal layer 14, the source metal layer 15 and the gate metal layer; in addition, an opening is formed in the passivation layer 16 to expose the drain metal layer 14 as a drain pad, an opening is formed in the passivation layer 16 to expose the source metal layer 15 as a source pad, and an opening is formed in the passivation layer 16 to expose the gate metal layer as a gate pad.

[0099] At this point, a trench MOSFET structure is obtained. Fig.10 The trench MOSFET structure is divided into a cell area 001 and a terminal area 002 located at the periphery of the cell area 001, including a first conductive type substrate 1, a first conductive type epitaxial layer 2, a first trench 4, an insulating layer 10 and a conductive layer 13, wherein the epitaxial layer 2 is located above the substrate 1, and the side of the epitaxial layer 2 away from the substrate 1 has a second conductive type well region 3; the insulating layer 10 is located on the sidewall and bottom of the first trench 4, and a first through hole 11 is formed at the bottom of the insulating layer 10, and the first through hole 11 exposes the substrate 1; the conductive layer 13 is located in the first trench 4, and the bottom end of the conductive layer 13 extends into the first through hole 11 to be electrically connected to the substrate 1.

[0100] As an example, the first conductivity type is N type, and the second conductivity type is P type. In other examples, the first conductivity type may be P type, and the second conductivity type may be N type.

[0101] As an example, the well region 3 located in the cell region 001 is used as a device body region, and the well region 3 located in the terminal region 002 is used as a field limiting ring.

[0102] As an example, the thickness of the insulating layer 10 is not less than That is, a thick oxide layer is provided at the bottom and sidewall of the first trench 4; specifically, in this embodiment, the thickness of the insulating layer 10 is set to

[0103] As an example, a second trench 5 is also included, and the second trench 5 is located in the cell area 001. The depth of the second trench 5 is greater than the depth of the well area 3 and less than the thickness of the epitaxial layer 2. The sidewalls and bottom of the second trench 5 are provided with a gate oxide layer 6, and the second trench 5 is provided with a gate polysilicon layer 8.

[0104] As an example, a first conductive type source region 9 is arranged in the well region 3 located in the cell region 001, and an active metal layer 15 is arranged above the epitaxial layer 2. The source metal layer 15 is electrically connected to the source region 9. Preferably, the source metal layer 15 penetrates the source region 9 and extends into the body region, which can prevent the generation of parasitic transistors between the substrate 1, the body region and the source region 9. The source and drain are only equivalent to a body diode, thereby improving the device performance.

[0105] As an example, a drain metal layer 14 is arranged above the epitaxial layer 2, and the drain metal layer 14 is electrically connected to the top of the conductive layer 13, that is, the drain metal layer 14 is electrically connected to the substrate 1 through the conductive layer 13; a gate metal layer (not shown) is also arranged above the epitaxial layer 2, and the gate metal layer is electrically connected to the gate polysilicon 8 through grooves and contact holes.

[0106] As an example, a passivation layer 16 is also included, and the passivation layer 16 covers the drain metal layer 14, the source metal layer 15 and the gate metal layer, wherein an opening is provided in the passivation layer 16, and the opening exposes the drain metal layer 14 as a drain pad, the opening exposes the source metal layer 15 as a source pad, and the opening exposes the gate metal layer as a gate pad; specifically, please refer to 11, which shows a schematic layout diagram of the trench MOSFET structure of the present invention, the drain pad 18 is led out from the front of the device through the conductive layer filled in the first trench 4; the source pad 19 is connected to the source region and led out from the front of the device; the gate pad 20 is led out from the front of the device, and is electrically connected to the gate polysilicon layer 8 in the second trench 5 through the contact through hole and the third trench 21.

[0107] As an example, the source, gate and drain terminals of the device in the present invention are all led out from the front side of the device, which is suitable for application scenarios where the drain of the MOSFET is on the surface of the device in packaging requirements, thereby expanding its application scope.

[0108] As an example, see Fig.12 , which is a schematic diagram showing the electric field line distribution of the MOSFET structure terminal of the present invention during reverse breakdown. Under the same rated voltage, compared with the prior art, the terminal trench sidewall and bottom are formed to be no more than The trench thin silicon dioxide dielectric layer has a relatively concentrated potential and electric field distribution (see Figure 2 ), which is prone to reverse breakdown instability, resulting in abnormal reverse breakdown operation of the device. The thickness of the insulating layer 10 in the present invention is relatively thick, which can significantly alleviate the electric field and potential concentration effect in the terminal area and improve the reverse breakdown stability; Fig.12It can be seen that in this application, the electric field is mainly distributed in the first groove closest to the cell area, and the electric field is relatively weak at the second first groove closest to the cell area. Therefore, this application sets a first groove structure to significantly improve the reverse breakdown stability, and at most two annular first groove structures can be set. The two first grooves 4 are spaced by a preset distance in the horizontal direction and are arranged in a ring outside the cell area 001, which greatly reduces the terminal size. Of course, in other examples, the number of first grooves is appropriately increased when the required rated voltage increases, which also falls within the scope of protection of the present invention.

[0109] As an example, the first groove structure in the terminal region of this embodiment can lead the device drain terminal from the front side, expand its application, and can significantly alleviate the electric field concentration effect in the terminal region and improve the reverse breakdown working stability. Of course, in other examples, the device drain terminal can be set to be led out from the back side according to actual needs, and the first groove structure is only used to alleviate the electric field concentration effect in the terminal region to improve the reverse breakdown working stability, which is easy to fall into the scope protected by the present invention.

[0110] In summary, in the trench MOSFET structure and manufacturing method of the present invention, by setting a first trench penetrating the epitaxial layer in the terminal region, the device drain terminal can be led out from the front, expanding its application range; and, setting a thick insulating layer on the sidewall and bottom of the first trench can alleviate the electric field concentration effect in the terminal region and improve the reverse breakdown working stability; in addition, since the number of first trenches in the terminal region is small, the terminal size can be significantly reduced. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a trench MOSFET structure, characterized in that: The trench MOSFET structure includes a cell region and a terminal region located outside the cell region, and the manufacturing method includes the following steps: Providing a first conductive type substrate, forming a first conductive type epitaxial layer on the substrate, and forming a second conductive type well region on a side of the epitaxial layer away from the substrate; Forming a first trench in the epitaxial layer, wherein the first trench is located in the terminal region, and the first trench vertically penetrates the epitaxial layer and extends into the substrate; forming an insulating layer on the sidewall and the bottom of the first trench, and forming a first through hole at the bottom of the insulating layer, wherein the first through hole exposes the substrate; A conductive layer is filled in the first trench, and a bottom end of the conductive layer extends into the first through hole to be electrically connected to the substrate.

2. The method for manufacturing a trench MOSFET structure according to claim 1, characterized in that: After the conductive layer is formed, the method further includes the following steps: forming a source metal layer and a drain metal layer above the epitaxial layer, wherein the drain metal layer is electrically connected to the top of the conductive layer.

3. The method for manufacturing a trench MOSFET structure according to claim 2, characterized in that: Before forming the insulating layer on the sidewall and the bottom of the first trench, the method further includes the following steps: forming a second trench in the epitaxial layer, wherein the second trench is located in the cell region, and a depth of the second trench is greater than a depth of the well region and less than a thickness of the epitaxial layer; forming a gate oxide layer on the sidewall and bottom of the second trench, and forming a gate polysilicon layer in the second trench; A first conductive type source region is formed in a well region located in the cell region, wherein the source metal layer is electrically connected to the source region.

4. The method for manufacturing a trench MOSFET structure according to claim 1, wherein: The thickness of the insulating layer is not less than 5. The method for manufacturing a trench MOSFET structure according to claim 1, characterized in that: There are a plurality of the first grooves, and the plurality of the first grooves are spaced apart by a preset distance in the horizontal direction and are arranged in a ring outside the cell region.

6. A trench MOSFET structure, wherein the trench MOSFET structure is divided into a cell region and a terminal region located outside the cell region, characterized in that: include: a first conductive type substrate; An epitaxial layer of a first conductivity type is located above the substrate, and a side of the epitaxial layer away from the substrate has a well region of a second conductivity type; A first trench, located in the terminal region, wherein the first trench vertically penetrates the epitaxial layer and extends into the substrate; an insulating layer, located on the sidewall and bottom of the first groove, wherein a first through hole is provided at the bottom of the insulating layer, and the first through hole exposes the substrate; A conductive layer is located in the first groove, and a bottom end of the conductive layer extends into the first through hole to be electrically connected to the substrate.

7. The trench MOSFET structure according to claim 6, characterized in that: It also includes a leakage metal layer, which is located above the epitaxial layer and is electrically connected to the top of the conductive layer.

8. The trench MOSFET structure according to claim 7, characterized in that: Also includes: A second trench is located in the epitaxial layer of the cell region, wherein a depth of the second trench is greater than a depth of the well region and less than a thickness of the epitaxial layer; a gate oxide layer, located on the sidewall and bottom of the second trench; a gate polysilicon layer, located in the second trench; A first conductive type source region, located in the well region of the cell region; A source metal layer is located above the epitaxial layer, and the source metal layer is electrically connected to the source region.

9. The trench MOSFET structure according to claim 6, characterized in that: The thickness of the insulating layer is not less than 10. The trench MOSFET structure according to claim 6, characterized in that: There are a plurality of the first grooves, and the plurality of the first grooves are spaced apart by a preset distance in the horizontal direction and are arranged in a ring outside the cell region.

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