MOSFET structure and preparation method thereof

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a preparation method thereof. The MOSFET structure comprises a semiconductor substrate layer; the drift layer is positioned on one side of the semiconductor substrate layer; the first well region and the second well region are arranged in the drift layer at an interval; the JFET region is located in the drift layer between the first well region and the second well region, the JFET region comprises a first JFET region and a second JFET region, the first JFET region is located between the first well region and the second JFET region, the second JFET region is located between the second well region and the first JFET region, and the doping concentration of the first JFET region is larger than that of the second JFET region; and the gate structure covers the JFET region, a part of the surface of the first well region and a part of the surface of the second well region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon Carbide (SiC), a wide bandgap semiconductor material, has become an ideal choice for high-voltage, high-temperature, high-frequency, and high-power power electronic devices due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. SiC Metal-Oxide-Semiconductor FieldEffecTransistor (MOSFET) is a unipolar device with ideal gate insulation characteristics. There is no tail current during the shutdown process, which can greatly reduce switching losses and reduce the size of the heat sink. In addition, the high switching frequency of SiC MOSFET is conducive to reducing the size and weight of source filter components in power electronic devices, and improving the efficiency and power density of the device.

[0003] However, the reliability of MOSFET structures in related technologies needs to be improved. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to improve the reliability of the gate dielectric layer of the MOSFET structure in the related art.

[0005] In order to solve the above technical problems, the present invention provides a MOSFET structure, including: a semiconductor substrate layer; a drift layer, located on one side of the semiconductor substrate layer; a first well region and a second well region spaced apart in the drift layer; a JFET region in the drift layer between the first well region and the second well region, the JFET region including a first JFET region and a second JFET region, the first JFET region being located between the first well region and the second JFET region, the second JFET region being located between the second well region and the first JFET region, the doping concentration of the first JFET region being greater than the doping concentration of the second JFET region; and a gate structure covering the JFET region, a portion of the surface of the first well region and a portion of the surface of the second well region.

[0006] Optionally, it also includes: a first doped region, located on the side wall of the first well region facing the second well region and separated from the second well region; wherein the portion of the first doped region located on the side wall of the first well region facing the second well region constitutes the first JFET region, and the portion of the drift layer located in the first JFET region and the second well region constitutes the second JFET region.

[0007] Optionally, the first doped region is also located in the drift layer on a side of the first well region facing the semiconductor substrate layer.

[0008] Optionally, in a direction from the first well region to the second well region, a ratio of a size of a surface of the first JFET region facing the gate structure to a size of a surface of the second JFET region facing the gate structure is 1:1-3:1.

[0009] Optionally, in the direction from the first well region to the second well region, a size of the surface of the first JFET region facing the gate structure is 0.4 microns to 1.2 microns, and a size of the surface of the second JFET region facing the gate structure is 0.2 microns to 0.8 microns.

[0010] Optionally, it also includes: a second doped region, located on the side of the second well region facing the semiconductor substrate layer and in contact with the second well region, the second doped region has the same conductivity type as the second well region, and the doping concentration of the second doped region is less than the doping concentration of the second well region.

[0011] Optionally, the second doped region is spaced apart from the first JFET region; or, the second doped region is also located on a side of the second well region facing the first well region, and the second doped region is also in contact with the first JFET region, wherein the second JFET region is located on a side of the second doped region facing away from the semiconductor substrate layer.

[0012] The present application also provides a method for preparing a MOSFET structure, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a first well region and a second well region in the drift layer; forming a JFET region in the drift layer, the JFET region comprising a first JFET region and a second JFET region, the first JFET region being located between the first well region and the second JFET region, the second JFET region being located between the second well region and the first JFET region, the doping concentration of the first JFET region being greater than the doping concentration of the second JFET region; and forming a gate structure, the gate structure covering the JFET region, a portion of the surface of the first well region, and a portion of the surface of the second well region.

[0013] Optionally, forming a JFET region in the drift layer includes: forming a first doped region in the drift layer; wherein the first doped region is located on a side wall of the first well region facing the second well region and is spaced from the second well region; wherein a portion of the first doped region located on the side wall of the first well region facing the second well region constitutes the first JFET region, and a portion of the drift layer located in the first JFET region and the second well region constitutes the second JFET region.

[0014] Optionally, the first doped region is also located in the drift layer on a side of the first well region facing the semiconductor substrate layer.

[0015] Optionally, it also includes: forming a second doped region, the second doped region is located on the side of the second well region facing the semiconductor substrate layer and is in contact with the second well region, the second doped region has the same conductivity type as the second well region, and the doping concentration of the second doped region is less than the doping concentration of the second well region.

[0016] Optionally, forming the second doping region includes: forming the second doping region on a side of the second well region facing the semiconductor substrate layer, the second doping region being spaced apart from the first JFET region.

[0017] Optionally, it also includes: forming the second doped region on the side of the second well region facing the semiconductor substrate layer, the second doped region is in contact with the first JFET region; wherein the second JFET region is located on the side of the second doped region away from the semiconductor substrate layer.

[0018] Optionally, it also includes: forming a second initial doping region in the drift layer; wherein, forming the first well region and the first doping region includes: forming the first well region and the first doping region in a portion of the second initial doping region and in a portion of the drift layer away from the semiconductor substrate layer on the side of the second initial doping region; wherein, forming the second well region includes: forming the second well region in a portion of the second initial doping region and in a portion of the drift layer away from the semiconductor substrate layer on the side of the second initial doping region; wherein the second doping region is formed by a portion of the second initial doping region located on the side of the second well region facing the semiconductor substrate layer and a portion located between the second well region and the first doping region.

[0019] The technical solution of the present invention has the following technical effects:

[0020] In the MOSFET structure provided by the technical solution of the present invention, the doping concentration of the first JFET region is greater than the doping concentration of the second JFET region, the doping concentration of the second JFET region is relatively small, and the charge of the second JFET region is small. When the MOSFET structure is reversely withstand voltage, the second JFET region and the second well region are depleted, and the depletion region of the PN junction formed by the second JFET region and the second well region is more extended in the second JFET region. The second JFET region and the second well region can be depleted faster at a smaller voltage, reducing the electric field strength near the gate dielectric layer in the gate structure, protecting the gate dielectric layer, and improving the reliability of the MOSFET structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of a MOSFET structure provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a MOSFET structure provided by another embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a MOSFET structure provided by another embodiment of the present invention;

[0025] Figures 4 to 6 A structural diagram of a preparation process of a MOSFET structure provided by an embodiment of the present invention;

[0026] Figures 7 to 10 A structural diagram of a preparation process of a MOSFET structure provided by another embodiment of the present invention;

[0027] Figures 11 to 13 A structural diagram of a preparation process of a MOSFET structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0030] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] An embodiment of the present application provides a MOSFET structure, referring to Figure 1 ,include:

[0033] Semiconductor substrate layer 100;

[0034] The drift layer 110 is located on one side of the semiconductor substrate layer 100;

[0035] A first well region 121 and a second well region 122 are spaced apart in the drift layer 110;

[0036] A JFET region in the drift layer 110 between the first well region 121 and the second well region 122, the JFET region comprising a first JFET region 151 and a second JFET region 152, the first JFET region 151 being located between the first well region 121 and the second JFET region 152, the second JFET region 152 being located between the second well region 122 and the first JFET region 151, and the doping concentration of the first JFET region 151 being greater than the doping concentration of the second JFET region 152;

[0037] The gate structure covers the JFET region, a portion of the surface of the first well region 121 , and a portion of the surface of the second well region 122 .

[0038] In this embodiment, the doping concentration of the first JFET region 151 is greater than the doping concentration of the second JFET region 152, the doping concentration of the second JFET region 152 is relatively small, and the charge of the second JFET region 152 is small. When the MOSFET structure is reversely withstand voltage, the second JFET region 152 and the second well region 122 are depleted, and the depletion region of the PN junction formed by the second JFET region 152 and the second well region 122 is more extended in the second JFET region 152. The second JFET region 152 and the second well region 122 can be depleted faster at a lower voltage, reducing the electric field strength near the gate dielectric layer 161 in the gate structure, protecting the gate dielectric layer 161, and improving the reliability of the MOSFET structure.

[0039] In this embodiment, the new generation SiC-based MOSFET structure represented by SiC has higher reverse withstand voltage, lower forward conduction loss, faster switching frequency and stronger environmental tolerance compared to the Si-based MOSFET structure, and is therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0040] In this embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer is silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0041] In this embodiment, the conductivity type of the first well region 121 is opposite to the conductivity type of the drift layer 110. The conductivity type of the second well region 122 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the first well region 121 is P-type, and the conductivity type of the second well region 122 is P-type.

[0042] In this embodiment, the MOSFET structure further includes: a source region 130, a portion of the source region 130 is located in a portion of the first well region 121, and another portion of the source region 130 is located in a portion of the second well region 122. The conductivity type of the source region 130 is opposite to the conductivity type of the first well region 121, and the conductivity type of the source region 130 is opposite to the conductivity type of the second well region 122. In one embodiment, the conductivity types of the first well region 121 and the second well region 122 are P-type, and the conductivity type of the source region 130 is N-type.

[0043] The gate structure also covers a portion of the source region 130 .

[0044] In this embodiment, the MOSFET structure further includes: an ohmic contact region 131, a portion of the ohmic contact region 131 is located in the first well region 121 on the side of the source region 130 away from the JFET region, and another portion of the ohmic contact region 131 is located in the second well region 122 on the side of the source region 130 away from the JFET region. The conductivity type of the ohmic contact region 131 is the same as the conductivity type of the first well region 121 and the same as the conductivity type of the second well region 122. The doping concentration of the ohmic contact region 131 is greater than the doping concentration of the first well region 121 and greater than the doping concentration of the second well region 122.

[0045] In this embodiment, the gate structure includes a gate dielectric layer 161 and a gate electrode layer 162. The gate electrode layer 162 is located on a side of the gate dielectric layer 161 away from the drift layer 110. The gate dielectric layer 161 is made of silicon oxide. The gate electrode layer 162 is made of polysilicon.

[0046] In this embodiment, it also includes: a front electrode (not shown), which is in contact with the source region 130 and the ohmic contact region 131 ; and a drain metal layer, which is located on a surface of the semiconductor substrate layer 100 that is away from the drift layer 110 .

[0047] In this embodiment, the MOSFET structure further includes: a first doping region 140, which is located on the side wall of the first well region 121 facing the second well region 122 and is spaced from the second well region 122; wherein the portion of the first doping region 140 located on the side wall of the first well region 121 facing the second well region 122 constitutes a first JFET region 151, and the portion of the drift layer 110 located in the first JFET region 151 and the second well region 122 constitutes a second JFET region 152. The conductivity type of the first doping region 140 is the same as that of the drift layer 110, and the doping concentration of the first doping region 140 is greater than the doping concentration of the drift layer 110.

[0048] In this embodiment, the first doped region 140 is also located in the drift layer 110 on the side of the first well region 121 facing the semiconductor substrate layer 100. In other embodiments, the first doped region may not extend to the side of the first well region 121 facing the semiconductor substrate layer 100.

[0049] If the ratio of the size of the surface of the first JFET region 151 facing the gate structure to the size of the surface of the second JFET region 122 facing the gate structure in the direction from the first well region 121 to the second well region 122 is too small, the on-resistance of the MOSFET structure is limited; if the ratio of the size of the surface of the first JFET region 151 facing the gate structure to the size of the surface of the second JFET region 122 facing the gate structure in the direction from the first well region 121 to the second well region 122 is too large, the depletion region of the PN junction formed by the second JFET region and the second well region is limited in the expansion of the second JFET region in the second JFET region by the size of the second JFET region 122 in the direction from the first well region 121 to the second well region 122, thereby limiting the degree of protection of the gate dielectric layer. Preferably, the ratio of the size of the surface of the first JFET region 151 facing the gate structure to the size of the surface of the second JFET region 122 facing the gate structure in the direction from the first well region 121 to the second well region 122 is 1:1-3:1, for example, 1:1, 2:1 or 3:1.

[0050] Preferably, in the direction from the first well region 121 to the second well region 122, the size of the surface of the first JFET region 151 facing the gate structure is 0.4 microns to 1.2 microns, for example, 0.4 microns, 0.6 microns, 0.8 microns, 1 micron or 1.2 microns; the size of the surface of the second JFET region 122 facing the gate structure is 0.2 microns to 0.8 microns, for example, 0.2 microns, 0.4 microns, 0.6 microns or 0.8 microns.

[0051] Another embodiment of the present application further provides a MOSFET structure, referring to Figure 2 The difference between this embodiment and the previous embodiment is that the MOSFET structure also includes a second doping region 170, which is located on the side of the second well region 122 facing the semiconductor substrate layer 100 and is in contact with the second well region 122, the second doping region 170 has the same conductivity type as the second well region 122, and the doping concentration of the second doping region 170 is less than the doping concentration of the second well region 122.

[0052] In this embodiment, the second doping region 170 is spaced apart from the first JFET region 151 .

[0053] The second doped region 170 and the drift layer 110 at the bottom of the second doped region 170 form a PN junction, which further transfers the electric field peak into the drift layer 110, reduces the electric field peak at the interface between the first doped region 140 and the first well region 121, and improves the reliability of the MOSFET structure.

[0054] Preferably, the doping concentration of the second doping region 170 is 2E16atom / cm 3 -1E17 atom / cm 3 The doping concentration of the second well region 122 is 7E17 atom / cm 3 -5E18 atom / cm 3 .

[0055] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0056] Another embodiment of the present application further provides a MOSFET structure, referring to Figure 3The MOSFET structure further includes a second doping region 170, which is located on the side of the second well region 122 facing the semiconductor substrate layer 100 and in contact with the second well region 122. The second doping region 170 has the same conductivity type as the second well region 122, and the doping concentration of the second doping region 170 is less than the doping concentration of the second well region 122. The second doping region 170 is also located on the side of the second well region 122 facing the first well region 121, and the second doping region 170 is also in contact with the first JFET region 151, wherein the second JFET region 152 is located on the side of the second doping region 170 facing away from the semiconductor substrate layer 100.

[0057] The second doped region 170 and the drift layer 110 at the bottom of the second doped region 170 form a PN junction, which further transfers the electric field peak into the drift layer 110, reduces the electric field peak at the interface between the first doped region 140 and the first well region 121, and improves the reliability of the MOSFET structure.

[0058] Preferably, the doping concentration of the second doping region 170 is 2E16atom / cm 3 -1E17 atom / cm 3 The doping concentration of the second well region 122 is 7E17 atom / cm 3 -5E18 atom / cm 3 .

[0059] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0060] The present application also provides a method for preparing a MOSFET structure, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a first well region and a second well region in the drift layer; forming a JFET region in the drift layer, the JFET region comprising a first JFET region and a second JFET region, the first JFET region being located between the first well region and the second JFET region, the second JFET region being located between the second well region and the first JFET region, the doping concentration of the first JFET region being greater than the doping concentration of the second JFET region; and forming a gate structure, the gate structure covering the JFET region, a portion of the surface of the first well region, and a portion of the surface of the second well region.

[0061] Combine the following Figures 4 to 6 The preparation process of a MOSFET structure is introduced in detail.

[0062] refer to Figure 4 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100 .

[0063] The description of the semiconductor substrate layer 100 and the drift layer 110 refers to the aforementioned embodiment and will not be described in detail.

[0064] Continue to refer Figure 4 , a first initial doping region 140 a is formed in the drift layer 110 .

[0065] The conductivity type of the first preliminary doping region 140 a is the same as that of the drift layer 110 , and the doping concentration of the first preliminary doping region 140 a is greater than the doping concentration of the drift layer 110 .

[0066] The process of forming the first preliminary doping region 140 a includes an ion implantation process with a mask.

[0067] refer to Figure 5 , a first well region 121 and a second well region 122 are formed in the drift layer 110; a JFET region is formed in the drift layer 110, the JFET region includes a first JFET region 151 and a second JFET region 152, the first JFET region 151 is located between the first well region 121 and the second JFET region 152, the second JFET region 152 is located between the second well region 122 and the first JFET region 151, and the doping concentration of the first JFET region 151 is greater than the doping concentration of the second JFET region 152.

[0068] In this embodiment, forming the first well region 121 and the second well region 122 in the drift layer 110 includes: forming the first well region 121 in the first initial doping region 140a, and the area of ​​the first initial doping region 140a located outside the first well region 121 constitutes the first doping region 140; forming the second well region 122 in the drift layer 110, and the second well region 122 is separated from the first doping region 140.

[0069] In this embodiment, forming a JFET region in the drift layer 110 includes: forming a first doping region 140 in the drift layer 110; wherein the first doping region 140 is located on the side wall of the first well region 121 facing the second well region 122 and is spaced from the second well region 122. The portion of the first doping region 140 located on the side wall of the first well region 121 facing the second well region 122 constitutes a first JFET region 151, and the portion of the drift layer 110 located in the first JFET region 121 and the second well region 122 constitutes a second JFET region 152.

[0070] In this embodiment, the first doped region 140 is also located in the drift layer 110 on the side of the first well region 121 facing the semiconductor substrate layer 100. In other embodiments, the first doped region may not extend to the side of the first well region 121 facing the semiconductor substrate layer 100.

[0071] Continue to refer Figure 5 , forming a source region 130; and forming an ohmic contact region 131.

[0072] Regarding the positions of the source region 130 and the ohmic contact region 131 , reference is made to the description of the previous embodiment.

[0073] refer to Figure 6 , forming a gate structure, the gate structure covers the JFET region, a portion of the surface of the first well region 121 and a portion of the surface of the second well region 122. The gate structure includes a gate dielectric layer 161 and a gate electrode layer 162. The gate structure also covers a portion of the source region 130.

[0074] Another embodiment of the present application also provides a preparation process of a MOSFET structure. The difference between the preparation process of the present application and the aforementioned embodiment is that the preparation method of the MOSFET structure also includes: forming a second doping region, the second doping region is located on the side of the second well region facing the semiconductor substrate layer and is in contact with the second well region, the second doping region has the same conductivity type as the second well region, and the doping concentration of the second doping region is less than the doping concentration of the second well region.

[0075] Figures 7 to 10 A structural diagram of a preparation process of a MOSFET structure provided by another embodiment of the present invention.

[0076] refer to Figure 7 A drift layer 110 is formed on one side of the semiconductor substrate layer 100; a first well region 121 and a second well region 122 are formed in the drift layer 110; a JFET region is formed in the drift layer 110, the JFET region includes a first JFET region and a second JFET region, the first JFET region is located between the first well region 121 and the second JFET region, the second JFET region is located between the second well region 122 and the first JFET region, and the doping concentration of the first JFET region is greater than the doping concentration of the second JFET region.

[0077] In this embodiment, forming a JFET region in the drift layer 110 includes: forming a first doping region 140 in the drift layer 110; wherein the first doping region 140 is located on the side wall of the first well region 121 facing the second well region 122 and is spaced from the second well region 122. The portion of the first doping region 140 located on the side wall of the first well region 121 facing the second well region 122 constitutes a first JFET region, and the portion of the drift layer 110 located in the first JFET region and the second well region 122 constitutes a second JFET region.

[0078] In this embodiment, the first doped region 140 is also located in the drift layer 110 on the side of the first well region 121 facing the semiconductor substrate layer 100. In other embodiments, the first doped region may not extend to the side of the first well region 121 facing the semiconductor substrate layer 100.

[0079] The process of forming the first well region 121 and the second well region 122 in the drift layer 110 refers to the description of the aforementioned embodiment, and the process of forming the first doping region 140 in the drift layer 110 refers to the description of the aforementioned embodiment.

[0080] refer to Figure 8 , forming a second doping region 170, wherein the forming of the second doping region 170 includes: forming the second doping region 170 on a side of the second well region 122 facing the semiconductor substrate layer 100, and the second doping region 170 is spaced apart from the first JFET region.

[0081] The process of forming the second doping region 170 includes an ion implantation process with a mask.

[0082] refer to Fig. 9 , forming a source region 130; and forming an ohmic contact region 131.

[0083] Regarding the positions of the source region 130 and the ohmic contact region 131 , reference is made to the description of the previous embodiment.

[0084] refer to Fig.10 , forming a gate structure, the gate structure covers the JFET region, a portion of the surface of the first well region 121 and a portion of the surface of the second well region 122. The gate structure includes a gate dielectric layer 161 and a gate electrode layer 162. The gate structure also covers a portion of the source region 130.

[0085] Another embodiment of the present application also provides a method for preparing a MOSFET structure. The difference between the present application and the method for preparing the MOSFET structure of the aforementioned embodiment is that the method for preparing the MOSFET structure also includes: forming a second initial doping region in the drift layer; wherein forming the first well region and the first doping region includes: forming the first well region and the first doping region in part of the second initial doping region and in the drift layer on a side of the part of the second initial doping region away from the semiconductor substrate layer; wherein forming the second well region includes: forming a second well region in part of the second initial doping region and in the drift layer on a side of the part of the second initial doping region away from the semiconductor substrate layer; wherein the second initial doping region includes a portion of the second well region located on a side of the second well region facing the semiconductor substrate layer and a portion located between the second well region and the first doping region forming a second doping region.

[0086] Figures 11 to 13 A structural diagram of a MOSFET structure preparation process provided by another embodiment of the present invention

[0087] refer to Fig.11 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100 ; and a second initial doping region 170 a is formed in the drift layer 110 .

[0088] The conductivity type of the second preliminary doping region 170 a is opposite to the conductivity type of the drift layer 110 .

[0089] The process of forming the second initial doping region 170a includes a maskless ion implantation process. The surface of the second initial doping region 170a facing the semiconductor substrate layer 100 is spaced from the semiconductor substrate layer 100. The surface of the second initial doping region 170a facing away from the semiconductor substrate layer 100 is spaced from the surface of the drift layer 110 facing away from the semiconductor substrate layer 100.

[0090] refer to Fig.12 A first well region 121 and a first doped region 140 are formed in part of the second initial doped region 170 a and in part of the drift layer 110 on the side of the second initial doped region 170 a away from the semiconductor substrate layer 100 ; a second well region 122 is formed; and a JFET region is formed in the drift layer 110 .

[0091] Forming the second well region 122 includes: forming the second well region 122 in part of the second initial doping region 170a and in part of the drift layer 110 on the side of the second initial doping region 170a facing away from the semiconductor substrate layer 100; wherein the second initial doping region 170a, the part located on the side of the second well region 122 facing the semiconductor substrate layer 100, and the part located between the second well region 122 and the first doping region 140 form the second doping region 170.

[0092] Forming a JFET region in the drift layer 110 includes: forming a first doping region 140 in the drift layer 110; wherein the first doping region 140 is located on the sidewall of the first well region 121 facing the second well region 122 and is spaced from the second well region 122. The portion of the first doping region 140 located on the sidewall of the first well region 121 facing the second well region 122 constitutes a first JFET region 151, and the portion of the drift layer 110 located on the first JFET region 121 and the second well region 122 constitutes a second JFET region 152.

[0093] In this embodiment, the first doped region 140 is also located in the drift layer 110 on the side of the first well region 121 facing the semiconductor substrate layer 100. In other embodiments, the first doped region may not extend to the side of the first well region 121 facing the semiconductor substrate layer 100.

[0094] The second doping region 170 is located on the side of the second well region 122 facing the semiconductor substrate layer 100 and in contact with the second well region 122. The second doping region 170 is also located on the side of the second well region 122 facing the first well region 121. The second doping region 170 is also in contact with the first JFET region 151. The second JFET region 152 is located on the side of the second doping region 170 facing away from the semiconductor substrate layer 100. The doping concentration of the second doping region 170 is less than the doping concentration of the second well region 122.

[0095] refer to Fig.13 , forming a source region 130; and forming an ohmic contact region 131.

[0096] Regarding the positions of the source region 130 and the ohmic contact region 131 , reference is made to the description of the previous embodiment.

[0097] Continue to refer Fig.13 , forming a gate structure, the gate structure covers the JFET region, a portion of the surface of the first well region 121 and a portion of the surface of the second well region 122. The gate structure includes a gate dielectric layer 161 and a gate electrode layer 162. The gate structure also covers a portion of the source region 130.

[0098] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A MOSFET structure, characterized in that: include: Semiconductor substrate layer; A drift layer, located on one side of the semiconductor substrate layer; A first well region and a second well region are disposed in the drift layer at intervals; a JFET region in a drift layer between a first well region and a second well region, the JFET region comprising a first JFET region and a second JFET region, the first JFET region being between the first well region and the second JFET region, the second JFET region being between the second well region and the first JFET region, and the doping concentration of the first JFET region being greater than the doping concentration of the second JFET region; The gate structure covers the JFET region, a portion of the surface of the first well region, and a portion of the surface of the second well region.

2. The MOSFET structure according to claim 1, characterized in that: Also includes: A first doped region, located on a side wall of the first well region facing the second well region and spaced from the second well region; wherein a portion of the first doped region located on the side wall of the first well region facing the second well region constitutes the first JFET region, and a portion of the drift layer located in the first JFET region and the second well region constitutes the second JFET region; Preferably, the first doped region is also located in the drift layer on a side of the first well region facing the semiconductor substrate layer.

3. The MOSFET structure according to claim 1, characterized in that: In a direction from the first well region to the second well region, a ratio of a size of a surface of the first JFET region facing the gate structure to a size of a surface of the second JFET region facing the gate structure is 1:1-3:1; Preferably, in the direction from the first well region to the second well region, a size of the surface of the first JFET region facing the gate structure is 0.4 microns to 1.2 microns, and a size of the surface of the second JFET region facing the gate structure is 0.2 microns to 0.8 microns.

4. The MOSFET structure according to claim 1, characterized in that: Also includes: The second doped region is located on a side of the second well region facing the semiconductor substrate layer and contacts the second well region. The second doped region has the same conductivity type as the second well region, and the doping concentration of the second doped region is less than the doping concentration of the second well region.

5. The MOSFET structure according to claim 4, characterized in that: The second doping region is spaced apart from the first JFET region; Alternatively, the second doped region is also located on a side of the second well region facing the first well region, and the second doped region is also in contact with the first JFET region, wherein the second JFET region is located on a side of the second doped region away from the semiconductor substrate layer.

6. A method for preparing a MOSFET structure, characterized in that: include: forming a drift layer on one side of the semiconductor substrate layer; forming a first well region and a second well region in the drift layer; forming a JFET region in the drift layer, the JFET region comprising a first JFET region and a second JFET region, the first JFET region being located between the first well region and the second JFET region, the second JFET region being located between the second well region and the first JFET region, and the doping concentration of the first JFET region being greater than the doping concentration of the second JFET region; A gate structure is formed, where the gate structure covers the JFET region, a portion of the surface of the first well region, and a portion of the surface of the second well region.

7. The method for preparing a MOSFET structure according to claim 6, characterized in that: Forming a JFET region in the drift layer includes: forming a first doped region in the drift layer; Wherein, the first doped region is located on a side wall of the first well region facing the second well region and is spaced apart from the second well region; Wherein, a portion of the first doped region located on a side wall of the first well region facing the second well region constitutes the first JFET region, and a portion of the drift layer located in the first JFET region and the second well region constitutes the second JFET region; Preferably, the first doped region is also located in the drift layer on a side of the first well region facing the semiconductor substrate layer.

8. The method for preparing a MOSFET structure according to claim 7, characterized in that: Also includes: A second doped region is formed, wherein the second doped region is located on a side of the second well region facing the semiconductor substrate layer and contacts the second well region, the second doped region has the same conductivity type as the second well region, and the doping concentration of the second doped region is less than the doping concentration of the second well region.

9. The method for preparing a MOSFET structure according to claim 8, characterized in that: Forming the second doping region includes: forming the second doping region on a side of the second well region facing the semiconductor substrate layer, the second doping region being spaced apart from the first JFET region.

10. The method for preparing a MOSFET structure according to claim 8, characterized in that: Also includes: The second doped region is formed on a side of the second well region facing the semiconductor substrate layer, and the second doped region is in contact with the first JFET region; wherein the second JFET region is located on a side of the second doped region facing away from the semiconductor substrate layer; Preferably, the method further comprises: forming a second initial doping region in the drift layer; Wherein, forming the first well region and the first doped region comprises: forming the first well region and the first doped region in a part of the second initial doped region and in a part of the drift layer on a side of the second initial doped region away from the semiconductor substrate layer; Wherein, forming the second well region comprises: forming the second well region in a part of the second initial doping region and in a part of the drift layer on a side of the second initial doping region away from the semiconductor substrate layer; The second initial doping region includes a portion of the second well region that is located on a side of the second well region that faces the semiconductor substrate layer and a portion of the second initial doping region that is located between the second well region and the first doping region.

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