Super junction trench gate MOSFET structure and forming method thereof

Abstract

The invention provides a super-junction trench gate MOSFET structure and a forming method thereof, and the structure comprises a substrate, the surface of which is provided with a drift region and a body region located on the surface of the drift region; the groove penetrates through the body region and the bottom of the groove extends into the drift region; the doped column is located at the bottom of the groove and located in the drift region; the auxiliary doped column is located in a part of the groove, the top surface of the auxiliary doped column is lower than the bottom surface of the body region, and the bottom surface of the auxiliary doped column is in contact with the top surface of the doped column; the trench gate is positioned in the residual trench and is positioned above the auxiliary doped column; the breakdown voltage of the super-junction trench gate MOSFET is effectively improved, and the super-junction trench gate MOSFET has a wide application range.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a super junction trench gate MOSFET structure and a forming method thereof. Background Art

[0002] Trench gate MOSFET device is a common MOFET device variant, which includes a gate, source and drain. The flow of current is controlled by adjusting the gate voltage. The core principle is to use the gate electric field to control the electrons in the channel. When there is a positive voltage between the gate and the source, an electron gas is formed in the channel, allowing current to pass. When the gate voltage is zero or negative, the channel becomes an insulator and the current stops.

[0003] Trench gate MOSFET devices are widely used in power conversion circuits and are often used in power switching devices. In order to improve the on-resistance of medium and high voltage (50V~200V) trench gates, the concept of super junction-trench gate has been proposed. The on-resistance Rsp and breakdown voltage BV of trench gates are one of its important parameter indicators. Obtaining higher breakdown voltage and lower on-resistance can improve the competitiveness of products.

[0004] However, the performance of existing superjunction trench gate MOSFET devices is poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a super junction trench gate MOSFET structure and a method for forming the same, which effectively improves the breakdown voltage of the super junction trench gate MOSFET and has a wider range of applications.

[0006] To solve the above problems, the present invention provides a super junction trench gate MOSFET structure, comprising: a substrate, a surface of the substrate having a drift region and a body region located on the surface of the drift region; a trench penetrating the body region and extending at the bottom into the drift region; a doped column located at the bottom of the trench and in the drift region; an auxiliary doped column located in part of the trench, the top surface of the auxiliary doped column being lower than the bottom surface of the body region, the bottom surface of the auxiliary doped column being in contact with the top surface of the doped column; and a trench gate located in the remaining trench and above the auxiliary doped column.

[0007] Optionally, the doping column is doped with first doping ions, and the auxiliary doping column is doped with second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

[0008] Optionally, the trench gate includes a gate dielectric layer located on the top surface of the auxiliary doped column, the gate dielectric layer is also located on the sidewall surface of the trench above the auxiliary doped column; and a gate polysilicon layer is located on the gate dielectric layer, the gate polysilicon layer fills the trench.

[0009] Optionally, a dielectric layer is provided between the auxiliary doping column and the trench, and the gate dielectric layer is also located on the top surface of the dielectric layer.

[0010] Optionally, it also includes a source end heavily doped region in the body region on both sides of the trench gate, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is opposite to the type of the first doping ion.

[0011] Optionally, it also includes an interlayer dielectric layer located on the surface of the body region, a plug located in the interlayer dielectric layer, the bottom of the plug extends into the body region, and the plug penetrates the heavily doped source region on both sides of the trench gate.

[0012] Optionally, the method further includes: a heavily doped region located at the bottom of the plug, wherein the heavily doped region has fourth doping ions, and the type of the fourth doping ions is opposite to the type of the third doping ions.

[0013] Optionally, it further includes a source metal layer located on the top surface of the interlayer dielectric layer, and the source metal layer is also located on the top surface of the plug.

[0014] Optionally, it also includes a drain metal layer located on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

[0015] Correspondingly, the present invention also provides a method for forming a super junction trench gate MOSFET structure, comprising the steps of: providing a substrate, a drift region being formed on the surface of the substrate, and a body region being formed on the surface of the drift region; etching the body region and a portion of the drift region to form a groove penetrating the body region, wherein the bottom of the groove extends into the drift region; forming a doped column in the drift region at the bottom of the groove; forming an auxiliary doped column in a portion of the groove, wherein the top surface of the auxiliary doped column is lower than the bottom surface of the body region, and the bottom surface of the auxiliary doped column contacts the top surface of the doped column; and forming a trench gate in the remaining trench, wherein the trench gate is located above the auxiliary doped column.

[0016] Optionally, the doping column is doped with first doping ions, and the auxiliary doping column is doped with second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

[0017] Optionally, the method for forming a groove includes: forming an etch stop layer on the surface of the body region; forming a hard mask layer on the surface of the etch stop layer; forming a photoresist layer on the surface of the hard mask layer, wherein the photoresist layer has an opening exposing a portion of the surface of the hard mask layer; etching the hard mask layer using the photoresist layer as a mask to form a hard mask opening exposing a portion of the etch stop layer in the hard mask layer; removing the photoresist layer; and etching the etch stop layer, the body region, and a drift region of partial thickness using the hard mask layer as a mask to form a groove.

[0018] Optionally, the distance between the bottom of the trench and the bottom of the body region in a direction perpendicular to the substrate surface is greater than 1 um, and the distance between the bottom of the trench and the top of the substrate in a direction perpendicular to the substrate surface is greater than 5 um.

[0019] Optionally, the auxiliary doping column and the method for forming the doping column include: forming a sacrificial oxide layer on the side wall of the groove; using the hard mask layer as a mask, ion implanting into the drift region at the bottom of the groove to form a doping column, wherein the doping column has a first doping ion; removing the hard mask layer, the sacrificial oxide layer and the etch stop layer, and forming an initial dielectric layer on the side wall surface of the groove, the bottom surface of the groove and the surface of the body region; etching the initial dielectric layer until the top surface of the doping column is exposed to form an intermediate dielectric layer; filling the groove with the initial auxiliary doping column layer, and the initial auxiliary doping column layer also extends to the surface of the body region; ion doping the initial auxiliary doping layer to form an auxiliary doping column layer; etching back the auxiliary doping column layer and the intermediate interlayer dielectric layer until the top surface of the auxiliary doping column layer and the top surface of the intermediate interlayer dielectric layer are lower than the bottom surface of the body region, forming a dielectric layer on the side wall of part of the groove, and forming an auxiliary doping column between the dielectric layers, wherein the auxiliary doping column has a second doping ion.

[0020] Optionally, the method for forming a trench gate includes: after forming an auxiliary doping column, forming a gate dielectric layer on the sidewalls of the remaining trench, the surface of the auxiliary doping column and the surface of the dielectric layer; forming a gate polysilicon layer on the gate dielectric layer, and the gate polysilicon layer fills the trench.

[0021] Optionally, after forming the trench gate, the method further includes: performing ion implantation on the body region on both sides of the trench gate to form a source end heavily doped region, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is opposite to the type of the first doping ion; forming an interlayer dielectric layer on the surface of the body region; forming a plug in the interlayer dielectric layer, wherein the bottom of the plug extends into the body region, and the plug is located between the source end heavily doped regions on one side of an adjacent trench gate; forming a heavily doped region at the bottom of the plug, wherein the heavily doped region has a fourth doping ion, and the type of the fourth doping ion is opposite to the type of the third doping ion; forming a source end metal layer on the top surface of the interlayer dielectric layer, wherein the source end metal layer is formed on the top surface of the plug; forming a drain end metal layer on the surface of the substrate, wherein the drain end metal layer and the drift region are respectively located on both sides of the substrate.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the super junction trench gate MOSFET structure of the present invention, the doped column is located in the drift region, the trench penetrates the body region and the bottom extends to the drift region, the bottom of the trench exposes the top surface of the doped column, the auxiliary doped column is located in the trench and the top surface of the auxiliary doped column is lower than the bottom surface of the body region, the bottom surface of the auxiliary doped column is in contact with the top of the doped column, the trench gate is located in the trench and above the auxiliary doped column, and the top surface of the trench gate is flush with the top surface of the body region; the doped column is used to assist in the depletion of the drift region, and the auxiliary doped column can also be used to assist in the depletion of the drift region, thereby increasing the length of the depletion of the drift region and improving the breakdown voltage of the device, and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a superjunction trench gate MOSFET structure in one embodiment;

[0025] Figures 2 to 12 It is a structural schematic diagram of a formation process of a super junction trench gate MOSFET structure according to an embodiment of the present invention;

[0026] Fig.13 Schematic diagram of the id-vd relationship curve of the super junction trench gate MOSFET in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The electrical performance of the super junction trench gate MOSFET structure in the prior art still needs to be improved.

[0028] Figure 1 It is a schematic structural diagram of a super junction trench gate MOSFET structure in one embodiment.

[0029] Please refer to Figure 1 The super junction trench gate MOSFET includes: a substrate 1, an epitaxial layer 2, a doped column 3, a gate dielectric layer 4, a trench gate 5, a body region 6, a first heavily doped region 8, an interlayer insulating dielectric layer 10, a second heavily doped region 7, a conductive plug 9, a source metal layer 11 and a drain metal layer 12, wherein the epitaxial layer 2 covers the front surface of the substrate 1; the doped column 3 is located in the epitaxial layer 2; an array of trenches is formed in the epitaxial layer 2 between the doped columns 3, the gate dielectric layer 4 covers the bottom wall and side wall of the trench, and the trench gate 5 covers the gate The dielectric layer 4 and the remaining space filling the trench; the body region 6 is located in the epitaxial layer 2 between the trench gates 5; the first heavily doped region 8 is located in the body region 6; the interlayer insulating dielectric layer 10 covers the first heavily doped region 8 and the trench gate 5; the conductive plug 9 is located in the interlayer insulating dielectric layer 10, the first heavily doped region 8 and a partial thickness of the body region 6; the second heavily doped region 7 is located at the bottom of the conductive plug 9; the source metal layer 11 covers the interlayer insulating dielectric layer 10 and the conductive plug 9; the drain metal layer 12 covers the back side of the substrate 1.

[0030] The inventors found that in the above embodiment, the doped column 3 is formed by ion implantation. Since the ion implantation energy is limited, the process is restricted when the ion implantation energy is greater than 3500Kev, especially for the requirement of BV>80V (the thickness of the epitaxial layer 2 is greater than 5um). The ion implantation energy is greater than 2500Kev, which makes the bottom of the doped column 3 as close to the highly doped substrate 1 as possible. However, the high-energy ion implantation brings great difficulties to the process integration.

[0031] The inventors have found through research that the doped column is located in the drift region, the groove passes through the body region and the bottom extends to the drift region, the bottom of the groove exposes the top surface of the doped column, the auxiliary doped column is located in the groove and the top surface of the auxiliary doped column is lower than the bottom surface of the body region, the bottom surface of the auxiliary doped column is in contact with the top of the doped column, and the trench gate is located in the groove and above the auxiliary doped column; the doped column is used to assist in the depletion of the drift region, and the auxiliary doped column can also be used to assist in the depletion of the drift region, thereby increasing the length of the depletion of the drift region, which can improve the breakdown voltage of the device and reduce the difficulty of process integration, and has a wider range of applications.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] First, please refer to Figure 2 , a substrate 101 is provided, a drift region 102 is formed on the surface of the substrate 101 , and a body region 106 is formed on the surface of the drift region 102 .

[0034] In this embodiment, taking an N-type channel SJ-TGMOSFET as an example, the substrate 101 is a highly doped N-type substrate.

[0035] It should be noted that all subsequent doping ion types are described using an N-type channel as an example; if the channel type changes, all doping ion types will be changed accordingly according to actual application needs.

[0036] In some embodiments, the substrate 101 may also be a highly doped P-type substrate.

[0037] In this embodiment, the material of the substrate is silicon.

[0038] In some embodiments, the substrate may be made of other semiconductor materials such as silicon germanium.

[0039] In this embodiment, epitaxial growth is performed on the substrate 101 to form an epitaxial layer, and the epitaxial layer is in-situ doped to form a drift region 102. The drift region 102 is N-type. Specifically, the epitaxial layer is doped with N-type ions with a concentration of 5e15-1e17cm -2 .

[0040] In this embodiment, the process parameters of epitaxial growth include the gases used, including hydrogen, HCl gas, SiH2Cl2, PH3 and CH3SiH3 gas, the flow rate of hydrogen is 2000sccm~20000sccm, the flow rate of HCl gas is 30sccm~150sccm, the flow rate of SiH2Cl2 is 50sccm~1000sccm, the flow rate of PH3 is 10sccm~2000sccm, the flow rate of CH3SiH3 is 50sccm~5000sccm, the chamber pressure is 10torr~600torr, and the temperature is 650 degrees Celsius~850 degrees Celsius.

[0041] After the drift region 102 is formed, P-type ions are implanted into the surface of the drift region 102 to form a body region 106 .

[0042] In this embodiment, after the body region 106 is formed, a thermal drive process is performed to perform thermal diffusion drive, and the thermal diffusion drive process of the body region 106 is placed before the subsequently formed trench gate structure and doped columns to prevent excessive lateral diffusion of the doped columns under the thermal drive process of the body region 106.

[0043] The body region 106 and part of the drift region 102 are etched to form a trench penetrating the body region 106 , wherein the bottom of the trench extends into the drift region 102 . Figure 3 to Figure 4 .

[0044] Please refer to Figure 3 , an etch stop layer 201 is formed on the surface of the body region 106; a hard mask layer 502 is formed on the surface of the etch stop layer 201; a photoresist layer 501 is formed on the surface of the hard mask layer 502, and the photoresist layer 501 has an opening that exposes a portion of the surface of the hard mask layer 502; using the photoresist layer 501 as a mask, the hard mask layer 502 is etched to form a hard mask opening that exposes a portion of the etch stop layer 201 in the hard mask layer 502.

[0045] In this embodiment, the material of the etch stop layer 201 is a silicon nitride layer.

[0046] In some embodiments, the material of the etch stop layer 201 may also be silicon carbonitride, silicon carbide, etc.

[0047] In this embodiment, the material of the hard mask layer 502 is silicon oxide.

[0048] In some embodiments, the material of the hard mask layer 502 may also be silicon oxynitride, silicon oxycarbide, etc.

[0049] Please refer to Figure 4, remove the photoresist layer 501 ; and etch the etch stop layer 201 , the body region 106 and a portion of the thickness of the drift region 102 using the hard mask layer 502 as a mask to form a trench 113 .

[0050] In this embodiment, the depth of the trench 113 is greater than 3 um.

[0051] In this embodiment, the distance d1 between the bottom of the groove 113 and the bottom of the body region 106 in the direction perpendicular to the surface of the substrate 101 is greater than 1um, and the distance d2 between the bottom of the groove 113 and the top of the substrate 101 in the direction perpendicular to the surface of the substrate 101 is greater than 5um.

[0052] In this embodiment, the method for forming the groove 113 is a dry etching process, and the specific parameters include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20sccm~200sccm, the flow rate of CH3F is 20sccm~50sccm, the source RF power is 200W~500W, and the chamber pressure is 1torr~10torr.

[0053] A doped column is formed in the drift region 102 at the bottom of the trench 113, and an auxiliary doped column is formed in a portion of the trench 113. The top surface of the auxiliary doped column is lower than the bottom surface of the body region 106. For the process of the bottom surface of the auxiliary doped column contacting the top surface of the doped column, please refer to Figures 5 to 10 .

[0054] Please refer to Figure 5 , a sacrificial oxide layer 202 is formed on the sidewall of the trench 113 .

[0055] In this embodiment, the substrate with the hard mask layer 502 is placed in a furnace tube to grow a sacrificial oxide layer 202, and defects formed by etching the trench 113 are repaired by a thermal oxidation process, which helps to improve the quality of subsequently formed devices.

[0056] Please refer to Figure 6 , using the hard mask layer 502 as a mask, ion implantation is performed into the drift region 102 at the bottom of the trench 113 to form a doped column 103 , wherein the doped column 103 has first doped ions.

[0057] In this embodiment, the sacrificial oxide layer 202 is used as an implantation liner layer, and implantation is performed using the hard mask layer 502 as a mask to form the doped pillars 103 .

[0058] In this embodiment, the doping column 103 is located in the drift region 102 directly below the trench 113. The injection energy for forming the doping column 103 is 50Kev to 4000Kev, and the injection angle is greater than or equal to 0° and less than 7°. The doping column 103 has a first doping ion, and the first doping ion is P-type, such as B, and the concentration is 1e12-1e13cm-2 .

[0059] Please refer to Figure 7 , remove the hard mask layer 502 , the sacrificial oxide layer 202 and the etch stop layer 201 , and form an initial dielectric layer 203 on the sidewall surface of the trench 113 , the bottom surface of the trench 113 and the surface of the body region 106 .

[0060] In this embodiment, the initial dielectric layer 203 is an insulating dielectric layer such as silicon nitride.

[0061] In this embodiment, the hard mask layer 502 and the sacrificial oxide layer 202 share the same wet etching removal process, which can further save manufacturing costs.

[0062] Please refer to Figure 8 , the initial dielectric layer 203 is etched until the top surface of the doped column 103 is exposed, thereby forming an intermediate dielectric layer 203 ′.

[0063] In this embodiment, the initial dielectric layer 203 is etched to expose the doped column 103 at the bottom of the trench 113 , so as to form a short circuit between the subsequent auxiliary doped column and the doped column 103 .

[0064] Please refer to Fig. 9 , the trench 113 is filled with an initial auxiliary doping column layer, and the initial auxiliary doping column layer also extends to the surface of the body region 106; the initial auxiliary doping layer is ion doped to form an auxiliary doping column layer 205'.

[0065] In this embodiment, the material of the auxiliary doped column layer 205 ′ is polysilicon.

[0066] Please refer to Fig.10 , the auxiliary doped column layer 205' and the intermediate interlayer dielectric layer 203' are etched back until the top surface of the auxiliary doped column layer 205' and the top surface of the intermediate interlayer dielectric layer 203' are lower than the bottom surface of the body region 106, a dielectric layer 204 is formed on the sidewall of part of the trench 113, and an auxiliary doped column 205 is formed between the dielectric layers 204, and the auxiliary doped column 205 has second doping ions, and the type of the second doping ions is the same as the type of the first doping ions.

[0067] In this embodiment, the ions doped in the auxiliary doping column 205 may be B.

[0068] In this embodiment, the doping column 103 is used to assist in the depletion of the drift region 102, and the auxiliary doping column 205 can also be used to assist in the depletion of the drift region 102, thereby increasing the depletion length of the drift region 102, which can improve the breakdown voltage of the device and reduce the difficulty of process integration, and has a wider range of applications.

[0069] A trench gate is formed in the remaining trench 113, and the trench gate is located above the auxiliary doping column 205. Please refer to the process Fig.11 .

[0070] Please refer to Fig.11 After the auxiliary doping column 205 is formed, a gate dielectric layer 104 is formed on the sidewalls of the remaining trench 113, the surface of the auxiliary doping column 205 and the surface of the dielectric layer; a gate polysilicon layer 105 is formed on the gate dielectric layer 104, and the gate polysilicon layer 105 fills the trench 113.

[0071] In this embodiment, a first gate silicon oxide layer (not shown in the figure) of 100 to 400 angstroms is grown by a low-temperature thermal oxidation growth process, the oxidation temperature is 800 to 930°C, and the time is less than 30 minutes; then a TEOS silicon oxide layer is deposited as a second gate oxide layer and rapid annealing is performed to densify the TEOS, a gate polysilicon layer 105 is deposited, and chemical mechanical polishing is performed to form a gate structure.

[0072] In this embodiment, the gate dielectric layer 104 is grown in a low-temperature oxidation and deposition manner, which reduces the heat process introduced by thermal growth and allows the doped pillars 103 to diffuse laterally.

[0073] In this embodiment, the gate polysilicon layer 105 is N-type heavily doped polysilicon.

[0074] Please refer to Fig.12 After forming the trench gate, the method further includes: performing ion implantation on the body region 106 on both sides of the trench gate to form a source end heavily doped region 108, wherein the source end heavily doped region 108 has a third doping ion, and the type of the third doping ion is opposite to the type of the first doping ion; forming an interlayer dielectric layer 110 on the surface of the body region 106; forming a plug 109 in the interlayer dielectric layer 110, wherein the bottom of the plug 109 extends into the body region 106, and the plug 109 penetrates the source end heavily doped region 108 on both sides of the trench gate; forming a heavily doped region 107 at the bottom of the plug 109, wherein the heavily doped region 107 has a fourth doping ion, and the type of the fourth doping ion is opposite to the type of the third doping ion; forming a source end metal layer 111 on the top surface of the interlayer dielectric layer 110, wherein the source end metal layer 111 is formed on the top surface of the plug 109; forming a drain end metal layer 112 on the surface of the substrate 101, wherein the drain end metal layer 112 and the drift region 102 are respectively located on both sides of the substrate 101.

[0075] In this embodiment, the fourth doping ion is of P type, and the third doping ion is of N type.

[0076] Correspondingly, the present invention also provides a super junction trench gate MOSFET structure, including a substrate 101, wherein the surface of the substrate 101 has a drift region 102 and a body region 106 located on the surface of the drift region 102; a trench 113 that penetrates the body region 106 and extends at the bottom into the drift region 102; a doped column 103 located at the bottom of the trench 113 and located in the drift region 102; an auxiliary doped column 205 located in a portion of the trench 113, wherein the top surface of the auxiliary doped column 205 is lower than the bottom surface of the body region 106, and the bottom surface of the auxiliary doped column 205 is in contact with the top surface of the doped column 103; and a trench gate located in the remaining trench 113 and above the auxiliary doped column 205.

[0077] In this embodiment, the doping column 103 is used to assist in the depletion of the drift region 102, and the auxiliary doping column 205 can also be used to assist in the depletion of the drift region 102, thereby increasing the depletion length of the drift region 102, which can improve the breakdown voltage of the device and reduce the difficulty of process integration, and has a wider range of applications.

[0078] In this embodiment, the simulation shows that the super junction trench gate MOSFET structure has a withstand voltage of up to 210V when the total trench depth is 5.5um (e.g. Fig.13 shown).

[0079] In this embodiment, the doping column 103 is doped with first doping ions, and the auxiliary doping column 205 is doped with second doping ions. The type of the first doping ions is the same as the type of the second doping ions.

[0080] In this embodiment, the trench gate includes a gate dielectric layer 104 located on the top surface of the auxiliary doped column 205, and the gate dielectric layer 104 is also located on the sidewall surface of the trench 113 above the auxiliary doped column 205; and a gate polysilicon layer 105 is located on the gate dielectric layer 104, and the gate polysilicon layer 105 fills the trench 113.

[0081] In this embodiment, a dielectric layer 204 is further provided between the auxiliary doping column 205 and the trench 113 , and the gate dielectric layer 104 is further located on the top surface of the dielectric layer 204 .

[0082] In this embodiment, a source end heavily doped region 108 is further included in the body region 106 on both sides of the trench gate. The source end heavily doped region 108 has third doping ions, and the type of the third doping ions is opposite to the type of the first doping ions.

[0083] In this embodiment, it also includes an interlayer dielectric layer 110 located on the surface of the body region 106, and a plug 109 located in the interlayer dielectric layer 110. The bottom of the plug 109 extends into the body region 106, and the plug 109 penetrates the source end heavily doped region 108 on both sides of the trench gate.

[0084] In this embodiment, it also includes: a heavily doped region 107 located at the bottom of the plug 109, and the heavily doped region 107 has fourth doping ions. The type of the fourth doping ions is opposite to the type of the third doping ions. In this embodiment, the fourth doping ions are P-type and the third doping ions are N-type.

[0085] In this embodiment, a source metal layer 111 is further included and is located on the top surface of the interlayer dielectric layer 110 . The source metal layer 111 is also located on the top surface of the plug 109 .

[0086] In this embodiment, a drain metal layer 112 is further included on the surface of the substrate 101 . The drain metal layer 112 and the drift region 102 are respectively located on two sides of the substrate 101 .

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A super junction trench gate MOSFET structure, characterized in that: include: A substrate, wherein a surface of the substrate has a drift region and a body region located on the surface of the drift region; A trench penetrating the body region and extending at its bottom into the drift region; a doped column at the bottom of the trench and within the drift region; An auxiliary doping column located in a portion of the trench, wherein a top surface of the auxiliary doping column is lower than a bottom surface of the body region, and a bottom surface of the auxiliary doping column contacts a top surface of the doping column; A trench gate is located in the remaining trench and above the auxiliary doped column.

2. The super junction trench gate MOSFET structure according to claim 1, characterized in that: The doping column is doped with first doping ions, and the auxiliary doping column is doped with second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

3. The super junction trench gate MOSFET structure according to claim 1, characterized in that: The trench gate includes a gate dielectric layer located on the top surface of the auxiliary doped column, the gate dielectric layer is also located on the sidewall surface of the trench above the auxiliary doped column; and a gate polysilicon layer is located on the gate dielectric layer, the gate polysilicon layer fills the trench.

4. The super junction trench gate MOSFET structure according to claim 3, characterized in that: A dielectric layer is also provided between the auxiliary doping column and the trench, and the gate dielectric layer is also located on the top surface of the dielectric layer.

5. The super junction trench gate MOSFET structure according to claim 2, characterized in that: It also includes a source end heavily doped region in the body region on both sides of the trench gate, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is opposite to the type of the first doping ion.

6. The super junction trench gate MOSFET structure according to claim 5, characterized in that: It also includes an interlayer dielectric layer located on the surface of the body region, a plug located in the interlayer dielectric layer, the bottom of the plug extends into the body region, and the plug penetrates the heavily doped source region on both sides of the trench gate.

7. The super junction trench gate MOSFET structure according to claim 6, characterized in that: Also includes: A heavily doped region is located at the bottom of the plug, wherein fourth doping ions are present in the heavily doped region, and a type of the fourth doping ions is opposite to a type of the third doping ions.

8. The super junction trench gate MOSFET structure according to claim 7, characterized in that: It also includes a source metal layer located on the top surface of the interlayer dielectric layer, and the source metal layer is also located on the top surface of the plug.

9. The super junction trench gate MOSFET structure according to claim 1, characterized in that: It also includes a drain metal layer located on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

10. A method for forming a super junction trench gate MOSFET structure, characterized in that: Includes steps: Providing a substrate, wherein a drift region is formed on a surface of the substrate, and a body region is formed on a surface of the drift region; Etching the body region and a portion of the drift region to form a trench penetrating the body region, wherein the bottom of the trench extends into the drift region; forming a doped column in the drift region at the bottom of the trench; forming an auxiliary doping column in a portion of the trench, wherein a top surface of the auxiliary doping column is lower than a bottom surface of the body region, and a bottom surface of the auxiliary doping column contacts a top surface of the doping column; A trench gate is formed in the remaining trench, wherein the trench gate is located above the auxiliary doped column.

11. The method for forming a super junction trench gate MOSFET structure according to claim 10, wherein: The doping column is doped with first doping ions, and the auxiliary doping column is doped with second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

12. The method for forming a super junction trench gate MOSFET structure according to claim 10, wherein: The method for forming the groove comprises: forming an etch stop layer on a surface of the body region; forming a hard mask layer on a surface of the etch stop layer; forming a photoresist layer on the surface of the hard mask layer, wherein the photoresist layer has an opening exposing a portion of the surface of the hard mask layer; Using the photoresist layer as a mask, etching the hard mask layer to form a hard mask opening in the hard mask layer that exposes a portion of the etch stop layer; removing the photoresist layer; The etch stop layer, the body region, and a partial thickness of the drift region are etched using the hard mask layer as a mask to form the trench.

13. The method for forming a super junction trench gate MOSFET structure according to claim 10 or 12, characterized in that: The distance between the bottom of the trench and the bottom of the body region in a direction perpendicular to the substrate surface is greater than 1 um, and the distance between the bottom of the trench and the top of the substrate in a direction perpendicular to the substrate surface is greater than 5 um.

14. The method for forming a super junction trench gate MOSFET structure according to claim 12, wherein: The method for forming the auxiliary doping column and the doping column includes: forming a sacrificial oxide layer on the sidewalls of the trench; Using the hard mask layer as a mask, ion implantation is performed on the drift region at the bottom of the trench to form the doped column, wherein the doped column has first doped ions; removing the hard mask layer, the sacrificial oxide layer and the etch stop layer, and forming an initial dielectric layer on the sidewall surface of the trench, the bottom surface of the trench and the surface of the body region; Etching the initial dielectric layer until the top surface of the doped column is exposed to form an intermediate dielectric layer; Filling the trench with an initial auxiliary doped column layer, wherein the initial auxiliary doped column layer also extends to the surface of the body region; Performing ion doping on the initial auxiliary doping layer to form an auxiliary doping column layer; The auxiliary doped column layer and the intermediate interlayer dielectric layer are etched back until the top surface of the auxiliary doped column layer and the top surface of the intermediate interlayer dielectric layer are lower than the bottom surface of the body region, a dielectric layer is formed on the sidewall of part of the groove, and auxiliary doped columns are formed between the dielectric layers, wherein the auxiliary doped columns have second doping ions.

15. The method for forming a super junction trench gate MOSFET structure according to claim 14, characterized in that: The method for forming the trench gate includes: After forming the auxiliary doping column, forming a gate dielectric layer on the remaining sidewalls of the trench, the surface of the auxiliary doping column and the surface of the dielectric layer; A gate polysilicon layer is formed on the gate dielectric layer, and the gate polysilicon layer fully fills the trench.

16. The method for forming a super junction trench gate MOSFET structure according to claim 15, characterized in that: After forming the trench gate, the method further includes: Performing ion implantation on the body region at both sides of the trench gate to form a source end heavily doped region, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is opposite to the type of the first doping ion; forming an interlayer dielectric layer on the surface of the body region; forming a plug in the interlayer dielectric layer, wherein the bottom of the plug extends into the body region, and the plug is located between the heavily doped source regions adjacent to one side of the trench gate; forming a heavily doped region at the bottom of the plug, wherein the heavily doped region has fourth doping ions, and the type of the fourth doping ions is opposite to the type of the third doping ions; forming a source metal layer on the top surface of the interlayer dielectric layer, wherein the source metal layer is formed on the top surface of the plug; A drain metal layer is formed on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

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