MOSFET transistor with improved body structure and related manufacturing process

Abstract

The invention relates to a MOSFET transistor with an improved body structure and a related manufacturing process. A MOSFET transistor has a semiconductor body comprising a drain region of a first conductivity type delimited by a front surface and at least one cell comprising: a pair of gate structures laterally offset parallel to a first axis, each gate structure includes a respective gate dielectric region disposed on the front surface and a respective gate conductive region disposed on the respective gate dielectric region; a body structure of a second conductivity type including a body region extending inside the drain region starting from the front surface and contacting a portion of the gate dielectric region, and a reinforcement region extending below the body region; and a pair of source regions of the first conductivity type extending inside the body region starting from the front surface. The body structure includes an enrichment region that extends inside the body region below the source regions and projects laterally parallel to the first axis in both directions with respect to the paired source regions.

Description

Technical Field

[0001] The present disclosure relates to MOSFET transistors having an improved body structure to increase robustness and related fabrication processes. Background Art

[0002] As is known, there are MOSFET transistors that are designed to withstand particularly high voltages; in use, these MOSFET transistors may find themselves operating for a short period of time in breakdown conditions. For example, when the MOSFET transistor has an inductive load, the MOSFET transistor may have to withstand a drain-source voltage that is higher than the breakdown voltage, in which case a high reverse current flows through the drain-source diode present in the MOSFET transistor. Due to this reverse current, the parasitic bipolar transistor formed by the body region, the source region and the drain region of the MOSFET transistor can be turned on, in which case a further increase in the current flowing through the MOSFET transistor may occur, leading to subsequent damage to the MOSFET transistor. These operating situations are accurately reproduced during the so-called "unclamped inductive switching" (UIS) test, which is intended to verify the actual robustness of the MOSFET transistor.

[0003] The present disclosure provides a MOSFET transistor that can withstand a high reverse current without causing a corresponding parasitic bipolar transistor to turn on. Summary of the invention

[0004] According to the present disclosure, there is provided a MOSFET transistor and a process for manufacturing the same, as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a better understanding of the present disclosure, embodiments of the present disclosure will now be described by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0006] Figure 1 schematically shows a cross section of a portion of a MOSFET transistor; and

[0007] Figures 2 to 9 Schematically shows the process during successive steps of the manufacturing process Figure 1 Cross section of a MOSFET transistor shown in . DETAILED DESCRIPTION

[0008] Figure 1 An orthogonal reference frame XYZ and a MOSFET transistor 1 are shown, the transistor 1 comprising a semiconductor body 4 (eg formed of silicon and comprising a substrate 6 and a drain region 8).

[0009] For example, the substrate 6 has N++ type doping (for example, including 1*1018 cm -3 With 9*10 20 cm -3 and at the bottom by the bottom surface S bot The bottom surface is substantially parallel to the XY plane. The drain region 8 has, for example, an N-type doping (for example, including 1*10 14 cm -3 With 1*10 17 cm -3 The drain region 8 is formed by the top surface S at the top. top By definition, the top surface is substantially parallel to the XY plane.

[0010] Furthermore, the MOSFET transistor 1 comprises a plurality of gate structures 10 ( Figure 1 Two) and multiple main structures 20 ( Figure 1 One can be seen in ).

[0011] The gate structures 10 are substantially equal to each other and have a top surface S top The gate structure 10 extends upward and has an elongated shape parallel to the Y-axis; in addition, the gate structure 10 is arranged to be laterally offset and parallel to the X-axis.

[0012] The main structures 20 are substantially equal to each other, and are top The main structure 20 starts to extend inside the drain region 8 and has an elongated shape parallel to the Y axis; in addition, the main structure 20 is arranged in a lateral offset parallel to the X axis in an alternating manner relative to the gate structure 10. In other words, parallel to the X axis, each main structure 20 extends between two corresponding gate structures 10, such as Figure 1 as shown in .

[0013] In practice, each main structure 20 forms a cell 2 of a MOSFET transistor 1 together with a corresponding pair of gate structures 10. Therefore, the MOSFET transistor 1 is composed of a plurality of cells 2 ( Figure 1 The cells 2 are formed by approximately equalizing each other (only one of which is visible) and are arranged parallel to the X-axis so that adjacent cells share the same gate structure 10.

[0014] In more detail, each gate structure 10 includes a corresponding gate dielectric region 12 , a corresponding gate conductive region 14 , and a corresponding gate insulating region 16 , as described below with reference to a single gate structure 10 .

[0015] In particular, the gate dielectric region 12 is formed on the top surface S top The gate dielectric region 12 extends above the semiconductor body 4, contacts the semiconductor body 4, and is formed of a dielectric material such as, for example, an oxide (eg, thermal oxide). In addition, the gate dielectric region 12 has an approximately planar shape, extending parallel to the Y-axis.

[0016] The gate conductive region 14 extends over and directly contacts the gate dielectric region 12 and is formed of, for example, polysilicon. The gate conductive region 14 also has a substantially planar shape and is elongated parallel to the Y-axis.

[0017] The gate insulating region 16 is formed of a dielectric material such as, for example, an oxide (e.g., silicon oxide or TEOS), and extends so as to surround the gate dielectric region 12 and the gate conductive region 14 at the top and laterally. In particular, a central portion of the gate insulating region 16 extends over the gate conductive region 14, in direct contact; furthermore, two lateral portions of the gate insulating region 16 extend on opposite sides of the gate dielectric region 12 and the gate conductive region 14, so as to laterally cover the gate dielectric region 12 and the gate conductive region 14, in direct contact, until contacting the semiconductor body 4 at the bottom.

[0018] Although not shown, the gate conductive regions 14 are arranged in electrical contact with each other in a manner known per se so as to form a gate terminal of the MOSFET transistor 1. In order to allow the gate terminal to be electrically coupled to the outside world, the MOSFET transistor 1 may, for example, include a gate metallization (not shown) extending through a portion of at least one gate insulating region 16 so as to electrically contact the corresponding gate conductive region 14. However, these details are not relevant for the operation of the MOSFET transistor 1.

[0019] The MOSFET transistor 1 further includes a drain metallization 37 extending below the substrate 6 in direct contact, and a source metallization 17 extending above the gate insulating region 16 in direct contact and extending between the gate insulating regions 16 to contact the exposed top surface S of the gate structure 10. top part.

[0020] Referring again to the main structure 20, it includes a main region 22 and a reinforcement region 24, which will be described in more detail below; for this purpose, a symmetry plane H parallel to the YZ plane is introduced, and the two gate structures 10 corresponding to the main structure 20 are arranged symmetrically with respect to the symmetry plane H. In addition, without loss of generality, as a first approximation, the main structure 20 has a cross section parallel to the XZ plane, which is invariant to the translation along the Y axis.

[0021] In detail, both the main region 22 and the reinforcement region 24 have an elongated shape parallel to the Y axis and are substantially symmetrical with respect to the symmetry plane H. In addition, the main region 22 and the reinforcement region 24 have a P-type doping (for example, including 1*10 14 cm -3 With 1*10 16 cm -3 between).

[0022] In more detail, the reinforcement region 24 is arranged below the main body region 22 and has an approximately parallelepiped shape with its axis parallel to the Y-axis.

[0023] Regarding the main body region 22, it has a circular shape in cross section. In particular, the main body region 22 includes: a central portion 25, which faces the top surface S at the top. top and contacts the reinforcement zone 24 at the bottom; and a pair of peripheral portions 26', 26" extending on opposite sides relative to the central portion 25 in an approximately symmetrical manner relative to the plane of symmetry. The peripheral portions 26', 26" protrude laterally relative to the reinforcement zone 24 of the underlying layer.

[0024] In more detail, each peripheral portion 26 ′, 26 ″ faces the top surface S at the top. top And has a convex profile defining a corresponding recess arranged facing the central portion 25 .

[0025] In more detail, denoted by w(z) as a function of the value of the width w (parallel to the X-axis) of the body region 22 as a function of the z-coordinate taken along the Z-axis, the following occurs.

[0026] On the top surface S top At , the function w(z) is initially equal to the value W top ; Subsequently, as the value of the z coordinate decreases, and therefore as the depth inside the semiconductor body 4 increases, the value of the function w(z) increases until a maximum value W is reached at a depth greater than the maximum depth reached by the first source region 30 ′ and the second source region 30 ″ max ; Then, as the value of the z coordinate decreases, the value of the function w(z) decreases until it reaches a value W at the plane where the main body region 22 and the reinforcement region 24 contact. init (which represents the width of the reinforcement zone 24). W init <W top <W max .

[0027] In other words, the body region 22 has a width that follows a non-monotonic trend with increasing depth within the semiconductor body 4, the width increasing in width relative to the top surface S top The maximum value is exhibited at an intermediate depth of the reinforced zone 24 .

[0028] Each main structure 20 also includes a corresponding enriched region 23, which has a P+ type doping. In addition, for each main structure 20, the MOSFET transistor 1 includes a pair of corresponding source regions ( Figure 1 The corresponding source regions in a pair have N+ type doping and are referred to hereinafter as first source region 30 ′ and second source region 30 ″, respectively.

[0029] In detail, the first source region 30 ′ and the second source region 30 ″ have an elongated shape parallel to the Y axis and extend from the top surface S top It begins to extend inside the body region 22 so as to be arranged at a distance parallel to the X-axis in a manner that is approximately symmetrical relative to the symmetry plane H. Without loss of generality, each of the first source region 30′ and the second source region 30″ extends partially inside the central portion 25 of the body region 22, and partially extends inside the corresponding peripheral portions of the pair of peripheral portions 26′, 26″.

[0030] In more detail, each of the first source region 30′ and the second source region 30″ extends partially under the corresponding gate structure 10. In particular, each of the first source region 30′ and the second source region 30″ includes: a corresponding outer portion, which extends under, in direct contact with, a portion of the gate dielectric region 12 of the corresponding gate structure 10; a middle portion, which extends under, in direct contact with, a lateral portion of the corresponding gate insulation region 16; and an inner portion, which extends under, in direct contact with, a corresponding portion of the source metallization 17. In addition, the first source region 30′ and the second source region 30″ are laterally separated by a portion of the central portion 25 of the main region 22.

[0031] The enriched region 23 is located inside the main region 22 and is adjacent to the top surface S top A certain distance from the strengthening region 24 and extending below the first source region 30' and the second source region 30"; without loss of generality, Figure 1 In the example shown in , the enriched region 23 does not contact the first source region 30 ′ and the second source region 30 ″, although embodiments (not shown) are also possible in which the enriched region 23 contacts the first source region 30 ′ and the second source region 30 ″.

[0032] In more detail, the enriched region 23 has an approximately elliptical shape in cross section, is symmetrical relative to the symmetry plane H, and partially occupies the central portion 25 and the peripheral portions 26′, 26″ of the main region 22 without contacting the drain region 8; in particular, the enriched region 23 is laterally surrounded by the main region 22 at the top and at the bottom.

[0033] In more detail, parallel to the X-axis, the enriched region 23 protrudes laterally relative to the first source region 30 ′ and the second source region 30 ″; in particular, with reference to Figure 1 As already shown in , the enriched region 23 protrudes to the left relative to the first source region 30′ and to the right relative to the second source region 30″. Therefore, what happens is that, parallel to the X-axis, the enriched region 23 protrudes laterally in two directions relative to the pair formed by the first source region 30′ and the second source region 30″. In addition, parallel to the X-axis, the enriched region 23 also protrudes laterally in two directions relative to the underlying reinforcement region 24.

[0034] In use, when the gate terminal of the MOSFET transistor 1 is biased above the threshold voltage, in each cell 2, a pair of conductive channels are formed inside the corresponding body region 22. In particular, the first conductive channel starts from the first source region 30' and extends parallel to the XY plane, under the corresponding gate dielectric region 12 to the peripheral portion 26' of the body region 22; the second conductive channel starts from the second source region 30" and extends parallel to the XY plane, under the corresponding gate dielectric region 12 to the peripheral portion 26" of the body region 22.

[0035] Thus, in each cell 2 , current may initially flow in a corresponding conductive channel formed in the respective body region 22 ; the current then follows a vertical direction (parallel to the Z-axis) inside the drain region 8 towards the drain metallization 37 .

[0036] In practice, the MOSFET transistor 1 has a superjunction structure and, as described above, comprises a plurality of cells 2. Figure 1 As shown in FIG. 1 , with reference to the second source region 30″ (but the same considerations also apply to the first source region 30′), the second source region 30″ forms a parasitic bipolar transistor of NPN type (in Figure 1 The emitter of FIG. 1 (shown qualitatively in FIG. 1 ) has a base formed by the enriched region 23 and a drain formed by a portion of the drain region 8 in contact with the peripheral portion 26″ of the body region 8.

[0037] Having said that, due to the fact that the enrichment region 23 protrudes laterally relative to the second source region 30″, it happens that the base of the parasitic bipolar transistor has a high concentration and the distance between the drain and the emitter is large. For these reasons, the parasitic bipolar transistor has a parameter h fe The value of the current that can flow into the base of the parasitic bipolar transistor before it switches on and risks being destroyed by the MOSFET transistor 1 is particularly high. For this reason, the MOSFET transistor 1 is particularly robust, for example if tested with a so-called UIS test.

[0038] Unless otherwise stated, the MOSFET transistor 1 is manufactured by the manufacturing process described below with reference to a single cell 2 .

[0039] like Figure 2 As shown in FIG. 1 , a semiconductor body 4 is initially formed in a known manner, the semiconductor body 4 comprising a substrate 6 , a drain region 8 , and a reinforcement region 24 .

[0040] In particular, the reinforcement region 24 is formed to be buried inside the drain region 8 and to be spaced apart from the top surface S topThe drain region 8 and the reinforcement region 24 can be formed in a manner known per se, for example, by performing a series of epitaxial growths and ion implantations starting from the substrate 6; the details relating to the manufacture of the drain region 8 and the reinforcement region 24 are in any case irrelevant for the purpose of manufacturing the MOSFET transistor 1.

[0041] Then, if Figure 3 As shown in FIG. 1 , a first ion implantation of a P-type dopant (eg, boron) is performed to implant a P-type dopant at the top surface S top A P+ type first thin layer 123 is formed between the top surface S and the reinforcing region 24, and the first thin layer 123 extends into the drain region 8. In particular, the first thin layer 123 is top Both the reinforcement area 24 extend at a certain distance from each other.

[0042] In more detail, the aforementioned first injection Figure 3 Indicated by arrow 50, and may be included in 1*10 13 cm -2 With 1*10 15 cm -2 and with an energy between 100 KeV and 500 KeV and arranged on the top surface S top The first resist mask 40 is formed on the first thin layer 123. In particular, the first mask 40 makes the first thin layer 123 have an elongated shape parallel to the Y axis; in addition, the first thin layer 123 has an approximately symmetrical shape about the symmetry plane H and parallel to the X axis, and it protrudes laterally in two directions relative to the reinforcing area 24 of the underlying layer, so it has a larger width relative to the width of the reinforcing area 24.

[0043] Then, if Figure 4 As shown in FIG. , the first mask 40 is removed and the top surface S top A dielectric layer 112 and a conductive layer 114 are formed thereon.

[0044] The dielectric layer 112 is formed of, for example, a thermally grown oxide and has a top surface S2 formed above the semiconductor body 4. top For example, the conductive layer 114 is formed by deposition of polysilicon and extends over the dielectric layer 112, making direct contact therewith.

[0045] Then, if Figure 5 As shown in FIG. 1 , a portion of the conductive layer 114 and a lower portion of the dielectric layer 112 are selectively removed to form a conductive layer facing the top surface S topIn practice, the remaining portion of the dielectric layer 112 forms the gate dielectric region 12; the remaining portion of the conductive layer 114 forms the gate conductive region 14. In addition, the window 99 extends between the two gate dielectric regions 12 and between the two gate conductive regions 14; the window 99 has a shape that is approximately symmetrical about the symmetry plane H.

[0046] In more detail, the window 99 has an elongated shape parallel to the Y axis and covers the reinforcement area 24 at a certain distance. In addition, parallel to the X axis, the window 99 has a width that is smaller than the width of the first thin layer 123. Without loss of generality, Figure 5 In the example shown in , the window 99 has approximately the same width as the reinforcement area 24 .

[0047] Then, if Figure 6 As shown in FIG. 1 , a second ion implantation of a P-type dopant (eg, boron) is performed to implant a P-type dopant at the top surface S top A P-type second thin layer 125 is formed between the first thin layer 123 and the drain region 8. In particular, the second thin layer 125 is top Both extend at a certain distance from the underlying first thin layer 123 .

[0048] In more detail, the aforementioned second injection Figure 6 Indicated by arrow 60, and may be included in 1*10 12 cm -2 With 1*10 14 cm -2 10 and occurs through the window 99 with, for example, an energy comprised between 60 KeV and 300 KeV. Thus, the second thin layer 125 has an elongated shape parallel to the Y axis, approximately symmetrical with respect to the symmetry plane H; moreover, parallel to the X axis, the second thin layer 125 has a smaller width relative to the width of the first thin layer 123. Thus, parallel to the X axis, the first thin layer 123 protrudes laterally in two directions relative to the overlying first thin layer 125. Furthermore, without loss of generality, the second thin layer 125 has substantially the same width as the reinforcement zone 24.

[0049] Then, a heat treatment is performed, for example, with a duration comprised between one and four hours and at a temperature comprised between 900° C. and 1200° C. In this way, the doping substances forming the first thin layer 123 and the second thin layer 125 diffuse. In particular, as Figure 7 As shown in FIG. 1 , diffusion of the doping substances forming the first thin layer 123 and the second thin layer 125 results in the formation of the body region 22 and the enrichment region 23 .

[0050] Then, if Figure 8As shown in FIG. 1 , a second mask 80 is formed inside the window 99, which laterally defines a first opening 81 and a second opening 82, which are laterally offset parallel to the X-axis, extend on opposite sides of the second mask 80 and face the top surface S. top In particular, the first opening 81 is laterally defined by the second mask 80, by one of the two gate dielectric regions 12, and by the overlying gate conductive region 14, while the second opening 82 is laterally defined by the second mask 80, by the other of the two gate dielectric regions 12, and by the overlying gate conductive region 14.

[0051] Then, if Figure 8 As shown in FIG. 1 , a third ion implantation of an N-type dopant (e.g., phosphorus) is performed to form an N+-type third thin layer 130′ and a fourth thin layer 130″ through the first opening 81 and the second opening 82, respectively. The third thin layer 130′ and the fourth thin layer 130″ are laterally offset along the X axis and extend into the body region 22. top There is a certain distance between the enrichment area 23 and the enrichment area 23 .

[0052] In more detail, the aforementioned third injection Figure 8 Indicated by arrow 90, and may be included in 10 15 cm -2 with 10 16 cm -2 and occurs with an energy comprised between 60 KeV and 150 KeV, for example.

[0053] Then, if Fig. 9 As shown in , the second mask 80 is removed and a further heat treatment is performed, for example, the heat treatment having a duration comprised between 15 minutes and 60 minutes and at a temperature comprised between 900° C. and 1100° C. In this way, diffusion of the doping substances forming the third thin layer 130′ and the fourth thin layer 130″ occurs, which are transformed into the first source region 30′ and the second source region 30″, respectively. Furthermore, as a first approximation, this further heat treatment has a negligible effect on the body region 22 and the enrichment region 23.

[0054] The manufacturing process can then be carried out in a manner known per se and therefore not shown, in order to form the gate insulation region 16 , the source metallization 17 , and the drain metallization 37 .

[0055] As can be clearly seen from the foregoing description, the present MOSFET transistor has an advantage in reducing the risk of turning on a parasitic bipolar transistor. In addition, due to the shape of the body region, the present MOSFET transistor is characterized by a reduced electric field under the gate dielectric region, resulting in a reduced charge injected into the gate-drain capacitor; it can also be demonstrated that the Miller effect is reduced, resulting in reduced energy dissipation and increased switching efficiency.

[0056] Finally, it is evident that modifications and variations may be made to the previously described MOSFET transistor and the related manufacturing process without departing from the scope of the present disclosure as defined in the appended claims.

[0057] For example, the doping types may be reversed relative to what has been described. Furthermore, the materials may be different from what has been described.

[0058] A MOSFET transistor is generally described as comprising a semiconductor body (4) comprising a front surface (S top ), the MOSFET transistor (1) further comprising at least one unit (2), the unit comprising: a pair of gate structures (10) which are laterally offset parallel to the first axis (X), and each gate structure comprises a gate electrode arranged on the front surface (S top ) on the front surface (S), and a corresponding gate dielectric region (12) arranged on the corresponding gate dielectric region (12), and a corresponding gate conductive region (14) arranged on the corresponding gate dielectric region (12); a main structure (20) of a second conductive type, which includes a main region (22) and a reinforcement region (24), the main region (22) extending from the front surface (S top ) starts to extend inside the drain region (8) and contacts a portion of the gate dielectric region (12), a reinforcement region (24) extends inside the drain region (8) and below the body region (22); and a pair of source regions (30′, 30″) of the first conductivity type, the pair of source regions extending from the front surface (S top ) start to extend inside the main region (22) and each contacts the corresponding gate dielectric region (12); wherein the main structure (20) includes an enriched region (23) having a doping level greater than the doping level of the main region (22) and extending inside the main region (22) and below the source regions (30′, 30″); and wherein parallel to the first axis (X), the enriched region (23) protrudes laterally in two directions relative to the paired source regions (30′, 30″).

[0059] The body region (22) has a circular shape; and the width of the body region (22) measured parallel to the first axis (X) has a non-monotonic trend of increasing with depth and has a maximum value (W ) at a depth greater than the maximum depth reached by the source region (30′, 30″) max ).

[0060] Parallel to the first axis (X), the enriched zone ( 23 ) also projects transversely in two directions relative to the reinforced zone ( 24 ).

[0061] The gate structure (10), the body structure (20), and the source regions (30', 30") have an elongated shape parallel to a second axis (Y) perpendicular to the first axis (X).

[0062] The enhancement region (24) has a doping level lower than the doping level of the enrichment region (23).

[0063] The first conductivity type is N-type conductivity; and the second conductivity type is P-type conductivity.

[0064] A process for manufacturing a MOSFET transistor is summarized as comprising: forming a semiconductor body (4) comprising a front surface (S top ) defined by a drain region (8) of a first conductivity type; and forming at least one unit (2), the unit comprising: forming a pair of gate structures (10), the pair of gate structures (10) being laterally offset parallel to the first axis (X), and each comprising a gate electrode arranged on the front surface (S top ) on the corresponding gate dielectric region (12), and a corresponding gate conductive region (14) arranged on the corresponding gate dielectric region (12); forming a main body structure (20) of a second conductive type, wherein forming the main body structure (20) includes: forming a main body region (22) and forming a reinforcement region (24), the main body region (22) extending from the front surface (S top ) starts to extend inside the drain region (8) and contacts the portion of the gate dielectric region (12), the reinforcement region (24) extends inside the drain region (8) and below the body region (22); and a pair of source regions (30′, 30″) of the first conductivity type are formed, the pair of source regions (30′, 30″) extending from the front surface (S top ) start to extend inside the main region (22) and each contact the corresponding gate dielectric region (12); and wherein forming the main structure (20) also includes: forming an enriched region (23), which has a doping level greater than the doping level of the main region (22) and extends inside the main region (22) and below the source region (30′, 30″); and wherein parallel to the first axis (X), the enriched region (23) protrudes laterally in two directions relative to the paired source regions (30′, 30″).

[0065] The manufacturing process comprises: after forming a reinforcement region (24) and before forming a gate structure (10), by first implanting a second conductive type dopant, top) and the reinforcing region (24) to form a first injection layer (123) extending into the drain region (8); then forming a gate dielectric region (12) and a gate conductive region (14); then, through a second injection of a second conductive type dopant, forming a first injection layer (123) extending into the drain region (8) on the front surface (S top ) and the first injection layer (123) and forming a second injection layer (125) extending into the drain region (8); and subsequently performing a first heat treatment to cause diffusion of doping substances of the first injection layer and the second injection layer (123, 125), and subsequent formation of the main region (22) and the enrichment region (23).

[0066] The second implantation is performed through a window (99) formed by the gate dielectric region (12) and the gate conductive region (14).

[0067] Forming the first implantation layer (123) includes performing the first implantation through a mask (40) arranged on the front surface (S top ) and such that, parallel to the first axis (X), the first injection layer (123) protrudes laterally in two directions relative to the reinforcement zone (24).

[0068] Forming the second injection layer (125) includes forming the second injection layer (125) such that the first injection layer (123) protrudes laterally in two directions relative to the second injection layer (125) parallel to the first axis (X).

[0069] Forming a pair of source regions (30′, 30″) includes: after a first heat treatment, forming a third injection layer and a fourth injection layer (130′, 130″) by a third injection of a first conductive type of dopant, the third injection layer and the fourth injection layer (130′, 130″) extending inside the main region (22) and above the enriched region (23); then performing a second heat treatment to cause diffusion of the dopant of the third injection layer and the fourth injection layer (130′, 130″), and the subsequent formation of the source regions (30′, 30″).

[0070] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0071] In light of the above detailed description, these and other changes can be made to the embodiments. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A transistor, comprising: a semiconductor body including a drain region of a first conductivity type, the drain region being defined by a first surface, the first surface being opposite to the second surface along a first direction; as well as a plurality of cells, the plurality of cells being in the semiconductor body, the plurality of cells comprising: A pair of gate structures, wherein the pair of gate structures are laterally offset along a second direction, the second direction being transverse to the first direction, each gate structure comprising a corresponding gate dielectric region and a corresponding gate conductive region, the corresponding gate dielectric region being arranged on the first surface, and the corresponding gate conductive region being arranged on the corresponding gate dielectric region; a main body structure of a second conductivity type, the main body structure comprising a main body region and a reinforcement region, the main body region extending from the first surface along the first direction into the drain region and contacting a portion of the gate dielectric region, the reinforcement region extending between the main body region and the second surface along the first direction into the drain region; a pair of source regions of the first conductivity type, the pair of source regions extending from the first surface inside the body region, each source region being coupled to a corresponding gate dielectric region; and An enriched region, wherein the enriched region is in the main structure, the enriched region has a doping level greater than the doping level of the main region, and extends inside the main region between the source region and the reinforcement region, the enriched region has a first dimension along the second direction, and the first dimension is greater than a second dimension of the reinforcement region along the second direction.

2. A transistor according to claim 1, wherein the main body region has a circular shape; and wherein the width of the main body region along the second direction has a non-monotonic trend that increases with depth along the first direction, and has a maximum width along the second direction at a depth along the first direction greater than the maximum depth reached by the source region.

3. The transistor according to claim 1, wherein Along the second direction, the enriched region laterally protrudes further than a maximum width between a first source region of the pair of source regions and a second source region of the pair of source regions along the second direction. 4 . The transistor of claim 1 , wherein the gate structure, the body structure, and the source region have an elongated shape in a third direction, the third direction being transverse to the first direction and the second direction. The transistor of claim 1 , wherein the reinforcement region has a doping level lower than a doping level of the enrichment region.

6. The transistor of claim 1, wherein the first conductivity type is N-type conductivity; and wherein the second conductivity type is P-type conductivity.

7. A method comprising: forming a semiconductor body having a front surface opposite to the second surface along a first direction, the semiconductor body including a drain region of a first conductivity type, the drain region being defined by the front surface; as well as Forming a unit, forming the unit comprises: forming a pair of gate structures, each gate structure comprising a corresponding gate dielectric region and a corresponding gate conductive region, wherein the corresponding gate dielectric region is on the front surface and the corresponding gate conductive region is on the corresponding gate dielectric region; Forming a main structure of a second conductivity type, wherein forming the main structure of the second conductivity type comprises: forming a body region extending from the front surface along the first direction inside the drain region by a first distance and contacting a portion of the gate dielectric region; and forming a reinforcement region, wherein the reinforcement region extends along the first direction inside the drain region to a second distance, wherein the second distance is greater than the first distance; forming a pair of source regions of the first conductivity type, the pair of source regions extending from the front surface inside the body region, and each of the source regions contacting a corresponding gate dielectric region; and An enriched region is formed, the enriched region having a doping level greater than that of the body region and extending inside the body region along the first direction between the source region and the reinforcement region.

8. The method according to claim 7, comprising: After forming the reinforcement region and before forming the gate structure, forming a first injection layer between the front surface and the reinforcement region by first injection of a dopant of the second conductivity type, wherein the first injection layer extends into the drain region; forming each gate dielectric region and each gate conductive region; forming a second injection layer between the front surface and the first injection layer by a second injection of the second conductivity type dopant, the second injection layer extending into the drain region; as well as A first thermal treatment is performed, resulting in diffusion of the dopant species of the first implantation layer and diffusion of the dopant species of the second implantation layer, and subsequent formation of the body region and the enrichment region. 9 . The method of claim 8 , wherein the second implant is performed through a window formed by the gate dielectric region and the gate conductive region.

10. The method according to claim 8, wherein forming the first injection layer comprises: The first implantation is performed through a mask, the mask being on the front surface, the first implantation layer protruding further in a second direction transverse to the first direction than a maximum width of the reinforcement region in the second direction.

11. The method according to claim 8, wherein: The first injection layer protrudes further along a second direction transverse to the first direction than a maximum width of the second injection layer along the second direction.

12. The method according to claim 8, wherein forming the pair of source regions comprises: After the first heat treatment, a third injection layer and a fourth injection layer are formed by a third injection of the first conductivity type doping material, wherein the third injection layer and the fourth injection layer extend inside the body region along the first direction between the enriched region and the front surface; as well as A second heat treatment is performed, resulting in diffusion of the dopant substance of the third implantation layer and diffusion of the dopant substance of the fourth implantation layer, and formation of the source region.

13. A device comprising: A substrate having a first surface, the first surface being opposite to the second surface along a first direction; a drain region, the drain region being in the substrate, the drain region having a first surface coplanar with the first surface of the substrate, and the drain region having a first conductivity type; a first gate structure, the first gate structure being on the first surface of the substrate; a second gate structure, the second gate structure being on the first surface of the substrate, the second gate structure being spaced apart from the first gate structure along a second direction transverse to the first direction; A main structure extending into the drain region, the main structure comprising: a main body region, the main body region extending along the first direction into the drain region by a first distance, the main body region comprising: a first surface coplanar with the first surface of the substrate, the first surface having a first width along the second direction; and a maximum width along the second direction that is greater than the first width of the first surface of the body region, the maximum width being a first depth along the first direction, the first depth being between the first surface of the substrate and the second surface of the substrate; and a reinforcement region having a second depth along the first direction greater than the first depth, the reinforcement region having a second width along the second direction less than the first width; and A plurality of source regions are provided in the body region, each source region having a first surface coplanar with the first surface of the substrate.

14. The device of claim 13, wherein the first gate structure comprises: a first gate dielectric region, the first gate dielectric region being on the first surface of the substrate; a first gate conductive region, the first gate conductive region being on the first gate dielectric region; and A first gate insulating region is directly on the first gate dielectric region and the first surface of the substrate. 15 . The device of claim 14 , wherein both the first gate dielectric region and the first gate insulation region are in direct contact with corresponding source regions of the plurality of source regions.

16. The device of claim 14, wherein the first gate dielectric region comprises oxide and the first gate conductive region comprises polysilicon. 17 . The device of claim 14 , wherein the first gate conductive region of the first gate structure is electrically coupled to a second gate conductive region of the second gate structure.

18. The device of claim 13, wherein the body region has a second conductivity type that is different from the first conductivity type. 19 . The device of claim 13 , wherein the plurality of source regions have a maximum depth along the first direction that is less than a first depth. 20 . The device of claim 19 , further comprising an enriched region in the body region, the enriched region having a fourth width greater than the second width of the reinforcement region.

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