Silicon carbide MOSFET structure with nail-shaped electrode on back surface and preparation process thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure with a nail-shaped electrode on the back surface and a preparation process of the silicon carbide MOSFET structure. The silicon carbide MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a source electrode, a grid electrode, a grid oxide layer, a semiconductor epitaxial layer and a drain electrode, wherein an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer are formed in the semiconductor epitaxial layer through ion implantation, and a discharge tip is further arranged in the middle area of the drain electrode in the single MOS cell; wherein the section shape of the N substrate layer is matched with the shape of the discharge tip. According to the invention, current can be guided to flow through the channel more uniformly through the discharge tip, the problem of over-high local current density is reduced, heat can be managed better through the discharge tip, formation of local hot spots is reduced, the risk of thermal runaway is reduced, and the long-term stability of the device is improved.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a silicon carbide MOSFET structure with a back-side nail-shaped electrode and a preparation process thereof. Background Art

[0002] The back-side spike electrode silicon carbide (SiC) MOSFET structure is an advanced design designed to optimize device performance, especially in high voltage, high frequency and high temperature applications. This structure improves the device's electrical characteristics, thermal management and reliability by introducing a special spike electrode on the back side of the MOSFET.

[0003] The existing patent discloses a SGT MOSFET structure with a back-side spike electrode (publication number CN221379378U), including: a main body and a wafer main body, the back side of the main body is provided with a drain electrode; a substrate, the substrate is provided on the back side of the main body, and the surface of the substrate is provided with a substrate spike-shaped recess; a source electrode, the source electrode is provided on the front side of the main body, and a semiconductor, the semiconductor is provided on the surface of the main body. In the technology disclosed in the patent, the problem of excessive local current density is prone to occur, so that the formation of local hot spots is very likely to occur, thereby increasing the risk of thermal runaway. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a silicon carbide MOSFET structure with a back-side nail-shaped electrode and a preparation process thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide MOSFET structure with a back-side spike electrode is provided, comprising a plurality of mutually parallel MOS cells, wherein the MOS cell comprises a source, a gate, a gate oxide layer, a semiconductor epitaxial layer and a drain, wherein an N substrate layer, an N drift layer, a P+ layer, a P well layer and an N well layer are formed inside the semiconductor epitaxial layer by ion implantation, and the middle region of the drain in a single MOS cell also comprises a discharge tip; The cross-sectional shape of the N substrate layer matches the shape of the discharge tip.

[0006] Furthermore, both sides of the drain in a single MOS cell also include side tips.

[0007] Furthermore, both sides of the drain in a single MOS cell further include polysilicon, wherein the size of the cross-sectional profile of the polysilicon is the same as the size of the cross-sectional profile of the discharge tip.

[0008] Furthermore, the left and right sides of the N drift layer in a single MOS cell are doped with doping particles.

[0009] Furthermore, drift region P-layers are formed on the left and right sides of the N drift layer in a single MOS cell by ion implantation, wherein the drift region P-layer contacts the N substrate layer, and the drift region P-layers between adjacent MOS cells are integrated.

[0010] Furthermore, a substrate region P-layer is formed on the left and right sides of the N-drift layer in a single MOS cell by ion implantation, and the substrate region P-layer is in ohmic contact with the drain.

[0011] A process for preparing a back-side spike-shaped electrode silicon carbide MOSFET structure comprises the following steps: S1, cleaning the back of the semi-finished semiconductor epitaxial layer and applying photoresist, and then photolithography to form a groove that matches the discharge tip; S2, after cleaning the back side of the semiconductor epitaxial layer and the inside of the groove, firstly forming the discharge tip part and then forming the drain part by vapor deposition; S3. Test the electrode performance of the source, gate, and drain of the formed silicon carbide MOSFET structure.

[0012] Furthermore, in step S, the electrode performance of the MOSFET structure is determined based on the resistance between the drain and the source of the MOSFET structure in the on state, the leakage current between the drain and the source when no voltage is applied to the gate, and the maximum electric field strength that the gate oxide layer can withstand, then: In the formula, represents the performance coefficient of the tested MOSFET structure, It represents the resistance between the drain and the source in the on state. It represents the leakage current between the drain and the source when no voltage is applied to the gate. Indicates the maximum electric field strength that the gate oxide layer can withstand.

[0013] Furthermore, when When , it means that the electrode performance of the tested MOSFET structure meets the requirements.

[0014] The present invention provides a silicon carbide MOSFET structure with a back-side spike electrode and a preparation process thereof. Compared with the prior art, the method has the following effects: 1. The present invention can help guide the current to flow more evenly through the channel through the discharge tip, reduce the problem of excessive local current density, and because the discharge tip can better manage heat, the formation of local hot spots is reduced, the risk of thermal runaway is reduced, and the long-term stability of the device is improved.

[0015] 2. The present invention can effectively disperse and homogenize the electric field distribution by arranging side tips on both sides. Especially in high voltage applications, the tips can guide the strong electric field from the key area to a wider area, thereby avoiding the breakdown phenomenon caused by excessive local electric field. And by introducing the side tips, a relatively gentle electric field gradient can be formed in the electric field concentration area, thereby reducing the electric field peak and improving the voltage resistance of the device.

[0016] 3. The present invention uses polysilicon as a field plate to provide additional shielding under high voltage conditions, so that the electric field will not be concentrated in the sensitive area, thereby increasing the breakdown voltage. In addition, polysilicon can reduce edge capacitance because they can effectively disperse the electric field and reduce the capacitive coupling effect with surrounding structures.

[0017] 4. The present invention adopts a design similar to a field limiting ring by doping particles, which can provide additional shielding effect under high voltage conditions so that the electric field will not be concentrated in sensitive areas. At the same time, the field limiting ring has a problem of limited use range. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of the structure of Embodiment 5 of the present invention; Figure 6 This is a schematic diagram of the structure of Embodiment 6 of the present invention; Figure 7 Graph showing the relationship between different gate-source voltages and on-resistance in the present invention.

[0019] In the figure: 1, source; 2, gate oxide layer; 3, gate; 4, P+ layer; 5, P well layer; 6, N well layer; 7, drain; 8, N substrate layer; 9, N drift layer; 10, polysilicon; 11, doped particles; 12, drift region P-layer; 71, discharge tip; 72, side tip; 121, substrate region P-layer. DETAILED DESCRIPTION

[0020] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 As shown, a preparation process of a back-side spike electrode silicon carbide MOSFET structure includes the following steps: Step 1: After cleaning and applying photoresist to the back of the semi-finished semiconductor epitaxial layer, a groove matching the discharge tip 71 is formed by photolithography; Step 2: After cleaning the back of the semiconductor epitaxial layer and the inside of the groove, the discharge tip 71 is first formed by vapor deposition, and then the drain 7 is formed; Step 3: Determine the electrode performance of the MOSFET structure based on the resistance between the drain 7 and the source 1 in the on state of the MOSFET structure, the leakage current between the drain 7 and the source 1 when no voltage is applied to the gate 3, and the maximum electric field strength that the gate oxide layer 2 can withstand, then: In the formula, represents the performance coefficient of the tested MOSFET structure, represents the resistance between drain 7 and source 1 in the on state, represents the leakage current between the drain 7 and the source 1 when no voltage is applied to the gate 3, Indicates the maximum electric field strength that the gate oxide layer 2 can withstand.

[0022] The performance of the electrode is tested for any MOSFET structure. The resistance between the drain 7 and the source 1 in the on state is (Ω), the maximum electric field strength that the gate oxide layer 2 can withstand is (V), the leakage current between the drain 7 and the source 1 when no voltage is applied to the gate 3 is (mA), then: From the above calculation, we can know that the performance coefficient of the MOSFET structure tested this time is , then it means that the electrode performance of the tested MOSFET structure meets the requirements. And compare multiple groups of sample data: Table 1 Partial test data and MOSFET structure status From the data in Table 1 above, we can know that when the sample tends to infinity, the performance coefficient G will be used to classify whether the MOSFET structure meets the use requirements, that is, when When , it means that the electrode performance of the tested MOSFET structure meets the requirements.

[0023] Example 1 like Figure 1As shown, according to one aspect of the present invention, a silicon carbide MOSFET structure with a back-side nail-shaped electrode is provided, which is composed of a plurality of mutually parallel MOS cells, wherein the MOS cell includes a source 1, a gate 3, a gate oxide layer 2, a semiconductor epitaxial layer and a drain 7, wherein an N substrate layer 8, an N drift layer 9, a P+ layer 4, a P well layer 5 and an N well layer 6 are formed inside the semiconductor epitaxial layer by ion implantation, and the middle area of ​​the drain 7 in a single MOS cell also includes a discharge tip 71; wherein the cross-sectional shape of the N substrate layer 8 matches the shape of the discharge tip 71. The discharge tip 71 can significantly improve the device sensitivity and reduce the drain-source resistance by reducing the distance between the drain and the source. And the discharge tip 71 can help guide the current to flow through the channel more evenly, reduce the problem of excessive local current density, avoid the formation of hot spots, and thus improve the thermal stability and reliability of the device. And because the discharge tip 71 can better manage heat, the formation of local hot spots is reduced, the risk of thermal runaway is reduced, and the long-term stability of the device is improved.

[0024] Example 2 like Figure 2 As shown, the drain 7 in a single MOS cell also includes side tips 72 on both sides. Providing the side tips 72 on both sides can effectively disperse and evenly distribute the electric field. Especially in high voltage applications, the tips can guide the strong electric field from the key area (such as the edge of the gate oxide layer 2) to a wider area, thereby avoiding the breakdown phenomenon caused by excessive local electric field. In addition, by introducing the side tips 72, a relatively gentle electric field gradient can be formed in the electric field concentration area, thereby reducing the electric field peak and improving the voltage resistance of the device.

[0025] Example 3 like Figure 3 As shown, both sides of the drain 7 in a single MOS cell also include polysilicon 10, wherein the size of the cross-sectional profile of the polysilicon 10 is the same as the size of the cross-sectional profile of the discharge tip 71. Since the polysilicon 10 also has the ability to conduct electricity, but the ability to conduct electricity is far less than that of the discharge tip 71 and the side tip 72. This allows the polysilicon 10 to act as a field plate, providing additional shielding under high voltage conditions, so that the electric field will not be concentrated in the sensitive area, thereby increasing the breakdown voltage. In addition, the polysilicon 10 can reduce the edge capacitance because they can effectively disperse the electric field and reduce the capacitive coupling effect with the surrounding structures.

[0026] Example 4 like Figure 4As shown, the left and right sides of the N drift layer 9 in a single MOS cell are also doped with doping particles 11. By introducing doping particles 11 on both sides of the N drift layer 9, the electric field distribution can be effectively dispersed and uniformed, thereby avoiding excessive local electric field and reducing the electric field concentration effect to improve the withstand voltage capability of the device. In addition, the doping particles 11 are similar to field limiting rings, that is, they can provide additional shielding under high voltage conditions, so that the electric field will not be concentrated in sensitive areas, but at the same time, they are subject to the problem of limited use range of the field limiting ring.

[0027] Example 5 like Figure 5 As shown, the drift region P-layer 12 is formed on the left and right sides of the N drift layer 9 in a single MOS cell by ion implantation, wherein the drift region P-layer 12 is in contact with the N substrate layer 8, and the drift region P-layer 12 between adjacent MOS cells is integral. The PN junction between the drift region P-layer 12 and the N drift layer 9 can generate a built-in electric field under high voltage conditions, and this built-in electric field helps to disperse the externally applied electric field, thereby avoiding excessive local electric field and reducing the electric field concentration effect. In addition, the drift region P-layer 12 can help guide the current to flow through the channel more evenly, reduce the problem of excessive local current density, and thus improve the thermal stability and reliability of the device.

[0028] Example 6 like Figure 6 As shown, the left and right sides of the N drift layer 9 in a single MOS cell are also formed with a substrate region P-layer 121 by ion implantation, and the substrate region P-layer 121 is in ohmic contact with the drain 7. The substrate region P-layer 121 can reduce the edge capacitance because they can effectively disperse the electric field and reduce the capacitive coupling effect with the surrounding structure, which is very important for high-frequency applications because it can reduce switching losses and increase switching speed.

[0029] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A silicon carbide MOSFET structure with a back-side spike electrode, comprising a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a source electrode (1), a gate electrode (3), a gate oxide layer (2), a semiconductor epitaxial layer and a drain electrode (7), wherein an N substrate layer (8), an N drift layer (9), a P+ layer (4), a P well layer (5) and an N well layer (6) are formed inside the semiconductor epitaxial layer by ion implantation, characterized in that: The middle region of the drain electrode (7) in a single MOS cell also includes a discharge tip (71); The cross-sectional shape of the N substrate layer (8) matches the shape of the discharge tip (71).

2. The silicon carbide MOSFET structure with a back-side spike electrode according to claim 1, characterized in that: Both sides of the drain electrode (7) in a single MOS cell also include side tips (72).

3. The silicon carbide MOSFET structure with a back-side spike electrode according to claim 1, characterized in that: Both sides of the drain electrode (7) in a single MOS cell also include polysilicon (10), wherein the size of the cross-sectional profile of the polysilicon (10) is the same as the size of the cross-sectional profile of the discharge tip (71).

4. The silicon carbide MOSFET structure with a back-side spike electrode according to claim 1, characterized in that: The left and right sides of the N drift layer (9) in a single MOS cell are also doped with doping particles (11).

5. The silicon carbide MOSFET structure with a back-side spike electrode according to claim 1, characterized in that: A drift region P-layer (12) is formed on the left and right sides of the N drift layer (9) in a single MOS cell by ion implantation, wherein the drift region P-layer (12) is in contact with the N substrate layer (8), and the drift region P-layers (12) between adjacent MOS cells are integrated.

6. The silicon carbide MOSFET structure with a back-side spike electrode according to claim 4, characterized in that: A substrate region P-layer (121) is formed on the left and right sides of the N drift layer (9) in a single MOS cell by ion implantation, and the substrate region P-layer (121) is in ohmic contact with the drain (7).

7. A process for preparing a back-side spike electrode silicon carbide MOSFET structure, characterized in that: The preparation process of the back-side spike-shaped electrode silicon carbide MOSFET structure is applied to the silicon carbide MOSFET structure according to any one of claims 2 to 6, and the preparation process of the back-side spike-shaped electrode silicon carbide MOSFET structure comprises the following steps: S1, cleaning the back side of the semi-finished semiconductor epitaxial layer, applying photoresist, and then photolithographically forming a groove matching the discharge tip (71); S2, after cleaning the back side of the semiconductor epitaxial layer and the inside of the groove, firstly forming the discharge tip (71) part and then forming the drain (7) part by vapor deposition; S3. Testing the electrode performance of the source (1), gate (3), and drain (7) of the formed silicon carbide MOSFET structure.

8. The process for preparing a back-side spike electrode silicon carbide MOSFET structure according to claim 7, characterized in that: In step S3, the electrode performance of the MOSFET structure is determined based on the resistance between the drain (7) and the source (1) of the MOSFET structure in the on state, the leakage current between the drain (7) and the source (1) when no voltage is applied to the gate (3), and the maximum electric field strength that the gate oxide layer (2) can withstand, then: In the formula, represents the performance coefficient of the tested MOSFET structure, represents the resistance between the drain (7) and the source (1) in the on state, represents the leakage current between the drain (7) and the source (1) when no voltage is applied to the gate (3), Indicates the maximum electric field strength that the gate oxide layer (2) can withstand.

9. The process for preparing a back-side spike electrode silicon carbide MOSFET structure according to claim 8, characterized in that: when When , it means that the electrode performance of the tested MOSFET structure meets the requirements.

Images