Back contact battery and preparation method thereof

Abstract

The invention relates to a back contact cell and a preparation method thereof, the back contact cell comprises a substrate, the substrate has a first surface and a second surface which are opposite, the first surface is provided with N-type regions, isolation regions and P-type regions which are alternately distributed, and the isolation regions are located between the N-type regions and the P-type regions; the first doping layer is located in the P-type region; the isolation layer is located in the isolation region; the second doping layer is located in the N-type region; the transparent conductive layer covers the first doping layer, the isolation layer and the second doping layer, the transparent conductive layer is provided with a through isolation groove, and the isolation groove is arranged corresponding to the isolation layer; and the electrodes are respectively arranged on the transparent conductive layers covering the first doped layer and the second doped layer. According to the back contact battery, direct ohmic contact between the electrode and the first doping layer and between the electrode and the second doping layer is avoided by arranging the transparent conducting layer, so that the electrode can be manufactured on the conducting layer by using cheap metal, and the cost of the battery can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back contact cell and a preparation method thereof. Background Art

[0002] As a clean and environmentally friendly new energy, solar photovoltaic is an important development direction of renewable energy in various countries. At present, the electrodes of solar cells are in ohmic contact with the doping layer. Due to the limitations of materials and processes, only silver paste can be used to make electrodes, resulting in high battery costs. Summary of the invention

[0003] Based on this, it is necessary to provide a back contact battery and a preparation method thereof to address the problem of high battery costs.

[0004] Embodiments of the present disclosure provide a back-contact battery.

[0005] The back contact battery provided by the embodiment of the present disclosure includes:

[0006] A substrate, the substrate having a first surface and a second surface opposite to each other, the first surface being provided with N-type regions, isolation regions and P-type regions that are alternately distributed, and the isolation region being located between the N-type region and the P-type region;

[0007] A first doped layer, located in the P-type region;

[0008] An isolation layer, located in the isolation area;

[0009] A second doped layer, located in the N-type region;

[0010] a transparent conductive layer covering the first doped layer, the isolation layer and the second doped layer, wherein the transparent conductive layer is provided with an isolation groove penetrating therethrough, and the isolation groove is provided corresponding to the isolation layer;

[0011] The electrodes are respectively arranged on the transparent conductive layer covering the first doping layer and the second doping layer.

[0012] In one embodiment, the first doping layer, the isolation layer and the second doping layer are an integrated structure.

[0013] In one embodiment, the materials of the first doping layer and the second doping layer are doped polysilicon with opposite electrical properties, and the material of the isolation layer is intrinsic polysilicon.

[0014] In one embodiment, a first passivation layer and a second passivation layer are formed on the first surface and the second surface of the substrate respectively, the first passivation layer is formed on the substrate, and the first doped layer, the isolation layer and the second doped layer are formed on the first passivation layer.

[0015] In one embodiment, an aluminum oxide layer and an anti-reflection layer are further formed on the second passivation layer.

[0016] The present disclosure provides a method for preparing a back-contact battery.

[0017] The method for preparing a back contact battery provided in the embodiment of the present disclosure includes:

[0018] Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface being provided with N-type regions, isolation regions and P-type regions distributed alternately, the isolation region being located between the N-type region and the P-type region;

[0019] A first doping layer formed in the P-type region;

[0020] an isolation layer formed in the isolation region;

[0021] A second doping layer formed in the N-type region;

[0022] A transparent conductive layer is formed covering the first doping layer, the isolation layer and the second doping layer, and an isolation groove is formed penetrating the transparent conductive layer, wherein the isolation groove is arranged corresponding to the isolation layer; and electrodes are formed on the transparent conductive layer covering the first doping layer and the second doping layer.

[0023] In one embodiment, an intrinsic semiconductor material layer is formed covering the first surface;

[0024] A diffusion process is adopted to selectively dope the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region, so that the portion of the intrinsic semiconductor material layer located in the P-type region forms a first doped layer, the portion located in the N-type region forms a second doped layer, and the portion located in the isolation region forms the isolation layer.

[0025] In one embodiment, the step of selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region respectively by a diffusion process so that the portion of the intrinsic semiconductor material layer located in the P-type region forms a first doping layer, the portion located in the N-type region forms a second doping layer, and the portion located in the isolation region forms the isolation layer comprises:

[0026] forming a first mask layer on the intrinsic semiconductor material layer;

[0027] Selectively removing a portion of the first mask layer corresponding to the P-type region;

[0028] Using a diffusion process, doping a portion of the intrinsic semiconductor material layer located on the P-type region to form a first doping layer;

[0029] removing the remaining first mask layer;

[0030] forming a second mask layer on the intrinsic semiconductor material layer and the first doped layer;

[0031] Selectively removing a portion of the second mask layer corresponding to the N-type region;

[0032] Using a diffusion process, doping a portion of the intrinsic semiconductor material layer located on the N-type region to form a second doping layer;

[0033] The remaining second mask layer is removed.

[0034] In one embodiment, before forming the intrinsic semiconductor material layer covering the first surface, the method further includes:

[0035] forming a first passivation layer on the first surface of the substrate and a second passivation layer on the second surface;

[0036] The first intrinsic semiconductor material layer is formed on the first passivation layer.

[0037] In one embodiment, before selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region, respectively, a protective layer is formed on the second passivation layer of the substrate.

[0038] After selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region respectively, the protective layer is removed.

[0039] In one embodiment, an aluminum oxide layer and an anti-reflection layer are formed on the second passivation layer.

[0040] The above-mentioned back contact battery is provided with a transparent conductive layer covering the first doping layer, the isolation layer and the second doping layer, and an isolation groove is provided corresponding to the isolation layer, so that the conductive layers corresponding to the first doping layer and the second doping layer are disconnected, and then the electrodes are respectively provided on the transparent conductive layers corresponding to the first doping layer and the second doping layer, thereby avoiding direct ohmic contact between the electrodes and the first doping layer and the second doping layer. Moreover, the conductive layer forms a good ohmic contact with the first doping layer and the second doping layer, so that cheap metals can be used on the conductive layer to make electrodes, such as aluminum paste, silver copper paste, copper paste, etc., thereby reducing the cost of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a back contact battery provided by an embodiment of the present invention;

[0042] Figure 2 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 1 ;

[0043] Figure 3 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 2 ;

[0044] Figure 4 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 3 ;

[0045] Figure 5 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 4 ;

[0046] Figure 6 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 5 ;

[0047] Figure 7 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 6 ;

[0048] Figure 8 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 7 ;

[0049] Fig. 9 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 8 ;

[0050] Fig.10 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 9 ;

[0051] Fig.11 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 .

[0052] Explanation of the accompanying drawings: 1. substrate; 5. first doped layer; 6. second doped layer; 7. isolation layer; 8. transparent conductive layer; 9. isolation groove; 10. electrode; 11. first passivation layer; 12. protective layer; 13. intrinsic silicon layer; 14. first mask layer; 15. second mask layer; 17. aluminum oxide layer; 18. anti-reflection layer; 19. second passivation layer. DETAILED DESCRIPTION

[0053] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0054] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0058] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0059] On the one hand, see Figure 1 An embodiment of the present invention provides a back-contact battery, including a substrate 1, the substrate 1 has a first surface and a second surface opposite to each other, the first surface is provided with an N-type region, an isolation region and a P-type region alternately distributed, the isolation region is located between the N-type region and the P-type region; a first doped layer 5 is located in the P-type region; an isolation layer 7 is located in the isolation region; a second doped layer 6 is located in the N-type region; a transparent conductive layer 8 is covered on the first doped layer 5, the second doped layer 6 and the isolation layer 7, the transparent conductive layer 8 is provided with an isolation groove 9 penetrating therethrough, and the isolation groove 9 is arranged corresponding to the isolation region; electrodes 10 are respectively arranged on the transparent conductive layer 8 covering the first doped layer 5 and the second doped layer 6.

[0060] The substrate 1 can be an N-type substrate or a P-type substrate. The first surface of the substrate 1 corresponds to the backlight surface of the back contact battery, and the second surface of the substrate 1 corresponds to the light-facing surface of the back contact battery. Therefore, the second surface can be a plane, or the second surface is a velvet surface. Since the velvet surface has a light trapping effect, more light can be refracted into the substrate 1 to be absorbed and utilized, which can improve the photoelectric conversion efficiency of the back contact battery.

[0061] The back contact battery of this embodiment is provided with a transparent conductive layer 8 covering the first doping layer 5, the isolation layer 7 and the second doping layer 6, and the isolation groove 9 is provided corresponding to the isolation layer 7, so that the transparent conductive layer 8 corresponding to the first doping layer 5 and the second doping layer 6 is disconnected, and then the electrodes 10 are respectively provided on the transparent conductive layer 8 corresponding to the first doping layer 5 and the second doping layer 6, so that the direct ohmic contact between the electrode 10 and the first doping layer 5 and the second doping layer 6 is avoided. Moreover, the transparent conductive layer 8 forms a good ohmic contact with the first doping layer 5 and the second doping layer 6, so that the electrode 10 can be made of cheap metal on the transparent conductive layer 8, such as aluminum paste, silver copper paste, copper paste, etc., to reduce the cost of the back contact battery.

[0062] In one embodiment, the first doping layer 5, the isolation layer 7, and the second doping layer 6 of the back contact battery are an integrated structure. Since the first doping layer 5, the isolation layer 7, and the second doping layer 6 are an integrated structure, they can be deposited at one time, which can simplify the deposition process of the back contact battery, thereby reducing the production cost of the battery.

[0063] In one embodiment, the isolation layer 7 is intrinsic silicon. Since intrinsic silicon has good electrical isolation, it can completely isolate the first doped layer 5 and the second doped layer 6, ensuring that the back contact battery has good electrical performance. Moreover, since the first doped layer 5, the isolation layer 7 and the second doped layer 6 are an integrated structure, the isolation layer 7 is made of intrinsic silicon. It can be that the intrinsic silicon is first deposited on the substrate 1, and then the intrinsic silicon in the N-type region and the P-type region is doped to form the first doped layer 5 and the second doped layer 6, which simplifies the molding steps of the back contact battery and reduces the cost of the back contact battery.

[0064] In one embodiment, the materials of the first doping layer 5 and the second doping layer 6 are doped polysilicon with opposite electrical properties, and the material of the isolation layer 6 is intrinsic polysilicon. Since the first doping layer 5, the isolation layer 7 and the second doping layer 6 are an integrated structure, they are all intrinsic silicon at the beginning, and the intrinsic silicon of the P-type region and the N-type region is doped in turn. In the process of forming the first doping layer 5, a B source is first used for high-temperature diffusion, and then annealing is performed. In the process of annealing, the material of the intrinsic silicon is changed to polysilicon, so the material of the isolation layer 7 is changed to intrinsic polysilicon, and the material of the first doping layer 5 becomes doped polysilicon. The intrinsic silicon located in the N region is also changed to polysilicon, and the doping is subsequently performed to form doped polysilicon with opposite electrical properties to the P-type region, such as using a P source for doping.

[0065] In one embodiment, the transparent conductive layer 8 is a TCO layer, and the material of the TCO layer can be ITO, ZnO or FTO, etc. The TCO layer has good electrical transmission characteristics. The TCO layer is provided so that carriers can be collected and conducted in time, thereby reducing the carrier recombination rate. The TCO layer has good ohmic contact with the first doped layer 5 of the P-type region, so that it is convenient to use aluminum paste, silver copper paste, copper paste, etc. to make the electrode 10.

[0066] In one embodiment, the first surface and the second surface of the substrate 1 are respectively formed with a first passivation layer 11 and a second passivation layer 19, the first passivation layer 11 is formed on the substrate 1, and the first doping layer 5, the isolation layer 7 and the second doping layer 6 are formed on the first passivation layer. Providing the passivation layer can repair the surface of the substrate 1, reduce the surface state density of the substrate 1, and reduce the surface recombination rate of the substrate 1.

[0067] An aluminum oxide layer 17 and an anti-reflection layer 18 are also formed on the second passivation layer 19. The aluminum oxide layer 17 can resist ultraviolet attenuation, and the anti-reflection layer 18 can reduce the reflection of light, thereby increasing the absorption of light by the back contact cell.

[0068] On the other hand, see Figures 2 to 11 An embodiment of the present invention provides a method for preparing a back contact battery, the method comprising:

[0069] A substrate 1 is provided, the substrate 1 having a first surface and a second surface opposite to each other, the first surface being provided with N-type regions, isolation regions and P-type regions alternately distributed, the isolation region being located between the N-type region and the P-type region. The material, structure and conductivity type of the substrate 1 can be referred to above.

[0070] A first doping layer 5 is formed in the P-type region; an isolation layer 7 is formed in the isolation region; and a second doping layer 6 is formed in the N-type region. The first doping layer 5 and the second doping layer 6 have opposite electrical conductivity.

[0071] A transparent conductive layer 8 is formed to cover the first doping layer 5 , the isolation layer 7 and the second doping layer 6 , and an isolation groove 9 is formed penetrating the transparent conductive layer 8 . The isolation groove 9 is arranged corresponding to the isolation layer 7 .

[0072] The electrode 10 is formed on the transparent conductive layer 8 covering the first doping layer 5 and the second doping layer 6 .

[0073] In practical applications, a chemical vapor deposition process may be used to form an intrinsic semiconductor material layer on the first surface of the substrate 1, and then the intrinsic semiconductor material layer is doped to obtain a doped semiconductor layer. Then, the portion of the doped semiconductor layer located in the isolation region and the N-type region is selectively removed, and the remaining portion of the P region forms a first doped layer 5. Then, a chemical vapor deposition process is used to form another layer of intrinsic semiconductor material on the first doped layer 5. Then, the intrinsic semiconductor material layer located on the first doped layer 5 is removed, and a mask layer is set on the intrinsic semiconductor material layer located in the isolation region and the first doped layer 5, and the intrinsic semiconductor material layer located in the N-type region is doped to form a second doped layer 6. After removing the mask layer, the portion located in the isolation region is the isolation layer 7.

[0074] Alternatively, a chemical vapor deposition process may be firstly used on the first surface of the substrate 1 to form a first passivation layer and an intrinsic semiconductor material layer covering the first surface, and a diffusion process may be used to selectively dope the portions of the intrinsic semiconductor material layer located in the P-type region and the N-type region, respectively, so that the portion located in the P-type region forms a first doped layer 5, the portion located in the N-type region forms a second doped layer 6, and the intrinsic semiconductor material layer located in the isolation region forms an isolation layer 7.

[0075] In practical applications, such as Figures 3 to 6As shown, a chemical vapor deposition process is used to first form a first passivation layer 11 and an intrinsic semiconductor material layer 13 covering the first surface, and then a first mask layer 14 is formed on the intrinsic semiconductor material layer, and the portion of the first mask layer 14 corresponding to the P-type region is selectively removed, and a diffusion process is used to dope the portion of the intrinsic semiconductor material layer located on the P-type region to form a first doping layer 5, and the remaining first mask layer 14 is removed. A second mask layer 15 is formed on the intrinsic semiconductor material layer and the first doping layer 5, and the portion of the second mask layer 15 corresponding to the N-type region is selectively removed, and a diffusion process is used to dope the portion of the intrinsic semiconductor material layer located on the N-type region to form a second doping layer 6, and the remaining second mask layer 15 is removed, thereby forming a first doping layer 5, an isolation layer 7, and a second doping layer 6 of an integrated structure.

[0076] Among them, the first mask layer 14 completely covers all the P-type regions, N-type regions and isolation regions on the first surface of the substrate 1, that is, completely covers the intrinsic semiconductor material layer. The material of the first mask layer 14 can be any film layer with a masking function, such as silicon nitride and silicon oxide. When selectively removing the first mask layer 14 and the partial area of ​​the second mask layer 15, a photolithography or etching process can be used. After selective doping, a first doped silicon glass layer is formed on the intrinsic silicon semiconductor material layer. The first doped silicon glass can be removed by hydrofluoric acid. When removing the first doped silicon glass, the mask layer made of silicon oxide or silicon nitride can be removed together, thereby simplifying the manufacturing process of the back contact battery. After doping the N-type region, a second doped silicon glass layer will also be formed on the intrinsic semiconductor material layer. The removal of the second doped silicon glass layer and the second mask layer 15 is the same as the removal of the first doped silicon glass layer and the first mask layer 14.

[0077] In one embodiment, before forming an intrinsic semiconductor material layer on the substrate 1, the substrate 1 is first cleaned, and then the substrate 1 is textured. The substrate 1 is cleaned to remove organic matter and metal impurities on the surface of the substrate 1 and eliminate mechanical damage to the surface of the silicon wafer. At the same time, the surface of the substrate 1 is textured to reduce the reflection of sunlight on the surface of the substrate 1 and increase the absorption of light energy.

[0078] Then, a first passivation layer 11 and a second passivation layer 19 are formed on the first surface of the substrate 1 . The first passivation layer 11 and the second passivation layer 19 can respectively reduce the surface state density of the first surface and the second surface, thereby reducing the surface recombination rate of the substrate 1 .

[0079] In order to avoid doping the second surface of the substrate 1 when forming the first doping layer 5 and the second doping layer 6, a protective layer is formed on the second passivation layer 19 of the substrate before selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region, respectively, so as to avoid entering the interior of the substrate 1 through the second surface of the base when forming the first doping layer 5 and the second doping layer 6, and also to protect the second passivation layer 19 and avoid loss of the second passivation layer 19 when removing the mask layer. The protective layer 12 can be made of a material that can play a protective role, such as intrinsic silicon.

[0080] After selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region, respectively, the protective layer is removed, and then an aluminum oxide layer 17 and an anti-reflection layer 18 may be formed on the second passivation layer 19 .

[0081] In other embodiments, the protective layer 12 may not be formed on the second passivation layer 19, but after the first doping layer 5 and the second doping layer 6 are formed, the second passivation layer 19 is removed, and then a passivation layer, an aluminum oxide layer and an anti-reflection layer are sequentially formed on the second surface of the substrate 1, or a passivation layer, an aluminum oxide layer 17 and an anti-reflection layer 18 are sequentially formed directly on the second passivation layer 19. Since the passivation layer is formed on the second surface of the substrate 1, the surface state density of the second surface of the substrate 1 can be reduced, and the surface recombination rate of the substrate 1 can be reduced.

[0082] like Figures 2 to 11 As shown, the present invention also provides an embodiment to illustrate the manufacturing method and performance of the back contact battery provided by the embodiment of the present invention.

[0083] The first step is to clean the silicon wafer, for example, in a tank cleaning machine.

[0084] In the second step, a first passivation layer 11 and a second passivation layer 19 are deposited on the first side and the second side of the silicon wafer, respectively. The first passivation layer 11 and the second passivation layer 19 can be formed by PECVD or LPCVD thermal oxidation, such as Figure 2 shown.

[0085] In the third step, an intrinsic silicon layer 13 is deposited on the first passivation layer 11, and a protective layer 12 is deposited on the second passivation layer 19. The protective layer 12 and the intrinsic silicon layer 13 are both made of intrinsic silicon and can be formed simultaneously by LPCVD. Figure 3 shown.

[0086] Step 4: deposit a first mask layer 14 on the intrinsic silicon layer 13. The first mask layer 14 is grown by PECVD. The material of the first mask layer 14 is silicon nitride. Figure 4 shown.

[0087] Step 5: Use a laser process to partially remove the first mask layer 14, removing the portion of the first mask layer 14 located in the P-type region.

[0088] In the sixth step, the intrinsic silicon in the P-type region is doped by high-temperature diffusion, so that the intrinsic silicon in the P-type region becomes a P-type polysilicon layer, forming a first doped layer 5, the first doped layer 5 is made of P-type polysilicon, and the intrinsic silicon in the isolation region and the N-type region is also changed into polysilicon. The intrinsic polysilicon covered by the first mask layer 14 maintains the characteristics of intrinsic polysilicon.

[0089] In the seventh step, HF solution is used to remove the borosilicate glass layer formed on the P-type polysilicon after the above doping, and the first mask layer 14 is removed at the same time.

[0090] In the eighth step, a second mask layer 15 is deposited on the intrinsic silicon layer 13 and the first doped layer 5. The second mask layer 15 is grown by PECVD. The material of the second mask layer 15 is silicon nitride. Figure 5 shown.

[0091] In the ninth step, a laser process is used to partially remove the second mask layer 15, and the portion of the second mask layer 15 located in the N-type region is removed.

[0092] In the tenth step, the intrinsic silicon in the N-type region is doped by high temperature diffusion, so that the intrinsic silicon in the N-type region becomes N-type polysilicon, that is, the second doped layer 6 is N-type polysilicon. The intrinsic polysilicon and P-type polysilicon covered by the second mask layer 15 still maintain the previous characteristics. The intrinsic silicon between the first doped layer 5 and the second doped layer 6 is formed into an isolation layer 7.

[0093] In the eleventh step, the phosphosilicate glass layer formed on the N-type polysilicon after the doping is removed by using HF solution, and the second mask layer 15 is removed at the same time. Figure 6 shown.

[0094] In the twelfth step, the protective layer 12 on the second passivation layer 19 on the second surface is removed. Figure 7 shown.

[0095] In the thirteenth step, an aluminum oxide layer 17 and an anti-reflection layer 18 are sequentially deposited on the second passivation layer 19, such as Figure 8 shown.

[0096] In the fourteenth step, a TCO layer is deposited on the first doped layer 5, the isolation layer 17 and the second doped layer 6 using a PVD device. The TCO layer serves as a transparent conductive layer 8. Fig. 9 shown.

[0097] In the fifteenth step, a portion of the TCO layer on the isolation layer 7 is removed by laser, and an isolation groove 9 is formed on the TCO layer to isolate the TCO layer on the P-type polysilicon layer from the TCO layer on the N-type polysilicon layer. Fig.10 shown.

[0098] In the sixteenth step, metal electrodes 10 are printed on the TCO layers on the first doping layer 5 and the second doping layer 6, respectively, and sintered. Fig.11 shown.

[0099] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A back contact battery, characterized in that: include: A substrate, the substrate having a first surface and a second surface opposite to each other, the first surface being provided with N-type regions, isolation regions and P-type regions that are alternately distributed, and the isolation region being located between the N-type region and the P-type region; A first doped layer, located in the P-type region; An isolation layer, located in the isolation area; A second doped layer, located in the N-type region; a transparent conductive layer covering the first doped layer, the isolation layer and the second doped layer, wherein the transparent conductive layer is provided with an isolation groove penetrating therethrough, and the isolation groove is provided corresponding to the isolation layer; The electrodes are respectively arranged on the transparent conductive layer covering the first doping layer and the second doping layer.

2. The back contact cell according to claim 1, characterized in that The first doping layer, the isolation layer and the second doping layer are an integrated structure.

3. The back contact cell according to claim 1, characterized in that The materials of the first doping layer and the second doping layer are doped polysilicon with opposite electrical properties, and the material of the isolation layer is intrinsic polysilicon.

4. The back contact cell according to claim 1, characterized in that A first passivation layer and a second passivation layer are formed on the first surface and the second surface of the substrate, respectively. The first passivation layer is formed on the substrate, and the first doping layer, the isolation layer and the second doping layer are formed on the first passivation layer.

5. The back contact cell according to claim 4, characterized in that An aluminum oxide layer and an anti-reflection layer are also formed on the second passivation layer.

6. A method for preparing a back contact battery, characterized in that: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface being provided with N-type regions, isolation regions and P-type regions distributed alternately, the isolation region being located between the N-type region and the P-type region; A first doping layer formed in the P-type region; an isolation layer formed in the isolation region; A second doping layer formed in the N-type region; forming a transparent conductive layer covering the first doped layer, the isolation layer and the second doped layer, and forming an isolation groove penetrating the transparent conductive layer, wherein the isolation groove is arranged corresponding to the isolation layer; An electrode is formed on the transparent conductive layer covering the first doping layer and the second doping layer.

7. A method for preparing a back contact battery according to claim 6, characterized in that: forming an intrinsic semiconductor material layer covering the first surface; A diffusion process is adopted to selectively dope the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region, so that the portion of the intrinsic semiconductor material layer located in the P-type region forms a first doped layer, the portion located in the N-type region forms a second doped layer, and the portion located in the isolation region forms the isolation layer.

8. The method for preparing a back contact battery according to claim 7, characterized in that: The step of selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region respectively by using a diffusion process so that the portion of the intrinsic semiconductor material layer located in the P-type region forms a first doping layer, the portion located in the N-type region forms a second doping layer, and the portion located in the isolation region forms the isolation layer comprises: forming a first mask layer on the intrinsic semiconductor material layer; Selectively removing a portion of the first mask layer corresponding to the P-type region; Using a diffusion process, doping a portion of the intrinsic semiconductor material layer located on the P-type region to form a first doping layer; removing the remaining first mask layer; forming a second mask layer on the intrinsic semiconductor material layer and the first doped layer; Selectively removing a portion of the second mask layer corresponding to the N-type region; Using a diffusion process, doping a portion of the intrinsic semiconductor material layer located on the N-type region to form a second doping layer; The remaining second mask layer is removed.

9. The method for preparing a back contact battery according to claim 7, characterized in that: Before forming the intrinsic semiconductor material layer covering the first surface, the method further includes: forming a first passivation layer on the first surface of the substrate and a second passivation layer on the second surface; The first intrinsic semiconductor material layer is formed on the first passivation layer.

10. A method for preparing a back contact battery according to claim 9, characterized in that: Before selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region respectively, forming a protective layer on the second passivation layer of the substrate, After selectively doping the portions of the intrinsic semiconductor material layer located in the N-type region and the P-type region respectively, the protective layer is removed.

11. The method for preparing a back contact battery according to claim 9, characterized in that: An aluminum oxide layer and an anti-reflection layer are formed on the second passivation layer.

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