Display device, wearable electronic device, and method of manufacturing display device

Abstract

The invention relates to a display device, a wearable electronic device, and a method of manufacturing the display device. The display device includes: a base layer including a groove surrounded by a protrusion disposed in a boundary region between a plurality of sub-pixels; the reflecting electrode is arranged on the base body layer in the groove; a planarization pattern disposed on the reflective electrode in the groove; an anode electrode disposed on the planarization pattern and contacting the reflective electrode; and a light emitting layer disposed on the anode electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0143212 filed in the Korean Intellectual Property Office on October 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, a wearable electronic device, and a method of manufacturing the display device. Background Art

[0004] An organic light emitting diode (OLED) is an active light emitting display device having the following advantages: not only having a wide viewing angle and excellent contrast, but also being able to be driven with a low voltage, being lightweight and thin, and having a fast response speed. Summary of the invention

[0005] Embodiments may provide a display device having improved light output efficiency, a wearable electronic device, and a method of manufacturing the display device.

[0006] According to an embodiment of the present disclosure, a display device includes: a base layer, including a groove surrounded by a protrusion, wherein the protrusion is arranged in a boundary area between a plurality of sub-pixels; a reflective electrode, which is arranged on the base layer in the groove; a planarization pattern, which is arranged on the reflective electrode in the groove; an anode electrode, which is arranged on the planarization pattern and contacts the reflective electrode; and a light-emitting layer, which is arranged on the anode electrode.

[0007] A portion of the reflective electrode may cover a side surface of the protrusion, and an upper surface of the portion of the reflective electrode, an upper surface of the planarization pattern, and an upper surface of the protrusion may be positioned on the same plane.

[0008] The upper surface of the portion of the reflective electrode, the upper surface of the planarization pattern, and the upper surface of the protrusion may be simultaneously formed through a polishing process.

[0009] The anode electrode may be directly disposed on the portion of the reflective electrode and the planarization pattern, and may directly contact the portion of the reflective electrode.

[0010] The reflective electrode may include a first layer, a second layer, and a third layer that are sequentially stacked, each of the first layer and the third layer may include a transparent conductive material, and the second layer may include a metal material.

[0011] The second layer may include silver.

[0012] The anode electrode may directly contact the second layer of the reflective electrode.

[0013] The light emitting layer may directly contact the base layer in the boundary region between the plurality of sub-pixels.

[0014] The planarization pattern may include an inorganic material, and the anode electrode may include a transparent conductive material.

[0015] The reflective electrode may surround the planarization pattern in a plan view, and the anode electrode may cover the reflective electrode.

[0016] The display device may further include: a buffer pattern disposed in the groove below the reflective electrode.

[0017] The display device may further include: a pixel defining layer disposed on the base layer in the boundary region between the plurality of sub-pixels; and a protrusion pattern disposed on the pixel defining layer and having a width that becomes wider toward an upper portion.

[0018] The display device may further include: a plurality of grooves formed in the base layer in the boundary region, and the plurality of grooves may be separated from each other.

[0019] According to an embodiment of the present disclosure, a wearable electronic device includes: a display panel that emits light; and at least one lens disposed on the display panel. The display panel includes: a base layer that includes a groove surrounded by a protrusion, the protrusion being disposed in a boundary region between a plurality of sub-pixels; a reflective electrode disposed on the base layer in the groove; a planarization pattern disposed on the reflective electrode in the groove; an anode electrode disposed on the planarization pattern and contacting the reflective electrode; and a light-emitting layer disposed on the anode electrode.

[0020] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a groove in a base layer, the groove being surrounded by a protrusion, the protrusion being arranged in a boundary region between a plurality of sub-pixels; forming a reflective electrode layer on the base layer; forming a planarization layer on the reflective electrode layer; removing a portion of the reflective electrode layer on the protrusion and a portion of the planarization layer on the protrusion by a polishing process; forming an anode electrode on the base layer and the planarization layer; and forming a light-emitting layer on the anode electrode.

[0021] The forming the groove in the base layer may include simultaneously forming the groove and a via hole in the base layer using a half-tone mask.

[0022] The forming the groove in the base layer may include: forming the base layer; and forming the groove in the base layer.

[0023] The reflective electrode layer may be separated in the boundary region between the plurality of sub-pixels by the polishing process to form a reflective electrode, the reflective electrode being disposed in the groove.

[0024] The forming of the reflective electrode layer may include sequentially forming a first layer, a second layer, and a third layer on the base layer, each of the first layer and the third layer may include a transparent conductive material, and the second layer may include a metal material.

[0025] The second layer may include silver.

[0026] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0027] In the display device and the wearable electronic device according to the embodiments of the present disclosure, the reflective electrode may be disposed or buried in the groove of the base layer (or via layer), and may be formed by a polishing process instead of a dry etching process. In this case, the reflective electrode may include silver having a reflectivity higher than that of aluminum, and the light output efficiency of the sub-pixel may be improved.

[0028] In addition, the planarization pattern may be disposed on the reflective electrode in the groove of the base layer, thereby preventing damage (eg, scratches) to the reflective electrode during the CMP process.

[0029] The method of manufacturing a display device according to an embodiment of the present disclosure may form a reflective electrode disposed or buried in a groove of a base layer through a polishing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features of the embodiments of the present disclosure will become more apparent by further describing in detail non-limiting embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram showing an embodiment of a display device;

[0032] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any one of the sub-pixels;

[0033] Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of a sub-pixel;

[0034] Figure 4 It is shown Figure 1 A plan view of an embodiment of a display panel;

[0035] Figure 5 It is shown Figure 4 an exploded perspective view of a portion of a display panel;

[0036] Figure 6 It is shown Figure 5 A plan view of an embodiment of any one of the pixels;

[0037] Figure 7 is an example of a pixel along the Figure 6 A cross-sectional view taken along line II';

[0038] Figure 8 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light-emitting element layer in any one of the first to third sub-pixels;

[0039] Fig. 9 It is shown Figure 8 A plan view of an embodiment of a light emitting element layer;

[0040] Fig.10 is a diagram showing a comparative example of a pixel Figure 6 A cross-sectional view taken along line II';

[0041] Fig.11 It is shown that the Figure 7 A cross-sectional view of a comparative example of a light emitting element layer in any one of the first to third sub-pixels;

[0042] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E is a cross-sectional view showing a method of manufacturing a display device according to an embodiment;

[0043] Fig.12F and Figure 12G It is shown that the formation Fig. 12A A cross-sectional view of a method for a via layer;

[0044] Fig.13 is an example of a pixel along the Figure 6 A cross-sectional view taken along line II';

[0045] Fig.14 is an example of a pixel along the Figure 6 A cross-sectional view taken along line II';

[0046] Fig.15 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light emitting structure in any one of the first light emitting element to the third light emitting element;

[0047] Fig.16 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light emitting structure in any one of the first light emitting element to the third light emitting element;

[0048] Fig.17 It is shown Figure 5 A plan view of an embodiment of any one of the pixels;

[0049] Fig.18 It is shown Figure 5 A plan view of an embodiment of any one of the pixels;

[0050] Fig.19 is a block diagram illustrating an embodiment of a display system;

[0051] Fig. 20 It is shown Fig.19 A perspective view of an example application of the display system; and

[0052] Fig.21 It is shown Fig. 20 Illustration of a head mounted display device worn by a user. DETAILED DESCRIPTION

[0053] Hereinafter, the preferred embodiments according to the present disclosure are described in more detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to obscure the subject matter of the present disclosure. In some embodiments, the present disclosure may be implemented in other forms without being limited to the embodiments described herein. However, the embodiments described herein are provided to be described in sufficient detail so that those skilled in the art to which the present disclosure belongs can easily realize the technical spirit of the present disclosure.

[0054] Throughout the specification, when one part is "connected" to another part, the situation includes not only the situation that the part is "directly connected", but also the situation that the part is "indirectly connected" and another element is between them. The same figure mark always refers to the same element, and its repetitive description may not be provided. In some embodiments, in order to effectively describe the technical content, the thickness, proportion and size of the elements are exaggerated in the drawings. As used herein, the term "and / or" includes any combination and all combinations that can be defined by the relevant configuration.

[0055] The terms used herein are used to describe specific embodiments and are not intended to limit the present disclosure. Throughout the specification, unless otherwise stated, in the case of a certain part "including", the situation refers to that the part can also include another component without excluding another component. "At least any one of X, Y and Z" and "at least any one of the group consisting of X, Y and Z" can be interpreted as any combination of two or more of X, Y and Z (for example, XYZ, XY, YZ and XZ). Here, "and / or" includes all combinations of one or more in the corresponding configuration. Unless otherwise stated, the term in the singular includes plural forms. For example, unless the context clearly indicates otherwise, "one", "one (kind / person)" and "the (the)" are also intended to include plural forms.

[0056] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized."

[0057] As used herein, expressions such as “at least one of,” “one of,” “selected from,” and “selected from among,” when preceding (following) a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, the expressions “at least one of a to c” and “at least one of a, b, and c” may indicate only a, only b, only c, both a and b (e.g., a and b exist at the same time), both a and c (e.g., a and c exist at the same time), both b and c (e.g., b and c exist at the same time), all of a, b, and c, or variations thereof.

[0058] The term "and / or" includes all combinations of one or more of the associated listed elements.

[0059] In the present application, when a layer, film, region or plate is referred to as being "on" another layer, film, region or plate or "in the "upper portion" of another layer, film, region or plate, the layer, film, region or plate may not only be "directly on" the other layer, film, region or plate, but also there may be intervening layers, films, regions or plates. In contrast, when a layer, film, region or plate is referred to as being "in the "lower portion" of another layer, film, region or plate, the layer, film, region or plate may not only be directly below the other layer, film, region or plate, but also there may be intervening layers, films, regions or plates. In some embodiments, it will be understood that when a component is referred to as being "on" another component, the component may be provided above the other component, or may also be provided below the other component. It will be understood that the terms “include, includes, including,” “comprise, comprises, comprising,” and / or “has, having, have” when used in this specification specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0060] As used herein, the term "may" will be understood to refer to "one or more embodiments of the present disclosure," some of which include the described elements, and some of which exclude the elements and / or include alternative elements. Similarly, alternative language such as "or" refers to "one or more embodiments of the present disclosure" that each include the corresponding listed items.

[0061] Unless otherwise defined, all terms (including chemical terms, technical terms and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and the terms will not be interpreted in an idealized or overly formalized sense.

[0062] As used herein, the phrase "consisting essentially of" means that any additional components will not substantially affect the chemical, physical, optical, or electrical properties of the semiconductor film.

[0063] As used herein, the phrase “on a plane” or “plan view” means observing a target portion from the top, and the phrase “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0064] In the present disclosure, "does not include one or any "component"", "excludes one or any "component"" and / or "does not contain..."a "component"", etc. means that the "component" is not added, selected or used as a component in the composition, but due to other impurities and / or external factors, less than an appropriate amount of the "component" may still be included.

[0065] Here, terms such as first and second may be used to describe one or more suitable components, but these components are not limited to these terms. These terms are used to distinguish one component from another component. Therefore, a first component may refer to a second component within the scope of the scope disclosed herein.

[0066] For the purpose of description, spatial relative terms such as "below" and / or "on" may be used to describe the relationship between an element or feature and another element (or elements) or another feature (or features) as shown in the drawings. In addition to the directions depicted in the drawings, spatial relative terms are also intended to include other directions in use, operation and / or manufacture. For example, if the device shown in the drawings is turned upside down (e.g., when the device shown in the drawings is turned upside down), the elements or features depicted as being positioned "below" other elements or features are positioned in the direction "on" the other elements or features. Therefore, in some embodiments, the term "below" may include both upper and lower directions (e.g., there are both upper and lower directions). In some embodiments, the device may face other directions (e.g., rotated 90 degrees or in other directions), and the spatial relative terms used herein are therefore interpreted accordingly.

[0067] Various embodiments are described with reference to the accompanying drawings that schematically illustrate idealized embodiments. Therefore, it is expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, and should be construed to include variations in shape that occur, for example, due to manufacturing. As used herein, the shapes shown in the accompanying drawings may not show the actual shape of an area of ​​the device, and the present embodiments are not limited thereto.

[0068] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0069] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0070] refer to Figure 1 , the display device 100 may include a display panel 110 (or a display unit), a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0071] The display panel 110 (hereinafter, also referred to as the display panel DP) includes subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm, where m is an integer greater than 0. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn, where n is an integer greater than 0.

[0072] Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, or yellow). Two or more sub-pixels among the sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG. , three sub-pixels can constitute one pixel PXL.

[0073] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing at which a data signal is applied, and the like.

[0074] In an embodiment, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0075] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may include two or more physically and / or logically divided drivers, and the drivers may be disposed on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. As described above, according to the embodiment, the gate driver 120 may be disposed around the display panel 110 in various shapes.

[0076] The data driver 130 is connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 receives the image data DATA and the data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0077] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP may generate light of a brightness corresponding to the data signal. Therefore, an image is displayed in the display panel 110.

[0078] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0079] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0080] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS may be provided to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than that of the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0081] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such a reference voltage.

[0082] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0083] Controller 150 may convert input image data IMG to make it suitable for display device 100 or display panel 110 and output image data DATA. In an embodiment, controller 150 may output image data DATA after rearranging input image data IMG to fit sub-pixels SP of a row unit.

[0084] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be embedded in one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be embedded in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally divided components in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0085] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0086] The controller 150 may control various operations of the display device 100 according to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 according to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0087] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any one of the sub-pixels of FIG. Figure 2 In the Figure 1 The sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0088] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0089] The light emitting element LD is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. Figure 1 The first power supply voltage node VDD is connected to the second power supply voltage node VSSN. Figure 1 A node of a second power supply voltage VSS.

[0090] The anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0091] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 an i-th emission control line ELi among the first to m-th emission control lines EL1 to ELm, and Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD according to signals received through the signal lines.

[0092] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0093] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0094] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN through the light emitting element LD to the second power supply voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light emitting element LD may generate light of brightness corresponding to the data signal.

[0095] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0096] refer to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0097] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared with the i-th emission control line ELi, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0098] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 , and first and second capacitors C1 and C2 .

[0099] The first transistor T1 is connected between the first power supply voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2, and thus the first transistor T1 may be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0100] The second transistor T2 is connected between the jth data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1, and thus the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0101] The third transistor T3 is connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2, and thus the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0102] The fourth transistor T4 is connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub emission control line SEL2, and thus the fourth transistor T4 may be turned on in response to an emission control signal of the second sub emission control line SEL2.

[0103] The fifth transistor T5 is connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. In an embodiment, the initialization voltage may be Figure 1 In other embodiments, the initialization voltage may be provided by the display device 100 (see Figure 1 ) is provided by an external device. A gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, and thus the fifth transistor T5 may be turned on in response to a gate signal of the third sub-gate line SGL3.

[0104] The sixth transistor T6 is connected between the first power supply voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub emission control line SEL1, and thus the sixth transistor T6 may be turned on in response to the emission control signal of the first sub emission control line SEL1.

[0105] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power supply voltage node VDDN and the second node N2.

[0106] As described above, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6, and a first capacitor C1 and a second capacitor C2. However, the embodiment is not limited thereto. The sub-pixel circuit SPC may be implemented as any of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to an embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may change.

[0107] The first transistor T1 to the sixth transistor T6 may be a P-type transistor. Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). However, the embodiment is not limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced by an N-type transistor.

[0108] In an embodiment, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0109] The light emitting element LD may include an anode electrode AE, a cathode electrode CE and a light emitting layer. The light emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted through the j-th data line DLj is stored in the second capacitor C2, when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to be low, the fourth transistor T4 and the sixth transistor T6 may be turned on. In addition, the first transistor T1 may be turned on according to the data signal stored in the second capacitor C2, and thus current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light of corresponding brightness according to the amount of the flowing current.

[0110] Figure 4 It is shown Figure 1 A plan view of an embodiment of a display panel.

[0111] refer to Figure 4 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0112] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0113] When the display panel DP is used as a display screen of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be positioned very close to the user's eyes. In this case, a relatively high integration of sub-pixels SP is required. In order to improve the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (refer to FIG. 1 ) including a display panel DP formed on a substrate SUB (e.g., a silicon substrate) Figure 1 ) can be called a silicon-based OLED (OLEDoS) display device.

[0114] The sub-pixels SP are disposed in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0115] Two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL.

[0116] Components for controlling the sub-pixel SP may be disposed in the non-display area NDA on the substrate SUB. For example, a line (such as a Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn) may be disposed in the non-display area NDA.

[0117] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA. In an embodiment, Figure 1 The gate driver 120 may be formed in the display panel DP in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. In an embodiment, the temperature sensor 160 may be provided in the non-display area NDA to sense the temperature of the display panel DP.

[0118] The pad PD is disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a signal line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0119] The display panel DP and the display device 100 (refer to Figure 1 ) can be connected to each other through the pads PD. In an embodiment, the pads PD can be connected to each other through the pads PD. Figure 1 The driver integrated circuit DIC provides voltages and signals required for the operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0120] In an embodiment, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible circuit board (e.g., a flexible printed circuit board (FPCB)) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0121] In an embodiment, the display area DA may have various shapes. The display area DA may have various shapes including straight sides and / or curved sides. For example, the display area DA may have shapes such as polygonal, circular, semicircular, and elliptical.

[0122] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable or rollable. In these cases, the display panel DP and / or the substrate SUB may include a material having a flexible property.

[0123] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of a display panel. Figure 5 In the embodiment, for the sake of clarity and simplicity, the display panel DP (see Figure 4 ) and Figure 4 Portions of the display panel DP corresponding to the two pixels PXL1 and PXL2 among the pixels PXL of the display panel DP may be similarly configured.

[0124] refer to Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0125] exist Figure 5 , the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 have a quadrilateral shape when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2, and have sizes equal to each other. However, the embodiment is not limited thereto. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be modified to have various shapes.

[0126] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0127] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In another other embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0128] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least a part of a circuit element, a signal line, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0129] The circuit element may include a sub-pixel circuit SPC (refer to Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer interposed therebetween.

[0130] The signal line of the pixel circuit layer PCL may be connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The signal line may include a gate line, an emission control line, a data line, etc. The signal line may also include a signal line connected to Figure 2 In addition, the signal line may also include a line connected to the first power supply voltage node VDDN. Figure 2 A line to the second power supply voltage node VSSN.

[0131] The light emitting element layer LDL may include an anode electrode AE, a light emitting structure EMS, and a cathode electrode CE. According to an embodiment, the light emitting element layer LDL may not include a pixel defining layer PDL. In other words, the pixel defining layer PDL may be omitted.

[0132] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be connected to a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0133] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining layer PDL may be emission regions corresponding to the first to third subpixels SP1 to SP3, respectively.

[0134] In an embodiment, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0135] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and the like.

[0136] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be completely disposed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of each layer in the light emitting structure EMS may be disconnected or bent at the boundary between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiment is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the portions may be disposed in the opening OP of the pixel defining layer PDL.

[0137] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third subpixels SP1 to SP3. As described above, the cathode electrode CE may be provided as a common electrode for the first to third subpixels SP1 to SP3.

[0138] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag) and magnesium (Mg). However, the material of the cathode electrode CE is not limited thereto.

[0139] It can be understood that one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping with the one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the one of the anode electrodes AE can constitute a light emitting element LD (refer to Figure 2 ). In other words, each of the light emitting elements of the first to third sub-pixels SP1 to SP3 may include an anode electrode AE, a portion of the light emitting structure EMS overlapping the one anode electrode AE, and a portion of the cathode electrode CE overlapping the one anode electrode AE. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light emitting layer of the light emitting structure EMS to form excitons, and when the excitons are transformed from an excited state to a ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light emitting layer. According to the configuration of the light emitting layer, the wavelength range of the generated light may be determined.

[0140] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0141] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (Al x O yThe thin film including aluminum oxide may be positioned on an upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or a lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0142] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0143] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0144] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter the light emitted from the light emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include a plurality of color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of the plurality of color filters CF may pass light of a wavelength range corresponding to the corresponding sub-pixel. For example, the color filter corresponding to the first sub-pixel SP1 may pass red light, the color filter corresponding to the second sub-pixel SP2 may pass green light, and the color filter corresponding to the third sub-pixel SP3 may pass blue light. Depending on the light emitted from the light emitting structure EMS of each sub-pixel, at least a portion of the color filter CF may be omitted.

[0145] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the lenses LS may improve light output efficiency by redirecting light emitted from the light emitting structure EMS to a predetermined path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0146] In an embodiment, compared to the opening OP of the pixel defining layer PDL, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the lens LS of the lens array LA may be offset in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. Specifically, in the central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may be aligned with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In an area adjacent to the non-display area NDA in the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be offset in a plane direction from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in an area adjacent to the non-display area NDA in the display area DA, the opening OP of the pixel defining layer PDL may be misaligned with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. In an area of ​​the display area DA adjacent to the non-display area NDA, light emitted from the light emitting structure EMS can be effectively output in a direction inclined at a predetermined angle relative to the normal direction of the display surface.

[0147] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the layers below the outer coating OC from foreign matter such as dust or moisture. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0148] The cover window CW may be disposed on the outer coating layer OC. The cover window CW is configured to protect a layer disposed below the cover window CW. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect a component disposed below the cover window CW. In other embodiments, the cover window CW may be omitted.

[0149] Figure 6 It is shown Figure 5 A plan view of an embodiment of any one of the pixels of FIG. Figure 6In order to make the description clear and concise, the schematic diagram is shown Figure 5 The remaining pixels may be configured similarly to the first pixel PXL1.

[0150] refer to Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0151] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0152] The first emission area EMA1 may be formed from the light emitting structure EMS (refer to Figure 5 ) may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 5 As described, each emission region may be an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0153] Figure 7 is an example of a pixel along the Figure 6 A cross-sectional view taken along line II'. Figure 8 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light-emitting element layer in any one of the first to third sub-pixels. Fig. 9 It is shown Figure 8 A plan view of an embodiment of a light emitting element layer.

[0154] refer to Figures 7 to 9 , the pixel circuit layer PCL is disposed on the substrate SUB.

[0155] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0156] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (refer to Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for clear and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0157] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0158] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed to be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0159] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region and an insulating material such as a gate insulating layer GI may be disposed between the gate electrode GE and the channel region. The gate electrode GE may include a conductive material.

[0160] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC formed through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC formed through one or more insulating layers.

[0161] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as any one of the transistors of the first subpixel SP1.

[0162] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured similarly to the transistor T_SP1 of the first subpixel SP1.

[0163] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0164] The light emitting element layer LDL is disposed on the pixel circuit layer PCL. The light emitting element layer LDL may include a via layer VIAL, first to third reflective electrodes RE1 to RE3 (or reflective electrodes RE, refer to Figure 8 ), a first planarization pattern PLNP1, a second planarization pattern PLNP2 and a third planarization pattern PLNP3 (or a planarization pattern PLNP, refer to Figure 8 ), the first anode electrode AE1 to the third anode electrode AE3 (or the anode electrode AE, reference Figure 8 ), light emitting structure EMS and cathode electrode CE.

[0165] The via layer VIAL (or substrate layer) may cover the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0166] In an embodiment, the via layer VIAL may include a groove GRV that is recessed from the upper surface of the via layer VIAL and is surrounded by a protrusion SW of the via layer VIAL disposed in a boundary area BDA between the sub-pixels SP1 to SP3. Figure 8 , the protrusion SW may be provided to surround the reflective electrode RE.

[0167] The protrusion SW may be part of the via layer VIAL, but is not limited thereto. For example, the protrusion SW may be formed by a process different from that of the via layer VIAL, or may be a separate component including a material different from that of the via layer VIAL. In this case, the groove GRV may be an area in which the material forming the protrusion SW is removed.

[0168] On the via layer VIAL, the first to third reflective electrodes RE1 to RE3 are respectively disposed in the first to third sub-pixels SP1 to SP3. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element (e.g., the first conductive pattern CP1) disposed in the pixel circuit layer PCL through a connection electrode CCE formed through the via layer VIAL. Each of the first to third reflective electrodes RE1 to RE3 may directly contact a circuit element (e.g., the first conductive pattern CP1) disposed in the pixel circuit layer PCL.

[0169] In an embodiment, each of the first to third reflective electrodes RE1 to RE3 may be disposed in the groove GRV of the via layer VIAL. Figure 8 As shown in , the reflective electrode RE may be disposed on the bottom surface of the groove GRV, and a portion of the reflective electrode RE may cover the side surface of the protrusion SW.

[0170] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors that reflect light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), and an alloy of two or more materials selected therefrom, but the embodiment is not limited thereto.

[0171] In an embodiment, the reflective electrode RE may include a first layer RE_S1, a second layer RE_S2, and a third layer RE_S3, which are sequentially stacked.

[0172] like Figure 8 As shown in, on the bottom surface of the groove GRV of the via layer VIAL, the first layer RE_S1, the second layer RE_S2, and the third layer RE_S3 may be sequentially stacked in the third direction DR3. When the reflective electrode RE covers the side surface of the protrusion SW of the via layer VIAL, the first layer RE_S1, the second layer RE_S2, and the third layer RE_S3 may be sequentially stacked on the side surface of the protrusion SW in a direction perpendicular to the side surface of the protrusion SW (e.g., in the first direction DR1). The end of the first layer RE_S1, the end of the second layer RE_S2, and the end of the third layer RE_S3 may be positioned on the same plane (e.g., positioned on the same plane as the upper surface of the protrusion SW).

[0173] In an embodiment, Fig. 9As shown in FIG. 1 , in a plan view, the first layer RE_S1 may surround the second layer RE_S2 , and the second layer RE_S2 may surround the third layer RE_S3 .

[0174] In an embodiment, each of the first layer RE_S1 and the third layer RE_S3 may include a transparent conductive material, and the second layer RE_S2 may include a metal material. For example, each of the first layer RE_S1 and the third layer RE_S3 may include indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. For example, the second layer RE_S2 may include silver (Ag).

[0175] As will be referred to later Fig. 12C As described, the third layer RE_S3 may prevent damage to the second layer RE_S2 during the process of forming (or patterning) the reflective electrode RE.

[0176] The first to third planarization patterns PLNP1 to PLNP3 are disposed on the first to third reflective electrodes RE1 to RE3 , respectively.

[0177] In an embodiment, each of the first to third planarization patterns PLNP1 to PLNP3 may be disposed in the groove of the via layer VIAL. The first to third planarization patterns PLNP1 to PLNP3 may have a flat surface. The first to third planarization patterns PLNP1 to PLNP3 may planarize the step difference caused by the groove GRV of the via layer VIAL (and the first to third reflective electrodes RE1 to RE3).

[0178] As will be referred to later Fig. 12C As described, the first to third planarization patterns PLNP1 to PLNP3 may prevent damage to the reflective electrodes RE1 to RE3 (particularly, the second layer RE_S2 ) in a process of separating (or patterning) the reflective electrodes RE1 to RE3 from each other.

[0179] In an embodiment, Fig. 9 As shown in FIG. 8 , the planarization pattern PLNP may be surrounded by the reflective electrode RE (or the third layer RE_S3 ).

[0180] The first to third planarization patterns PLNP1 to PLNP3 may include an insulating material. For example, the first to third planarization patterns PLNP1 to PLNP3 may include a silicon oxide (SiO x ) or silicon nitride (SiN x ) of an inorganic material, but the embodiment is not limited thereto.

[0181] In an embodiment, Figure 8As shown in FIG. 1 , the upper surface of the planarization pattern PLNP, the upper surface of the protrusion SW, and the end of the reflective electrode RE (or the upper surface of the portion of the reflective electrode RE covering the side surface of the protrusion SW) may be positioned on the same plane. Fig. 12C As described, the upper surface of the planarization pattern PLNP, the upper surface of the protrusion SW, and the end portion of the reflective electrode RE may be simultaneously formed through a polishing process (chemical mechanical polishing (CMP)).

[0182] The first to third anode electrodes AE1 to AE3 respectively overlapped with the first to third reflective electrodes RE1 to RE3 are disposed on the via layer VIAL (or the protrusion SW) and the first to third planarization patterns PLNP1 to PLNP3. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Figure 6 The shapes of the first to third emission areas EMA1 to EMA3 are similar to those of the first to third emission areas EMA1 to EMA3. The first to third anode electrodes AE1 to AE3 are connected to the first to third reflective electrodes RE1 to RE3, respectively.

[0183] In an embodiment, Figure 8 As shown in , the anode electrode AE ​​may be directly disposed on the end of the reflective electrode RE and the planarization pattern PLNP, and may be directly connected to the end of the reflective electrode RE. When the reflective electrode RE includes a first layer RE_S1, a second layer RE_S2, and a third layer RE_S3, the anode electrode AE ​​may be directly connected to the end of each of the first layer RE_S1, the second layer RE_S2, and the third layer RE_S3.

[0184] When the planarization pattern PLNP is disposed between the anode electrode AE ​​and the reflective electrode RE, most of the anode electrode AE ​​and the reflective electrode RE may be separated from each other by the planarization pattern PLNP. Therefore, the anode electrode AE ​​and the reflective electrode RE may have separate structures rather than an integrated structure.

[0185] In an embodiment, Fig. 9 As shown in , the anode electrode AE ​​may cover the reflective electrode RE and the planarization pattern PLNP. In a plan view, the anode electrode AE ​​may completely cover the reflective electrode RE and the planarization pattern PLNP.

[0186] In an embodiment, the first to third anode electrodes AE1 to AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), at least one of transparent conductive materials of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto.

[0187] In an embodiment, Figure 8 As shown in , the anode electrode AE ​​may completely cover the first layer RE_S1 , the second layer RE_S2 , and the third layer RE_S3 of the reflective electrode RE and the planarization pattern PLNP.

[0188] The light emitting structure EMS (or the light emitting layer) is disposed on the first to third anode electrodes AE1 to AE3. The light emitting structure EMS may emit light.

[0189] The light emitting structure EMS may be disposed completely across the first to third sub-pixels SP1 to SP3. According to an embodiment, the light emitting structure EMS may be at least partially disconnected in the boundary area BDA. Therefore, when the display panel DP (see Figure 4 ), leakage current flowing from each of the first to third sub-pixels SP1 to SP3 to the sub-pixels adjacent thereto through the layers included in the light emitting structure EMS can be reduced. Therefore, the first to third light emitting elements LD1 to LD3 can operate with relatively high reliability.

[0190] In an embodiment, the light emitting structure EMS may be directly disposed on the via layer VIAL in a boundary area BDA disposed between the first to third sub-pixels SP1 to SP3 .

[0191] For reference, when the reflective electrode RE having a certain thickness is not buried in the via layer VIAL and is disposed on the via layer VIAL, and when the light emitting structure EMS is directly disposed on the side surface of the reflective electrode RE, the light emitting structure EMS on the side surface of the reflective electrode RE may emit light, or other problems may occur. In order to prevent light from being emitted from the side surface of the reflective electrode RE, etc., a pixel defining layer PDL may be disposed on the anode electrode AE ​​and the via layer VIAL in the boundary area BDA (reference Fig.10 Meanwhile, since the reflective electrode RE according to the embodiment is buried in the via layer VIAL, a separate pixel defining layer may not be required, and the light emitting structure EMS may be directly disposed on the via layer VIAL in the boundary area BDA.

[0192] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0193] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0194] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture, etc. from penetrating into the light emitting element layer LDL.

[0195] The optical function layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optical function layer OFL may be attached to the encapsulation layer TFE by an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately and attached to the encapsulation layer TFE by an adhesive layer APL. The adhesive layer APL may further perform the function of protecting the lower layer including the encapsulation layer TFE.

[0196] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may pass light of different wavelength ranges. For example, the first to third color filters CF1 to CF3 may pass red, green, and blue light, respectively.

[0197] In embodiments, the first to third color filters CF1 to CF3 may partially overlap in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0198] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third lenses LS1 to LS3 may improve light output efficiency by redirecting light emitted from the first to third light emitting elements LD1 to LD3 to a predetermined path.

[0199] As described above, the reflective electrode RE may be disposed or buried in the groove GRV of the via layer VIAL. The planarization pattern PLNP may be disposed on the reflective electrode RE in the groove GRV of the via layer VIAL to prevent damage to the reflective electrode RE during its formation process (or patterning process).

[0200] In addition, the reflective electrode RE may include a first layer RE_S1, a second layer RE_S2, and a third layer RE_S3 sequentially stacked, each of the first layer RE_S1 and the third layer RE_S3 may include a transparent conductive material, and the second layer RE_S2 may include a metal material (particularly silver (Ag)). The third layer RE_S3 may prevent damage to the second layer RE_S2 together with the planarization pattern PLNP.

[0201] Fig.10 is a diagram showing a comparative example of a pixel Figure 6 A cross-sectional view taken along line II'.

[0202] refer to Figure 7 and Fig.10 , except for the light emitting element layer LDL, Fig.10 The example can be compared with Figure 7 Therefore, the repeated description will not be repeated.

[0203] The light emitting element layer LDL is disposed on the via layer VIAL and may include first, second and third reflective electrodes RE1_C, RE2_C and RE3_C, a planarization layer PLNL, first to third anode electrodes AE1 to AE3, a pixel defining layer PDL, a light emitting structure EMS and a cathode electrode CE.

[0204] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each anode electrode AE. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL is not limited thereto, and the pixel defining layer PDL may include an organic material.

[0205] On the via layer VIAL, first to third reflective electrodes RE1_C to RE3_C are respectively disposed in the first to third subpixels SP1 to SP3. The first to third reflective electrodes RE1_C to RE3_C may include a metal material suitable for reflecting light. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be connected to the first reflective electrode RE1_C, the second reflective electrode RE2_C, and the third reflective electrode RE3_C through the first via hole VIA1, the second via hole VIA2, and the third via hole VIA3 passing through the planarization layer PLNL, respectively.

[0206] As the resolution of the display device increases, the gaps between the first to third sub-pixels SP1 to SP3 and the gaps GAP between the first to third reflective electrodes RE1_C to RE3_C corresponding to the gaps between the first to third sub-pixels SP1 to SP3 may be reduced. That is, the first to third reflective electrodes RE1_C to RE3_C may be formed by an ultra-fine patterning process.

[0207] For example, the first to third reflective electrodes RE1_C to RE3_C may be formed by a dry etching process, and, for this purpose, the first to third reflective electrodes RE1_C to RE3_C may include aluminum (Al) or an alloy thereof in consideration of manufacturing cost and time, etc. However, the reflectivity of aluminum (Al) may be lower than that of silver (Ag), and the light output efficiency of the sub-pixel including the first to third reflective electrodes RE1_C to RE3_C including aluminum (Al) may be approximately 30% lower than the light output efficiency of the sub-pixel including the first to third reflective electrodes RE1_C to RE3_C including silver (Ag).

[0208] Meanwhile, the reflective electrode RE (refer to Figure 8 ) may be buried in the via layer VIAL and may be formed by a CMP process instead of a dry etching process. In this case, the reflective electrode RE may include silver (Ag) having a reflectivity higher than that of aluminum (Al), and may improve the light output efficiency of the sub-pixel.

[0209] Fig.11 It is shown that the Figure 7 sectional view of a comparative example of a light emitting element layer in any one of the first to third sub-pixels.

[0210] refer to Figure 8 and Fig.11 , in the sub-pixel SP_C of the first case CASE1 , the reflective electrode RE_C (or the anode electrode AE) may be buried in the via layer VIAL, and the light emitting structure EMS may be directly disposed on the reflective electrode RE_C.

[0211] As in the second case CASE2, the reflective electrode RE_C may be buried in the via layer VIAL, the anode electrode AE ​​may be directly disposed on the upper surface of the reflective electrode RE_C, and the light emitting structure EMS may also be directly disposed on the anode electrode AE. The anode electrode AE ​​and the reflective electrode RE_C may have a non-separated structure (i.e., a structure that is not separated from each other).

[0212] As in the first case CASE1 and the second case CASE2, when the reflective electrode RE_C is buried in the via layer VIAL, the reflective electrode RE_C may be formed by a CMP process instead of a conventional photolithography process. However, when the upper surface of the reflective electrode RE_C is planarized by the CMP process, damage may occur on the upper surface of the reflective electrode RE_C (e.g., on the upper surface of the second layer RE_S2). Silver (Ag) is softer than copper (Cu), and the risk of scratches occurring on the reflective electrode RE_C including silver (Ag) during the CMP process is high. When damage such as scratches occurs in the reflective electrode RE_C, the reflectivity of the reflective electrode RE_C and the light emission efficiency of the sub-pixel SP_C may be reduced.

[0213] Meanwhile, in the embodiment of the present disclosure, the planarization pattern PLNP (refer to Figure 8 ) may be disposed on the reflective electrode RE in the groove of the via layer VIAL to prevent damage (eg, scratches) to the reflective electrode RE during the CMP process.

[0214] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. Fig.12F and Figure 12G It is shown that the formation Fig. 12A A cross-sectional view of the via layer method. Figure 8 The sub-pixels of the embodiments can be FIG. 12A to FIG. 12E For ease of description, the following description is omitted. Figure 8 The description of the embodiment is repeated.

[0215] refer to Figure 8 and Fig. 12A , a via layer VIAL (or a base layer) including a protrusion SW may be formed. In other words, a groove GRV and a protrusion SW surrounding the groove GRV may be formed in the via layer VIAL. The protrusion SW may be formed in the sub-pixels SP1 to SP3 (refer to Figure 7 ) protrude upward in the boundary area BDA between the via layers to form a groove GRV on the upper surface of the via layer VIAL.

[0216] In an embodiment, Fig.12F As shown in FIG. 1 , a half-tone mask MASK can be used to simultaneously form a protrusion SW in the via layer VIAL and a via VIAH formed through the via layer VIAL. In other words, in the process of forming the via VIAH, the protrusion SW can also be formed. Here, the via VIAH can be formed at a position adjacent to the connection electrode CCE (reference Figure 7 and Figure 8) in the area corresponding to .

[0217] For example, the half-tone mask MASK may include first to third regions A1 to A3 having different transmittances, and a photolithography process and an etching process using the half-tone mask MASK may be performed on the via layer VIAL. The protrusion SW may be formed in a region corresponding to the first region A1, the via hole VIAH may be formed in a region corresponding to the third region A3, and the rest of the via layer VIAL may be formed in a region corresponding to the second region A2.

[0218] In an embodiment, Figure 12G As shown in , the via layer VIAL and the protrusion SW may be formed by different processes. For example, the via layer VIAL may be formed, and then the protrusion SW may be formed by a separate process. In this case, the protrusion SW may include a material different from that of the via layer VIAL.

[0219] refer to Fig. 12B , a reflective electrode layer REL may be formed on the via layer VIAL. The reflective electrode layer REL may be completely formed on the via layer VIAL.

[0220] In an embodiment, the reflective electrode layer REL may include Figure 8 The depicted reflective electrodes RE correspond to first, second, and third layers sequentially stacked.

[0221] refer to Fig. 12C , a planarization layer PLNL may be formed on the reflective electrode layer REL. The planarization layer PLNL may be completely formed on the via layer VIAL (or the reflective electrode layer REL). The planarization layer PLNL may have a thickness sufficient to make the upper surface higher than the upper surface of the protrusion SW.

[0222] refer to Fig. 12C and Fig.12D , the upper surface of the planarization layer PLNL may be planarized through a polishing process (chemical mechanical polishing (CMP)).

[0223] The portion of the reflective electrode layer REL disposed on the protrusion SW and the portion of the planarization layer PLNL disposed on the protrusion SW may be removed by a polishing process. Therefore, the reflective electrode layer REL may be separated in the boundary region between the sub-pixels, and the reflective electrode RE as the portion of the reflective electrode layer REL disposed in the groove GRV of the via layer VIAL may be formed.

[0224] refer to Fig.12E , the anode electrode AE ​​may be formed on the via layer VIAL and the planarization pattern PLNP (or the planarization layer PLNL).

[0225] Afterwards, the Figure 8 The remaining configurations shown in FIG. 1 , such as the light emitting structure EMS, the cathode electrode CE and the encapsulation layer TFE. In this way, a device including a light emitting device according to the embodiment of the present invention can be manufactured. Figure 8 A display device of a sub-pixel SP of an embodiment.

[0226] Fig.13 is an example of a pixel along the Figure 6 A cross-sectional view taken along line II'. Fig.14 is an example of a pixel along the Figure 6 A cross-sectional view taken along line I-I'. Fig.14 In the embodiment of the separation member, an embodiment of the separation member is shown, and in addition to the separation member, Fig.14 The embodiments can be used with Fig.13 The embodiments are basically the same.

[0227] refer to Figure 7 , Fig.13 and Fig.14 , except for the buffer pattern BFP, the pixel defining layer PDL and the separation member (eg, the protrusion pattern PRT and the trenches TRCH1 and TRCH2), Fig.13 and Fig.14 The embodiments can be used with Figure 7 The embodiments of the present invention are substantially the same or similar. Therefore, repeated description will not be repeated.

[0228] In an embodiment, the buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3 disposed in the groove of the via layer VIAL.

[0229] In an embodiment, the buffer pattern BFP may include a conductive material and may improve the performance of the corresponding reflective electrode RE (see Figure 8 ) and the electrical connection characteristics between the circuit elements of the pixel circuit layer PCL. For example, the buffer pattern BFP may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto.

[0230] In an embodiment, the buffer pattern BFP may include an insulating material. For example, the buffer pattern BFP may include a silicon nitride (SiN x ), silicon carbonitride or silicon oxide (SiO x ) of an inorganic material, but the embodiment is not limited thereto.

[0231] According to an embodiment, the buffer pattern BFP may have a multi-layer structure. For example, the buffer pattern BFP may include a conductive layer and an insulating layer.

[0232] The height of the corresponding reflective electrode in the third direction DR3 may be adjusted by setting the buffer pattern BFP. For example, the buffer pattern BFP may be set between the first reflective electrode RE1 and the via layer VIAL in the first sub-pixel SP1. In the second sub-pixel SP2, the buffer pattern BFP may not be set between the second reflective electrode RE2 and the via layer VIAL, and the second reflective electrode RE2 may be directly set on the via layer VIAL. Similarly, in the third sub-pixel SP3, the buffer pattern BFP may not be set between the third reflective electrode RE3 and the via layer VIAL, and the third reflective electrode RE3 may be directly set on the via layer VIAL.

[0233] The first to third reflective electrodes RE1 to RE3 may be used as full reflectors, and the cathode electrode CE may be used as a half reflector. The light emitted from the light emitting layer of the light emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrode RE and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described above, the distance between each reflective electrode RE and the cathode electrode CE may be understood as a resonance distance for the light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0234] For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively, and a distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than a distance between the second reflective electrode RE2 and the cathode electrode CE.

[0235] Due to the buffer pattern BFP, the first subpixel SP1 may have a resonance distance shorter than the resonance distances of the second subpixel SP2 and the third subpixel SP3. The resonance distance adjusted as described above may enable light of a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first subpixel SP1 may effectively and efficiently output light of the corresponding wavelength range.

[0236] exist Fig.13, the buffer pattern BFP is provided to the first sub-pixel SP1 and is not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern BFP may also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the buffer pattern BFP may also be provided to the second sub-pixel SP2, and the resonance distance of the second sub-pixel SP2 may be adjusted. For example, the distance between the second reflective electrode RE2 and the cathode electrode CE may be the same as the distance between the first reflective electrode RE1 and the cathode electrode CE, and the distance between the third reflective electrode RE3 and the cathode electrode CE may be longer than the distance between the first reflective electrode RE1 and the cathode electrode CE.

[0237] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each anode electrode AE. In an embodiment, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0238] The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be completely disposed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least some of the layers in the light emitting structure EMS may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiment is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the portions may be disposed in the opening OP of the pixel defining layer PDL.

[0239] A separator may be provided in the boundary area BDA between adjacent sub-pixels.

[0240] The separation piece may cause discontinuity to be formed in the light emitting structure EMS at the boundary area BDA. For example, due to the separation piece, the light emitting structure EMS may be broken or bent at the boundary area BDA.

[0241] The separation member may be provided in or on the pixel defining layer PDL.

[0242] In embodiments, the pixel defining layer PDL may include a protrusion pattern PRT as a separation member in the boundary area BDA.

[0243] like Fig.13 As shown in , a protrusion pattern PRT additionally stacked on the pixel defining layer PDL may be provided in the boundary area BDA. The width of the protrusion pattern PRT may be widened in the upper portion. For example, the protrusion pattern PRT may include an inorganic insulating pattern. The width of the topmost inorganic insulating pattern among the inorganic insulating patterns may be greater than the width of the inorganic insulating pattern immediately below the topmost inorganic insulating pattern. For example, in the boundary area BDA, the first to third inorganic insulating patterns may be sequentially stacked on the pixel defining layer PDL, and the topmost third inorganic insulating pattern may have a width greater than the width of the second inorganic insulating pattern. For example, the protrusion pattern PRT may have a "T"-shaped cross-section or an "I"-shaped cross-section in the boundary area BDA. According to the shape of the protrusion pattern PRT, a plurality of layers included in the light emitting structure EMS may be at least partially disconnected or bent in the boundary area BDA.

[0244] The separation member may be variously modified and provided so that the light emitting structure EMS may have a discontinuous portion in the boundary area BDA. In an embodiment, the pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the separation member in the boundary area BDA.

[0245] like Fig.14 As shown in , one or more trenches TRCH1 and TRCH2 may be formed through the pixel defining layer PDL and may be partially formed through the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 may be formed at least partially through the via layer VIAL, and portions of the pixel defining layer PDL in the one or more trenches TRCH1 and TRCH2 may be removed.

[0246] For example, two grooves TRCH1 and TRCH2 separated from each other may be provided in the boundary area BDA. For example, the first groove TRCH1 and the second groove TRCH2 may be provided in the boundary area BDA between the second sub-pixel SP2 and the third sub-pixel SP3, the first groove TRCH1 may be provided along the edge of the second sub-pixel SP2, and the second groove TRCH2 may be provided along the edge of the third sub-pixel SP3. When the grooves TRCH1 and TRCH2 are separated from each other, the width of each of the grooves TRCH1 and TRCH2 may remain constant, and the discontinuous portion of the light emitting structure EMS may become uniform in the boundary area BDA. When the grooves TRCH1 and TRCH2 are connected, the width of the connected portion of the grooves TRCH1 and TRCH2 may become greater than the width of the other portion, the discontinuous portion of the light emitting structure EMS may become uneven, and the characteristics of the light emitting structure EMS may become uneven.

[0247] exist Fig.14 In the embodiment, two trenches TRCH1 and TRCH2 are provided in the boundary area BDA. However, the embodiment is not limited thereto. For example, the pixel defining layer PDL may include one trench in the boundary area BDA. Alternatively, the pixel defining layer PDL may include three or more trenches in the boundary area BDA.

[0248] Due to the first trench TRCH1 and the second trench TRCH2 provided in the boundary area BDA, discontinuous portions such as the first void VD1 and the second void VD2 may be formed in the light emitting structure EMS. A portion of the plurality of layers stacked in the light emitting structure EMS may be disconnected or bent by the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be disconnected in the first void VD1 and the second void VD2. As described above, due to the first trench TRCH1 and the second trench TRCH2, the portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3 may be at least partially separated.

[0249] exist Fig.14 In the boundary area BDA, the first void VD1 and the second void VD2 are formed in the light emitting structure EMS, but this is exemplary and the embodiment is not limited thereto. For example, in the boundary area BDA, a concave valley may be formed in the light emitting structure EMS. According to the shapes of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the light emitting structure EMS may be variously changed.

[0250] In embodiments, the light emitting structure EMS may be formed by processes such as vacuum deposition and inkjet printing, etc. In this case, the same material as that of the light emitting structure EMS may be positioned on the bottom surfaces of the first and second trenches TRCH1 and TRCH2 disposed adjacent to the via layer VIAL.

[0251] Fig.15 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0252] refer to Fig.15 The light emitting structure EMS may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 may be configured substantially identically.

[0253] Each of the first light emitting unit EU1 and the second light emitting unit EU2 may include at least one light emitting layer that generates light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0254] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and if necessary, may further include a hole buffer layer and an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration as or different configurations from each other.

[0255] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and if necessary, may further include an electron buffer layer and a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration as or different configurations from each other.

[0256] A connection layer may be provided between the first light emitting unit EU1 and the second light emitting unit EU2 to connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other, and the connection layer may be provided in the form of a charge generation layer CGL. In an embodiment, the charge generation layer CGL may have a stacked structure of a P dopant layer and an N dopant layer. For example, the P dopant layer may include a P-type dopant such as HAT-CN, TCNQ, and NDP-9, and the N dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not limited thereto.

[0257] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. The light emitted from each of the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and observed as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a stacked structure of a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light. The red light and the green light may be mixed, and thus yellow light may be provided. In this case, an intermediate layer configured to perform the function of transporting holes and / or blocking the transport of electrons may be further provided between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0258] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color.

[0259] The light emitting structure EMS may be formed by a method such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0260] Fig.16 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0261] refer to Fig.16 The light emitting structure EMS' may have a series structure in which the first light emitting unit EU1' to the third light emitting unit EU3' are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 in the embodiment may be configured substantially identically.

[0262] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0263] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and if necessary, may further include a hole buffer layer and an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration as or different configurations from each other.

[0264] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and if necessary, may further include an electron buffer layer and a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration as or different configurations from each other.

[0265] The first charge generation layer CGL1' is disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' is disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0266] In an embodiment, the first to third light-emitting layers EML1' to EML3' may generate light of different colors. Light emitted from each of the first to third light-emitting layers EML1' to EML3' may be mixed and observed as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0267] In other embodiments, two or more of the first to third light emitting layers EML1 ′ to EML3 ′ may generate light of the same color.

[0268] and Fig.15 and Fig.16 The embodiments are different. Figure 7 The light emitting structure EMS may include one light emitting unit in each of the first to third light emitting elements LD1 to LD3. The light emitting unit included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting unit of the first light emitting element LD1 may emit red light, the light emitting unit of the second light emitting element LD2 may emit green light, and the light emitting unit of the third light emitting element LD3 may emit blue light. In this case, Fig.15 and Fig.16Unlike that shown in FIG. 1 , the light emitting units of the first to third subpixels SP1 to SP3 may be separated from each other, and each of them may be disposed in the opening OP of the pixel defining layer PDL. In this case, at least a portion of the color filters CF1 to CF3 may be omitted.

[0269] Fig.17 It is shown Figure 5 A plan view of an embodiment of any one of the pixels.

[0270] refer to Fig.17 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0271] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' around the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' around the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' around the third emission area EMA3'.

[0272] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be arranged in the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0273] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have an area larger than that of the first emission area EMA1', and the third emission area EMA3' may have an area larger than that of the second emission area EMA2'. However, the embodiment is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than that of each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, the areas of the first to third sub-pixels SP1' to SP3' may be variously modified according to the embodiment.

[0274] Fig.18 It is shown Figure 5 A plan view of an embodiment of any one of the pixels.

[0275] refer to Fig.18The first pixel PXL1" may include the first sub-pixel SP1" to the third sub-pixel SP3". The first sub-pixel SP1" may include the first emission area EMA1" and the non-emission area NEA" around the first emission area EMA1". The second sub-pixel SP2" may include the second emission area EMA2" and the non-emission area NEA" around the second emission area EMA2". The third sub-pixel SP3" may include the third emission area EMA3" and the non-emission area NEA" around the third emission area EMA3".

[0276] When viewed in the third direction DR3, the first to third sub-pixels SP1″ to SP3″ may have a polygonal shape. Fig.18 As shown in FIG. 1 , the shapes of the first to third sub-pixels SP1 ″ to SP3 ″ may be hexagonal shapes.

[0277] When viewed in the third direction DR3, the first to third emission areas EMA1" to EMA3" may have a circular shape. However, the embodiment is not limited thereto. For example, each of the first to third emission areas EMA1" to EMA3" may have a polygonal shape.

[0278] The first subpixel SP1" and the third subpixel SP3" may be arranged in the first direction DR1. The second subpixel SP2" may be disposed in a direction (or an oblique direction) inclined at an acute angle from the second direction DR2 with respect to the first subpixel SP1".

[0279] Figure 6 , Fig.17 and Fig.18 The arrangement of the sub-pixels shown in is exemplary, and the embodiment is not limited thereto. Each pixel may include two or more sub-pixels, the sub-pixels may be arranged in various ways, each of the sub-pixels may have various shapes, and each of the emission regions of each of the sub-pixels may also have various shapes.

[0280] Fig.19 is a block diagram illustrating an embodiment of a display system.

[0281] refer to Fig.19 , the display system 1000 may include a processor 1100 , and one or more display devices 1210 and 1220 .

[0282] The processor 1100 may perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and may control the other components.

[0283] exist Fig.19 , the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0284] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0285] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0286] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0287] Fig. 20 It is shown Fig.19 A perspective view of an example application of the display system.

[0288] refer to Fig. 20 , Fig.19 The display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0289] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device housing box 2200. The head-mounted strap 2100 may be connected to the display device housing box 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for fixing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to surround the side portion of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head. However, the embodiment is not limited thereto. For example, the head-mounted strap 2100 may be implemented in the form of a glasses frame or a helmet, etc.

[0290] The display device receiving box 2200 can receive Fig.19 The first display device 1210 and the second display device 1220. The display device container 2200 may further contain Fig.19 Processor 1100.

[0291] Fig.21 It is shown Fig. 20 Illustration of a head mounted display device worn by a user.

[0292] refer to Fig.21 , also refer to Fig. 20 The head mounted display device 2000 (or wearable electronic device) may include a display panel emitting light and a lens unit disposed on the display panel (or on the emission path of light). The display panel may include a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220. The lens unit may further include one or more lenses LLNS and RLNS.

[0293] The right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user in the display device housing box 2200. The left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user in the display device housing box 2200.

[0294] The image output from the first display panel DP1 may be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract the light from the first display panel DP1 to be directed toward the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0295] The image output from the second display panel DP2 may be displayed to the left eye of the user through the left eye lens LLNS. The left eye lens LLNS may refract the light from the second display panel DP2 to be directed toward the left eye of the user. The left eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0296] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may pass through the respective corresponding sub-regions and may be observed by the user.

[0297] Although specific embodiments and application examples are described herein, other embodiments and modifications may be derived from the above description. Therefore, the spirit of the present disclosure is not limited to these embodiments, but extends to the scope of the appended claims, various obvious modifications and equivalents as set forth.

Claims

1. A display device, wherein: The display device comprises: a base layer including a groove surrounded by a protrusion, wherein the protrusion is disposed in a boundary region between a plurality of sub-pixels; a reflective electrode, arranged on the base layer in the groove; a planarization pattern, disposed in the groove on the reflective electrode; an anode electrode disposed on the planarization pattern and contacting the reflective electrode; and The light-emitting layer is arranged on the anode electrode.

2. The display device according to claim 1, wherein: A portion of the reflective electrode covers a side surface of the protrusion, and Wherein, an upper surface of the portion of the reflective electrode, an upper surface of the planarization pattern, and an upper surface of the protrusion are positioned on the same plane.

3. The display device according to claim 2, wherein: The upper surface of the portion of the reflective electrode, the upper surface of the planarization pattern, and the upper surface of the protrusion are simultaneously formed through a polishing process.

4. The display device according to claim 2, wherein: The anode electrode is directly disposed on the portion of the reflective electrode and the planarization pattern, and directly contacts the portion of the reflective electrode.

5. The display device according to claim 2, wherein: The reflective electrode includes a first layer, a second layer, and a third layer stacked sequentially, wherein each of the first layer and the third layer comprises a transparent conductive material, and Wherein, the second layer comprises a metal material.

6. The display device according to claim 5, wherein: The second layer includes silver.

7. The display device according to claim 5, wherein: The anode electrode directly contacts the second layer of the reflective electrode.

8. The display device according to claim 1, wherein: The light emitting layer directly contacts the base layer in the boundary region between the plurality of sub-pixels.

9. The display device according to claim 1, wherein: The planarization pattern includes an inorganic material, and Wherein, the anode electrode comprises a transparent conductive material.

10. The display device according to claim 1, wherein: The reflective electrode surrounds the planarization pattern in a plan view, and Wherein, the anode electrode covers the reflective electrode.

11. The display device according to claim 1, wherein: The display device further includes: A buffer pattern is disposed in the groove below the reflective electrode.

12. The display device according to claim 1, wherein: The display device further includes: a pixel defining layer disposed on the base layer in the boundary region between the plurality of sub-pixels; and A protrusion pattern is disposed on the pixel defining layer and has a width that becomes wider toward an upper portion.

13. The display device according to claim 1, wherein: The display device further includes: a plurality of grooves formed in the base layer in the boundary region, Wherein, the plurality of grooves are separated from each other.

14. A wearable electronic device, wherein: The wearable electronic device comprises: a display panel that emits light; and at least one lens, disposed on the display panel, Wherein, the display panel comprises: a base layer including a groove surrounded by a protrusion, wherein the protrusion is disposed in a boundary region between a plurality of sub-pixels; a reflective electrode, arranged on the base layer in the groove; a planarization pattern, disposed in the groove on the reflective electrode; an anode electrode disposed on the planarization pattern and contacting the reflective electrode; and The light-emitting layer is arranged on the anode electrode.

15. A method for manufacturing a display device, wherein: The method comprises: forming a groove in the base layer, the groove being surrounded by a protrusion, the protrusion being disposed in a boundary region between a plurality of sub-pixels; forming a reflective electrode layer on the substrate layer; forming a planarization layer on the reflective electrode layer; removing the portion of the reflective electrode layer on the protrusion and the portion of the planarization layer on the protrusion by a polishing process; forming an anode electrode on the base layer and the planarization layer; and A light emitting layer is formed on the anode electrode.

16. The method according to claim 15, wherein: The forming the groove in the base layer includes: simultaneously forming the groove and a via hole in the base layer using a half-tone mask.

17. The method according to claim 15, wherein: The forming the groove in the base layer comprises: forming the base layer; and The groove is formed in the base layer.

18. The method according to claim 15, wherein: The reflective electrode layer is separated in the boundary region between the plurality of sub-pixels through the polishing process to form a reflective electrode, and the reflective electrode is disposed in the groove.

19. The method according to claim 15, wherein: The forming of the reflective electrode layer comprises: sequentially forming a first layer, a second layer and a third layer on the base layer, wherein each of the first layer and the third layer comprises a transparent conductive material, and Wherein, the second layer comprises a metal material.

20. The method according to claim 19, wherein: The second layer includes silver.

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