Display substrate and display device

Abstract

The application provides a display substrate and a display device. The display substrate comprises a substrate and a plurality of sub-pixels. The sub-pixel comprises a pixel electrode and an effective light-emitting area. The pixel electrode comprises an interlinked main body and a connecting portion. The main body is the same shape as the effective light-emitting area, and the main body and at least part of the boundary of the pixel electrode coincide. The plurality of sub-pixels comprises at least one first sub-pixel and one second sub-pixel with the same light-emitting color. The nearest first sub-pixel and second sub-pixel are arranged along a second direction. The area of the orthographic projection of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the substrate is different. The two orthographic projections of the connecting portion and the main body of at least one of the first sub-pixel and the second sub-pixel on a straight line extending along a first direction at least partially do not overlap. The orthographic projection of the pixel electrode of the second sub-pixel on a straight line extending along the second direction is located within the orthographic projection of the pixel electrode of the first sub-pixel on the same straight line.

Description

[0001] This application is a divisional application. The original application has the application number 202080002176.4 and the application date is September 29, 2020. The entire contents of the original application can be incorporated herein by reference.

[0002] This application claims priority to PCT application No. PCT / CN2020 / 086997, filed on April 26, 2020, and PCT application No. PCT / CN2020 / 114623, filed on September 10, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0004] Active-matrix organic light emitting diode (AMOLED) display substrates have been widely used in display devices due to their advantages such as self-illumination, wide color gamut, high contrast, flexibility, and high response.

[0005] Currently, with the increasing pixel density in AMOLED display substrates, the pixel size is gradually decreasing, limiting the design space for pixels. Therefore, optimizing the pixel circuit structure and manufacturing process can significantly improve the display performance of display devices using AMOLED substrates. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display substrate and a display device that, while increasing the sub-pixel distribution density, effectively simplifies the overall layout design of the pixel circuits in the display substrate, thereby improving the light transmittance of the display substrate.

[0007] To achieve the above objectives, the present disclosure provides the following technical solutions:

[0008] On one hand, some embodiments of this disclosure provide a display substrate. The display substrate includes a substrate and a plurality of sub-pixels. Each sub-pixel includes a pixel electrode and an effective light-emitting area. The pixel electrode includes interconnected main body portions and connecting portions. The main body portions have the same shape as the effective light-emitting areas, and at least a portion of the boundary of the main body portions coincides with that of the pixel electrodes. The plurality of sub-pixels includes at least one first sub-pixel and one second sub-pixel with the same emitted color. The closest first sub-pixel and second sub-pixel are arranged along a second direction. The orthographic projections of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the substrate have different areas. The orthographic projections of the connecting portion and the main body portion of at least one of the first and second sub-pixels on a straight line extending along a first direction do not at least partially overlap. The orthographic projection of the pixel electrode of the second sub-pixel on a straight line extending along the second direction lies within the orthographic projection of the pixel electrode of the first sub-pixel on the same straight line. The second direction intersects the first direction, and the angle between them ranges from 80° to 100°.

[0009] In this embodiment, multiple sub-pixels with the same emission color employ two different structures: a first sub-pixel and a second sub-pixel. By designing the shapes of the pixel electrodes in the first and second sub-pixels as described above, the overall layout design of the pixel circuitry in the display substrate can be effectively simplified while increasing the sub-pixel distribution density, thereby improving the light transmittance of the display substrate.

[0010] In some embodiments, the main body includes a first side, a second side, and a third side connected in sequence; the third side extends along the second direction. The connecting portion is connected to the second side and is spaced apart from the first side. A straight line connecting any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, together with the main body and the connecting portion, forms a recessed area.

[0011] In some embodiments, the display substrate further includes a plurality of layers located between the substrate and the pixel electrode; the plurality of layers include at least one metal pattern. Along a direction perpendicular to the substrate, in each layer from the substrate to the pixel electrode, at least a portion of the notch region does not overlap with the metal pattern.

[0012] In other embodiments, the display substrate further includes a plurality of layers located between the substrate and the pixel electrode; the plurality of layers include a semiconductor pattern and at least one metal pattern. Along a direction perpendicular to the substrate, in each layer from the substrate to the pixel electrode, at least a portion of the notch region does not overlap with either the semiconductor pattern or the metal pattern.

[0013] In some embodiments, the connection portion of the pixel electrode in the first sub-pixel includes a bent portion and a compensation portion connected to the bent portion. The compensation portion extends along the second direction. The bent portion is connected to the second side, and there is a gap between the bent portion and the first side.

[0014] In some embodiments, the ratio of the area of ​​the notch region to the area of ​​the two orthographic projections of the curved portion on the substrate ranges from 0.2 to 5.

[0015] In some embodiments, the maximum dimension of the compensation portion along the first direction is greater than the maximum dimension of the bending portion along the first direction.

[0016] In some embodiments, the maximum dimension of the connection portion of the pixel electrode in the second sub-pixel along the second direction is less than or equal to the maximum dimension of the bending portion of the pixel electrode in the first sub-pixel along the second direction.

[0017] In some embodiments, the sub-pixel further includes pixel circuitry. The pixel circuitry includes a driving transistor.

[0018] The orthographic projection of the metal pattern with the same potential as the control electrode of the driving transistor onto the substrate is the first projection. The area where the orthographic projection of the pixel electrode in the first sub-pixel overlaps with the first projection on the substrate is the first area. The area where the orthographic projection of the pixel electrode in the second sub-pixel overlaps with the first projection on the substrate is the second area. The ratio of the first area to the second area ranges from 0.8 to 1.2.

[0019] In some embodiments, the display substrate further includes: a first gate metal layer located between the substrate and the pixel electrode, and a first metal layer located between the first gate metal layer and the pixel electrode. A metal pattern having the same potential as the control electrode of the driving transistor includes: a first electrode of a capacitor located in the first gate metal layer, and a first transition electrode located in the first metal layer.

[0020] The area of ​​the orthographic projection of the pixel electrode of the first sub-pixel and the first electrode of the capacitor on the substrate is smaller than the area of ​​the orthographic projection of the pixel electrode of the second sub-pixel and the first electrode of the capacitor on the substrate; and the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel and the first transfer electrode on the substrate is larger than the area of ​​the orthographic projection of the pixel electrode of the second sub-pixel and the first transfer electrode on the substrate.

[0021] In some embodiments, the display substrate further includes a plurality of signal lines extending along the first direction. The orthographic projection of the pixel electrode of the first sub-pixel on the substrate overlaps with the orthographic projection of at least three signal lines located on the same layer on the substrate.

[0022] In some embodiments, the at least three signal lines located on the same layer include: at least one gate scan signal line, at least one light emission control signal line, and at least one reset control signal line.

[0023] In some embodiments, the display substrate further includes: a first insulating layer and a plurality of connection electrodes. The first insulating layer is located between the pixel electrode and the connection electrode and has a plurality of first vias. The pixel electrode is coupled to the connection electrode through the first vias. The sub-pixel further includes a pixel circuit. The plurality of pixel circuits are arranged in a row along a first direction and in a column along a second direction. The orthographic projections of the plurality of first vias corresponding to the plurality of pixel circuits in the same row onto the substrate are arranged along a first straight line. In the plurality of sub-pixels corresponding to the plurality of pixel circuits in the same row, the effective light-emitting areas of the first sub-pixel and the effective light-emitting areas of the second sub-pixel are respectively located on opposite sides of the first straight line.

[0024] In some embodiments, the display substrate further includes a second insulating layer and a plurality of driving electrodes. The second insulating layer is located between the connection electrode and the driving electrode and has a plurality of second vias. The connection electrode is coupled to the driving electrode through the second vias. The first via and the second via corresponding to the same connection electrode are spaced apart by their orthogonal projections onto the substrate.

[0025] In some embodiments, the orthographic projections of the plurality of second vias corresponding to the plurality of pixel circuits in the same row on the substrate are arranged along a second straight line.

[0026] In some embodiments, the distance between the orthogonal projection of either the first via or the second via onto the substrate and the effective light-emitting area of ​​the corresponding sub-pixel is greater than 2 μm.

[0027] In some embodiments, the shapes and areas of the orthographic projections of the first via and the second via on the substrate are substantially the same. The orthographic projections of the first via and the second via corresponding to the same connection electrode on the substrate are aligned along a third straight line.

[0028] In some embodiments, the shapes of the orthographic projections of the driving electrode and the connecting electrode on the substrate are substantially the same, and the orthographic projection area of ​​the connecting electrode on the substrate is larger than the orthographic projection area of ​​the driving electrode on the substrate.

[0029] In some embodiments, the orthographic projection of the driving electrode on the substrate lies within the orthographic projection of the connecting electrode on the substrate, and a portion of the boundary of their orthographic projections coincides or substantially coincides.

[0030] In some embodiments, the orthographic projection of the connecting electrode on the substrate and the orthographic projection of the driving electrode on the substrate have a non-overlapping portion, and the orthographic projection of the first via on the substrate overlaps with the non-overlapping portion.

[0031] In some embodiments, the display substrate further includes a semiconductor patterning layer and a third insulating layer. The semiconductor patterning layer is located between the substrate and the driving electrode. The third insulating layer is located between the driving electrode and the semiconductor patterning layer and has a plurality of third vias. The driving electrode is coupled to a corresponding portion of the semiconductor patterning layer through the third vias. The third via, the second via, and the first via corresponding to the same driving electrode are spaced apart from each other in three orthographic projections onto the substrate.

[0032] In some embodiments, the minimum interval between the orthographic projection of either the first orthographic hole or the second orthographic hole on the substrate and the orthographic projection of the third orthographic hole on the substrate ranges from 0.8 μm to 10 μm. The minimum interval between the orthographic projections of the first orthographic hole and the second orthographic hole on the substrate ranges from 1 μm to 10 μm.

[0033] In some embodiments, the display substrate further includes multiple data lines. The data lines are disposed on the same layer as the driving electrodes. The third insulating layer also has multiple fourth vias. The data lines are connected to corresponding pixel circuits through the fourth vias. The data lines extend along the second direction and include multiple protrusions protruding towards the corresponding pixel circuits in the first direction. The overlap area between the orthographic projection of the fourth via on the substrate and the orthographic projection of the protrusions on the substrate is 70%-100% of the orthographic projection area of ​​the fourth via on the substrate.

[0034] In some embodiments, the display substrate further includes a plurality of power signal lines. The plurality of power signal lines includes at least one first power signal line. The first power signal line is disposed on the same layer as the connection electrode. The first power signal line includes a plurality of first sub-power signal lines extending along the first direction and a plurality of second sub-power signal lines extending along the second direction. The first sub-power signal lines and the second sub-power signal lines are interconnected.

[0035] There is a gap between the two effective light-emitting areas of the closest first and second sub-pixels. The orthographic projection of the first sub-power signal line on the substrate passes through the gap between the two effective light-emitting areas of the first and second sub-pixels. At least one second sub-power signal line has at least one break. The orthographic projection of the virtual connection between the two endpoints of the break in the second direction on the substrate passes through the two effective light-emitting areas of the first and second sub-pixels and the orthographic projection of the gap on the substrate. The second sub-power signal line with the break does not overlap with the orthographic projections of the two effective light-emitting areas of the first and second sub-pixels and the gap on the substrate.

[0036] In some embodiments, the plurality of power signal lines further include a plurality of second power signal lines. The second power signal lines extend along the second direction. When the display substrate further includes a second insulating layer and a plurality of driving electrodes, the second power signal lines are disposed on the same layer as the driving electrodes. The second insulating layer also has a plurality of fifth vias. The second sub-power signal lines are correspondingly coupled to the second power signal lines through the fifth vias.

[0037] The orthographic projections of the second power signal line and the second sub-power signal line coupled thereto on the substrate at least partially overlap. The orthographic projection of the second power signal line on the substrate partially overlaps with the orthographic projection of the effective light-emitting area of ​​either the first sub-pixel or the second sub-pixel on the substrate.

[0038] In some embodiments, the orthographic projections of the plurality of fifth vias located in the same row along the first direction onto the substrate lie on a fourth straight line extending along the first direction. The distance between the orthographic projection of the fifth via onto the substrate and the orthographic projection of any of the effective light-emitting areas onto the substrate is greater than 2.5 μm.

[0039] In some embodiments, the closest first and second sub-pixels constitute a sub-pixel pair. A sub-pixel group includes a first-color sub-pixel, the sub-pixel pair, and a third-color sub-pixel arranged sequentially along the first direction. The sub-pixel pair is configured to emit second-color light. The center of the orthographic projection of at least one of the first effective light-emitting area of ​​the first-color sub-pixel and the third effective light-emitting area of ​​the third-color sub-pixel onto the substrate lies within the orthographic projection of the corresponding first sub-power signal line onto the substrate.

[0040] In some embodiments, two second sub-power signal lines located on either side of and adjacent to the first effective light-emitting area of ​​the first color sub-pixel are unequally distanced from the center line extending along the second direction of the first effective light-emitting area. The display substrate further includes a plurality of pads and a plurality of support portions disposed on the same layer as the first power signal lines. The pads extend along the second direction. The pads are located between the first effective light-emitting area and the second sub-power signal lines, and are correspondingly coupled to the second sub-power signal lines via the support portions. The distance between the second sub-power signal line coupled to the pad and the center line extending along the second direction of the first effective light-emitting area is greater than the distance between another second sub-power signal line adjacent to the first effective light-emitting area and the center line. The pad is also correspondingly coupled to the first sub-power signal line.

[0041] In some embodiments, the pad is generally elongated. The center of the orthographic projection of the pad onto the substrate lies within the orthographic projection of the first sub-power signal line coupled to it onto the substrate.

[0042] In some embodiments, the ratio of the two distances between the orthographic projections of the two effective light-emitting areas of the first sub-pixel and the second sub-pixel onto the substrate and the orthographic projection of the first sub-power signal line located between the two effective light-emitting areas onto the substrate ranges from 0.9 to 1.1.

[0043] On the other hand, a display device is provided. The display device includes a display substrate as described in some of the foregoing embodiments. The beneficial effects achievable by the display device in this disclosure are the same as those achievable by the display substrate in some of the foregoing embodiments, and will not be repeated here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in some embodiments of this disclosure, the accompanying drawings used in the description of some embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings.

[0045] Figure 1 This is a schematic diagram of the structure of a display device according to some embodiments of the present disclosure;

[0046] Figure 2A This is an enlarged schematic diagram of a display substrate in the M0 region according to some embodiments of the present disclosure;

[0047] Figure 2B This is a schematic diagram of the structure of a sub-pixel group according to some embodiments of the present disclosure;

[0048] Figure 2C This is a schematic diagram of the distribution of a sub-pixel on a substrate according to some embodiments of the present disclosure;

[0049] Figure 3 This is a schematic diagram of the structure of a pixel circuit according to some embodiments of the present disclosure;

[0050] Figure 4 This is a schematic diagram of the structure of each pixel electrode in a sub-pixel group according to some embodiments of the present disclosure;

[0051] Figure 5 This is an enlarged schematic diagram of a display substrate in region M1 according to some embodiments of the present disclosure;

[0052] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I This is a top view schematic diagram of different layers of a display substrate during its fabrication process according to some embodiments of the present disclosure;

[0053] Figure 6E' This is a schematic diagram showing the position of the vias in the first metal layer and the second interlayer insulating layer 140 according to some embodiments of the present disclosure;

[0054] Figure 6G' This is a schematic diagram showing the position between the second metal layer and the via in the first planarization layer 122 according to some embodiments of this disclosure;

[0055] Figure 6H'This is a schematic diagram showing the position between the second metal layer and the via in the second planarization layer 121 according to some embodiments of the present disclosure;

[0056] Figure 6I' This is a schematic diagram showing the position between the second metal layer and the pixel electrode layer according to some embodiments of this disclosure;

[0057] Figure 7A This is a partial schematic diagram of a display substrate according to some embodiments of the present disclosure;

[0058] Figure 7B This is a schematic cross-sectional view of a display substrate along the AA' direction according to some embodiments of the present disclosure;

[0059] Figure 7C This is a schematic cross-sectional view of a display substrate along the BB' direction according to some embodiments of the present disclosure;

[0060] Figure 7D This is a schematic cross-sectional view of a display substrate along the CC' direction according to some embodiments of the present disclosure;

[0061] Figure 7E This is a schematic cross-sectional view of a display substrate along the DEFGH direction according to some embodiments of the present disclosure;

[0062] Figure 7F This is a schematic cross-sectional view along the LMN direction of a display substrate according to some embodiments of the present disclosure;

[0063] Figure 7G This is a schematic cross-sectional view along the RST direction of a display substrate according to some embodiments of the present disclosure;

[0064] Figure 8 This is a schematic diagram showing the positions of a first via, a second via, a third via, and a pixel electrode according to some embodiments of the present disclosure;

[0065] Figure 9 This is a schematic diagram showing the position of a pixel electrode of a first sub-pixel relative to its adjacent pixel electrodes according to some embodiments of the present disclosure. Detailed Implementation

[0066] The technical solutions of some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments that can be obtained by those skilled in the art based on some embodiments of this disclosure are within the scope of protection of this disclosure.

[0067] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0068] The following directional terms such as "up", "down", "left", and "right" may be defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and may change accordingly depending on the orientation of the components in the accompanying drawings.

[0069] The terms "first," "second," and other ordinal numbers are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0070] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0071] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0072] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0073] The use of “applies to” or “configured to” in this document implies open and inclusive language, which does not preclude applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of “based on” implies openness and inclusivity, because processes, steps, calculations, or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0074] In this document, “approximate” or “roughly” includes the values ​​stated and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation can be determined by considerations of a person skilled in the art regarding measurement errors and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system).

[0075] Furthermore, to clearly illustrate the multiple layers and regions in the accompanying drawings, the thickness of each layer has been enlarged to clearly show the relative positions between them. When a portion of a layer, film, region, plate, etc., is described as being "above" or "on" other portions, this description includes not only cases where it is "directly" above other portions, but also cases where other layers exist in between.

[0076] This disclosure provides a display device. The display device may be, for example, a mobile phone, a tablet computer, a computer, a smart wearable product (e.g., a smartwatch, a smart bracelet), a portable electronic device, a virtual reality (VR) terminal, an augmented reality (AR) terminal, etc. This disclosure does not impose any special limitations on the specific form of the aforementioned display device.

[0077] The display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0078] For ease of explanation, the following description uses display device 01 as an example. Figure 1 Taking the mobile phone shown as an example, in this case, the display device 01 includes at least a housing 11 and a display substrate 10 installed within the housing 11. The housing 11 typically also has a cavity for accommodating components such as a printed circuit board (PCB), battery, and camera. Figure 1(Not shown in the image).

[0079] Figure 2A for Figure 1 An enlarged schematic diagram of the display substrate 10 in the M0 region. Figure 2B This is a schematic diagram of the structure of a sub-pixel group in the display substrate 10. The following is combined with... Figure 2A and Figure 2B The example given is an AMOLED display substrate 10, but it is not limited to this.

[0080] In some embodiments, such as Figure 2A and Figure 2B As shown, the display substrate 10 includes a substrate 100 and a plurality of sub-pixel groups 200 located on the substrate 100. Each sub-pixel group may consist of a plurality of sub-pixels, and each sub-pixel includes a pixel electrode and an effective light-emitting area. For example, each sub-pixel group 200 includes a first color sub-pixel 210, a second color sub-pixel pair 220, and a third color sub-pixel 230 arranged along a first direction (the X direction shown in the figure). The second color sub-pixel pair 220 includes a first sub-pixel 22-1 and a second sub-pixel 22-2 arranged along a second direction (the Z direction shown in the figure) and emitting the same color. The effective light-emitting area of ​​the first color sub-pixel 210 is a first effective light-emitting area 2100. The effective light-emitting area of ​​the first sub-pixel 22-1 in the second color sub-pixel 220 is a first sub-effective light-emitting area 2201, and the effective light-emitting area of ​​the second sub-pixel 22-2 is a second sub-effective light-emitting area 2202. The effective light-emitting area of ​​the third color sub-pixel 230 is a third effective light-emitting area 2300.

[0081] The pixel electrode of the aforementioned sub-pixel includes an interconnected main body and a connecting part. For example... Figure 2B As shown, the pixel electrode 211 of the first color sub-pixel 210 includes an interconnected main body portion 2111 and a connecting portion 2112; the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 includes an interconnected main body portion 221-11 and a connecting portion 221-12; the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 includes an interconnected main body portion 221-21 and a connecting portion 221-22; and the pixel electrode 231 of the third color sub-pixel 230 includes an interconnected main body portion 2311 and a connecting portion 2312. Figure 2B It is understood that the main body of each pixel electrode has a shape that is approximately the same as the effective light-emitting area of ​​its respective sub-pixel, and the main body coincides with at least a portion of the boundary of the pixel electrode.

[0082] Please combine Figure 2B Understood, in some embodiments, such as Figure 2CAs shown, the plurality of sub-pixels on the substrate 100 include at least a first sub-pixel 22-1 and a second sub-pixel 22-2 with the same emission color. The areas of the orthographic projections of the two pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the substrate 100 are different. The orthographic projections of the connecting portion and the main body portion of at least one of the first sub-pixels 22-1 and the second sub-pixel 22-2 on a straight line extending along a first direction (e.g., the X direction) do not overlap at least partially. The orthographic projection of the pixel electrode of the second sub-pixel 22-2 on a straight line extending along a second direction (e.g., the Z direction) lies within the orthographic projection of the pixel electrode of the first sub-pixel 22-1 on the same straight line. Here, the second direction intersects the first direction, and the angle between them ranges from 80° to 100°. In this embodiment of the disclosure, multiple sub-pixels with the same emission color adopt two different structures as shown in the first sub-pixel 22-1 and the second sub-pixel 22-2. By designing the shape of the pixel electrode in the first sub-pixel 22-1 and the second sub-pixel 22-2, the overall layout design of the pixel circuit in the display substrate 10 can be effectively simplified while increasing the sub-pixel distribution density, thereby improving the light transmittance of the display substrate 10.

[0083] For ease of explanation, the following description assumes that the display substrate 10 adopts... Figure 2A The structure shown in the figure will be described in detail as an example.

[0084] Please continue reading. Figure 2A Multiple sub-pixel groups 200 are arranged along a first direction (e.g., the X direction) to form sub-pixel rows. These sub-pixel rows are arranged along a second direction (e.g., the Z direction), and the sub-pixel groups in any two adjacent rows are misaligned along the first direction; that is, any two adjacent sub-pixel rows have a certain offset along the first direction. Therefore, in any two adjacent sub-pixel rows, the subpixels configured to emit the same color light are not aligned in the second direction. Taking the arrangement of the second color sub-pixel pair 220 as an example... Figure 2A As shown, in any two adjacent rows of second color sub-pixel pairs 220 along the second direction, the second color sub-pixel pairs 220 of the second row R2 are misaligned with the second color sub-pixel pairs 220 of the first row R1 along the first direction, and the first row R1 and the second row R2 are arranged along the second direction.

[0085] Furthermore, in some examples, with the first direction as the row direction, the sub-pixel groups in the sub-pixel rows located in odd-numbered rows are arranged in the same way, and the sub-pixel groups in the sub-pixel rows located in even-numbered rows are arranged in the same way.

[0086] Optionally, the offset between two adjacent sub-pixels in the first direction is approximately half the size of the sub-pixel group 200 in the first direction. For example, the size of the sub-pixel group 200 in the first direction is the pitch of the sub-pixel group 200 in the first direction. Here, the pitch refers to the distance between the centers of the effective light-emitting areas of two first-color sub-pixels 210 in two adjacent sub-pixel groups 200 in the first direction. Here, the center of the effective light-emitting area refers to the geometric center of its orthographic projection shape on the substrate. The orthographic projection shape of the effective light-emitting area on the substrate 100 is approximately a regular shape, such as a symmetrical shape.

[0087] Furthermore, it is understood that the center involved in some embodiments of this disclosure refers to the geometric center of a regular shape and the approximate geometric center of an irregular shape. For example, a regular shape with a high similarity to the irregular shape is simulated, and then the geometric center of the simulated shape is taken as the center of the irregular shape.

[0088] The first and second directions intersect, and the included angle can range from 80° to 100°. For example, the first and second directions are two mutually perpendicular directions within the same plane. For example, this plane is the plane in which the sub-pixels are arranged, that is, a plane parallel to the substrate 100.

[0089] The aforementioned subpixel group is a repeating unit; its repetition refers only to the repetition of the subpixel arrangement, while other structural elements may differ or remain the same. Furthermore, this repetition means that the approximate position, shape, and size are roughly the same. In some cases, the shape may differ slightly for wiring or hole-making purposes, such as holes in different locations.

[0090] In some examples, the first color subpixel 210 is the red subpixel R. The first subpixel 22-1 and the second subpixel 22-2 in the second color subpixel pair 220 correspond to the green subpixels G1 and G2. The third color subpixel 230 is the blue subpixel B. However, this is not a limitation; the colors of the subpixels can be interchanged.

[0091] Understandably, please refer to Figure 3 In an AMOLED display substrate or a similar active-matrix display substrate, each sub-pixel includes a light-emitting device 0220 and a pixel circuit 0221 coupled to the light-emitting device 0220. The pixel circuit 0221 can drive the light-emitting device 0220 to emit light. The light-emitting device 0220 typically includes an anode, a light-emitting layer, and a cathode stacked sequentially. The electrode in the light-emitting device 0220 coupled to the pixel circuit 0221 is the pixel electrode of the corresponding sub-pixel, and this electrode is, for example, the anode. The following explanation uses the example of the pixel electrode being the anode.

[0092] For example, such as Figure 3As shown, the pixel circuit 0221 includes a driving circuit 0222, a first light-emitting control circuit 0223, a second light-emitting control circuit 0224, a data writing circuit 0225, a storage circuit 0226, a threshold compensation circuit 0227, and a reset circuit 0228. The driving circuit 0222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current to the light-emitting device 0220 to drive it to emit light.

[0093] The first light-emitting control circuit 0223 is coupled to the first voltage terminal VDD and the first terminal of the driving circuit 0222, respectively, and is configured to enable or disable the connection between the driving circuit 0222 and the first voltage terminal VDD. The second light-emitting control circuit 0224 is coupled to the second terminal of the driving circuit 0222 and the anode of the light-emitting device 0220, respectively, and is configured to enable or disable the connection between the driving circuit 0222 and the light-emitting device 0220. The data writing circuit 0225 is coupled to the first terminal of the driving circuit 0222 and is configured to write data signals to the storage circuit 0226 under the control of the gate scan signal. The storage circuit 0226 is coupled to the control terminal of the driving circuit 0222 and the first voltage terminal VDD, respectively, and is configured to store data signals. The threshold compensation circuit 0227 is coupled to the control terminal of the driving circuit 0222 and the second terminal of the driving circuit 0222, respectively, and is configured to perform threshold compensation on the driving circuit 0222. The reset circuit 0228 is coupled to the control terminal of the drive circuit 0222 and the anode of the light-emitting device 0220, and is configured to reset the control terminal of the drive circuit 0222 and the anode of the light-emitting device 0220 under the control of the reset control signal.

[0094] Optional, such as Figure 3 As shown, the driving circuit 0222 includes a driving transistor T1. The control terminal of the driving circuit 0222 is the control electrode of the driving transistor T1, the first terminal of the driving circuit 0222 is the first electrode of the driving transistor T1, and the second terminal of the driving circuit 0222 is the second electrode of the driving transistor T1. The data writing circuit 0225 includes a data writing transistor T2. The storage circuit 0226 includes a capacitor C. The threshold compensation circuit 0227 includes a compensation transistor T3. The first light-emitting control circuit 0223 includes a first light-emitting control transistor T4. The second light-emitting control circuit 0224 includes a second light-emitting control transistor T5. The reset circuit 0228 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0095] The first terminal of data writing transistor T2 is coupled to the first terminal of driving transistor T1. The second terminal of data writing transistor T2 is configured to be coupled to data line Vd to receive data signals. The control terminal of data writing transistor T2 is configured to be coupled to the first gate scan signal line Ga1 to receive scan signals. The first terminal of capacitor C is coupled to the first voltage terminal VDD. The second terminal of capacitor C is coupled to the control terminal of driving transistor T1. The first terminal of compensation transistor T3 is coupled to the second terminal of driving transistor T1. The second terminal of compensation transistor T3 is coupled to the control terminal of driving transistor T1. The control terminal of compensation transistor T3 is configured to be coupled to the second gate scan signal line Ga2 to receive compensation control signals. The first terminal of first reset transistor T6 is configured to be coupled to the first reset power supply terminal Vinit1 to receive the first reset signal. The second terminal of first reset transistor T6 is coupled to the control terminal of driving transistor T1. The control terminal of first reset transistor T6 is configured to be coupled to the first reset control signal line Rst1 to receive the first sub-reset control signal. The first terminal of the second reset transistor T7 is configured to be coupled to the second reset power supply terminal Vinit2 to receive the second reset signal. The second terminal of the second reset transistor T7 is coupled to the first electrode of the light-emitting device 0220. The control terminal of the second reset transistor T7 is configured to be coupled to the second reset control signal line Rst2 to receive the second sub-reset control signal. The first terminal of the first light-emitting control transistor T4 is coupled to the first voltage terminal VDD. The second terminal of the first light-emitting control transistor T4 is coupled to the first terminal of the driving transistor T1. The control terminal of the first light-emitting control transistor T4 is configured to be coupled to the first light-emitting control signal line EM1 to receive the first light-emitting control signal. The first terminal of the second light-emitting control transistor T5 is coupled to the second terminal of the driving transistor T1. The second terminal of the second light-emitting control transistor T5 is coupled to the anode of the light-emitting device 0220. The control terminal of the second light-emitting control transistor T5 is configured to be coupled to the second light-emitting control signal line EM2 to receive the second light-emitting control signal. The cathode of the light-emitting device 0220 is coupled to the second voltage terminal VSS.

[0096] Here, one of the first voltage terminal VDD and the second voltage terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, the first voltage terminal VDD is a voltage source that outputs a constant first voltage, which is a positive voltage. The second voltage terminal VSS is a voltage source that outputs a constant second voltage, which is a negative voltage, etc. Alternatively, for example, the first voltage terminal VDD is a power signal line, which may be, for example, a first power signal line and a second power signal line located on different layers and interconnected. The second voltage terminal VSS is grounded.

[0097] In some examples, the scan signal and the compensation control signal can be the same.

[0098] Optionally, the control electrode of the data write transistor T2 and the control electrode of the compensation transistor T3 are coupled to the same signal line, such as the first gate scan signal line Ga1, to receive the same signal (e.g., a scan signal). In this way, the second gate scan signal line Ga2 can be omitted in the display substrate, thereby reducing the total number of signal lines.

[0099] Optionally, the control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 are coupled to different signal lines, that is, the control electrode of the data writing transistor T2 is coupled to the first gate scan signal line Ga1, and the control electrode of the compensation transistor T3 is coupled to the second gate scan signal line Ga2. The first gate scan signal line Ga1 and the second gate scan signal line Ga2 transmit the same signal.

[0100] In other examples, the scan signal and the compensation control signal are different, so that the control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 can be controlled separately, thereby increasing the control flexibility of the pixel circuit.

[0101] Similarly, in some examples, the first light emission control signal and the second light emission control signal are the same.

[0102] Optionally, the control electrode of the first light-emitting control transistor T4 and the control electrode of the second light-emitting control transistor T5 are coupled to the same signal line, such as the first light-emitting control signal line EM1, to receive the same signal (e.g., the first light-emitting control signal). In this way, the second light-emitting control signal line EM2 can be omitted in the display substrate, thereby reducing the total number of signal lines.

[0103] Optionally, the control electrode of the first light-emitting control transistor T4 and the control electrode of the second light-emitting control transistor T5 are coupled to different signal lines. The control electrode of the first light-emitting control transistor T4 is coupled to the first light-emitting control signal line EM1, and the control electrode of the second light-emitting control transistor T5 is coupled to the second light-emitting control signal line EM2. The first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 transmit the same signal.

[0104] In other examples, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are transistors of different types; for example, the first light-emitting control transistor T4 is a P-type transistor, while the second light-emitting control transistor T5 is an N-type transistor. The first light-emitting control signal and the second light-emitting control signal are different, but the embodiments of this disclosure do not limit this.

[0105] Similarly, in some examples, the first sub-reset control signal and the second sub-reset control signal are the same.

[0106] Optionally, the control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are coupled to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this way, the second reset control signal line Rst2 can be omitted in the display substrate, thereby reducing the total number of signal lines.

[0107] Optionally, the control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are coupled to different signal lines. The control electrode of the first reset transistor T6 is coupled to the first reset control signal line Rst1, and the control electrode of the second reset transistor T7 is coupled to the second reset control signal line Rst2. The first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal.

[0108] In other examples, the first sub-reset control signal and the second sub-reset control signal may also be different.

[0109] Furthermore, in some examples, the second sub-reset control signal can be the same as the scan signal. For example, the control electrode of the second reset transistor T7 can be coupled to the first gate scan signal line Ga1 to receive the scan signal Ga1 as the second sub-reset control signal.

[0110] Furthermore, the first reset power supply terminal Vinit1, coupled to the first electrode of the first reset transistor T6, and the second reset power supply terminal Vinit2, coupled to the first electrode of the second reset transistor T7, can be DC reference voltage terminals to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same; for example, the first electrode of the first reset transistor T6 and the first electrode of the second reset transistor T7 can be connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to reset the control electrode of the driving transistor T1 and the anode of the light-emitting device 0220. This embodiment of the present disclosure does not impose any limitations on this. For example, the first electrode of the first reset transistor T6 and the first electrode of the second reset transistor T7 can be connected to the reset power supply signal line Init, respectively.

[0111] It should be noted that, Figure 3 The driving circuit 0222, data writing circuit 0225, storage circuit 0226, threshold compensation circuit 0227, and reset circuit 0228 in the pixel circuit 0221 shown are only illustrative. The specific structure of the driving circuit 0222, data writing circuit 0225, storage circuit 0226, threshold compensation circuit 0227, and reset circuit 0228 can be set according to actual application requirements, and the embodiments disclosed herein do not impose specific limitations on this.

[0112] For example, based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. For clarity, the embodiments of this disclosure use P-type transistors (e.g., P-type MOS transistors) as an example to illustrate the technical solutions of this disclosure. That is, in the description of the embodiments of this disclosure, the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7 can all be P-type transistors. However, the transistors in the embodiments of this disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of this disclosure according to actual needs.

[0113] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The first and second terminals of the transistor can be symmetrical in structure, so their physical structures can be indistinguishable. In the embodiments of this disclosure, the gate of the transistor is its control terminal, the first terminal is one of the source or drain, and the second terminal is the other of the source or drain. In the embodiments of this disclosure, the first and second terminals of all or some of the transistors can be interchanged as needed.

[0114] It should be noted that, in the embodiments of this disclosure, the pixel circuit 0221 can, in addition to being able to... Figure 3 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C or 9T2C structures. This disclosure does not limit the specific structure.

[0115] The pixel electrode of the light-emitting device 0220 is coupled to the pixel circuit 0221. Its shape can be designed according to actual needs to optimize the wiring design of the pixel circuit 0221 and ensure that each sub-pixel has a high distribution density, thereby improving the display effect of the display device.

[0116] In some embodiments, please refer to Figure 2B and Figure 4In at least two sub-pixels of sub-pixel group 200, such as the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220, the pixel electrode includes an interconnected main body portion and a connecting portion. The first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are: the closest first sub-pixel 22-1 and the closest second sub-pixel 22-2 among a plurality of first sub-pixels 22-1 and a plurality of second sub-pixels 22-2, and the first sub-pixel 22-1 and the second sub-pixel 22-2 are arranged along a second direction.

[0117] The shape of the aforementioned main body is approximately the same as the shape of the effective light-emitting area of ​​the light-emitting device 0220 to which it is located. Part of the edge of the main body is the corresponding edge of the pixel electrode, meaning that part of the boundary between the main body and its pixel electrode coincides. A notch is provided at the portion where the connecting part connects to the main body. For example, the main body includes a first side, a second side, and a third side connected sequentially, wherein the third side extends along a second direction; the second side connects to the connecting part, and there is a gap between the first side and the connecting part, meaning the first side does not connect to the connecting part. Thus, the area enclosed by a straight line connecting any point on the first side to any point on the edge of the connecting part extending along the second direction and far from the third side in the first direction, along with the main body and the connecting part, is the area where the notch is located, i.e., the notch area. Here, the first side, the second side, and the third side can be straight edges or folded edges; the distinction is made based on whether they connect to the connecting part.

[0118] Figure 2B Pixel electrodes of each sub-pixel and Figure 4 The pixel electrodes of sub-pixels of the same color have the same structure, but their shapes are slightly different. For example, Figure 2B The shapes of the connection parts of the pixels' electrodes are relatively regular. Figure 4 The shape of the connection portion of each pixel electrode has a large curvature. This disclosure does not limit this aspect.

[0119] For example, such as Figure 2B and Figure 4As shown, in the second color sub-pixel pair 220, the pixel electrode 221-1 of the first sub-pixel 22-1 includes a main body portion 221-11 and a connecting portion 221-12. The connecting portion 221-12 includes a bent portion 2-1 connected to the main body portion 221-11, and a compensation portion 2-2 connected to the bent portion 2-1. The main body portion 221-11, the bent portion 2-1, and the compensation portion 2-2 are integrally formed. The compensation portion 2-2 extends along a second direction. The maximum dimension D2max of the compensation portion 2-2 along the first direction is greater than the maximum dimension D1max of the bent portion 2-1 along the first direction. Here, the bent portion 2-1 is located between the main body portion 221-11 and the compensation portion 2-2, and the transition between it and the main body portion 221-11 and the compensation portion 2-2 can be smoothly processed. The maximum dimension of the bent portion 2-1 along the first direction is its cross-sectional dimension along the first direction. Thus, compared with the compensation part 2-2, the bending part 2-1 can have a smaller line width.

[0120] In the first sub-pixel 22-1, the main body portion 221-11 includes a first side a2-1, a second side b2-1, and a third side c2-1 connected sequentially. The third side c2-1 extends along the Z direction, the second side b2-1 is connected to the curved portion 2-1 in the connecting portion 221-12, and there is a gap between the first side a2-1 and the connecting portion 221-12. A straight line connecting any point on the first side a2-1 to any point on the edge of the connecting portion 221-12 that extends along the Z direction and is far away from the third side c2-1 in the X direction, together with the main body portion 221-11 and the connecting portion 221-12, forms a notch region 221-13.

[0121] Here, any point on the edge of the connecting part 221-12 that extends along the Z direction and is far away from the third side c2-1 in the X direction can be, for example, the end point of the curved part 2-1 that connects to the compensation part 2-2 and is far away from the third side c2-1 in the X direction; or the end point of the free end of the compensation part 2-2 that is far away from the third side c2-1 in the X direction; but it is not limited to this.

[0122] The smaller linewidth of the aforementioned curved portion 2-1 helps ensure a larger projected area of ​​the notch region 221-13 on the substrate 100. In some examples, the ratio of the projected area of ​​the notch region 221-13 on the substrate 100 to the projected area of ​​the curved portion 2-1 on the substrate 100 can range from 0.2 to 5. For example, the ratio of the projected area of ​​the notch region 221-13 on the substrate 100 to the projected area of ​​the curved portion 2-1 on the substrate 100 is one of 0.2, 1.5, 3, and 5. Thus, by providing a larger notch region 221-13 in the first sub-pixel 22-1, it is possible to avoid setting a metal pattern in the notch region 221-13, thereby improving the light transmittance of the display substrate 10.

[0123] The pixel electrode 221-2 of the second sub-pixel 22-2 and the pixel electrode 221-1 of the first sub-pixel 22-1 have different orthogonal projection areas on the substrate 100, and their structures correspond differently. For example, the two orthogonal projections of the connection portion and the main body portion of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on a straight line extending along the first direction do not overlap at least partially.

[0124] For example, such as Figure 2B and Figure 4 As shown, the pixel electrode 221-2 of the second sub-pixel 22-2 includes a main body 221-21 and a connecting part 221-22. The main body 221-21 and the connecting part 221-22 are an integral structure. The main body 221-21 includes a first side a2-2, a second side b2-2, and a third side c2-2 connected in sequence, wherein the third side c2-2 extends along the Z direction, the second side b2-2 is connected to the connecting part 221-22, and there is a gap between the first side a2-2 and the connecting part 221-22. At least one edge of the connecting part 221-22 can be bent, for example, the edge of the connecting part 221-22 away from the third side c2-2 in the X direction is bent. A straight line extending along the Z direction from any point on the first side a2-2 of the main body 221-21 to any point on the edge of the connecting portion 221-22 that is far away from the third side c2-1 in the X direction, together with the main body 221-21 and the connecting portion 221-22, forms a notch area 221-23. Similarly, by providing a notch area 221-23 in the second sub-pixel 22-2, it is possible to avoid setting a metal pattern in the notch area 221-23, thereby further improving the light transmittance of the display substrate 10.

[0125] Optional, please continue reading Figure 2B and Figure 4 The maximum dimension of the connecting portion 221-22 of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is less than or equal to the maximum dimension of the bent portion 2-1 of the pixel electrode 221-1 in the first sub-pixel 22-1 in the second direction. Thus, when the main body portion 221-21 of the pixel electrode 221-2 in the second sub-pixel 22-2 is approximately the same size as the main body portion 221-11 of the pixel electrode 221-1 in the first sub-pixel 22-1, the dimension of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is smaller than the dimension of the pixel electrode 221-1 in the first sub-pixel 22-1 in the same direction.

[0126] Please combine Figure 2AUnderstand that in any two adjacent rows of second color sub-pixel pairs 220 along a second direction (e.g., the Z direction), the second color sub-pixel pairs 220 of the second row R2 are misaligned with the second color sub-pixel pairs 220 of the first row R1 along a first direction (e.g., the X direction). The connection portion 221-12 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 extends between the pixel electrodes 221-2 of two correspondingly adjacent second sub-pixels 22-2 in the second color sub-pixel pair 220 of the first row R1. For example, the curved portion 2-1 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 and the connection portion 221-22 of the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 of the second row R1 are approximately located on a straight line extending along the first direction. The compensation portion 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 is located between the main portions 221-21 of the pixel electrodes 221-2 of two adjacent second sub-pixels 22-2 in the second color sub-pixel pair 220 of the first row R1. Thus, the orthographic projection of the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 of the first row R1 onto a straight line extending along the second direction, and the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2, lie within the orthographic projection of the same straight line.

[0127] Please combine Figure 5 It is understood that the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are designed as described above, which facilitates the side-by-side arrangement of four pixel circuits 0221 along the first direction within the space corresponding to each sub-pixel group 200. This simplifies the overall layout design of the pixel circuits 0221 in the display substrate 10 while increasing the sub-pixel distribution density.

[0128] In some embodiments, the pixel electrode 211 of the first color sub-pixel 210 and the pixel electrode 231 of the third color sub-pixel 230 may also refer to the structural design of the pixel electrode 221-2 in the second sub-pixel 22-2 described above.

[0129] For example, such as Figure 2B and Figure 4As shown, the pixel electrode 211 of the first color sub-pixel 210 includes an interconnected main body portion 2111 and a connecting portion 2112. The main body portion 2111 and the connecting portion 2112 are an integral structure. The main body portion 2111 includes a first side a1-1, a second side b1-1, and a third side c1-1 connected in sequence, wherein the third side c1-1 extends along the Z direction, the second side b1-1 is connected to the connecting portion 2112, and there is a gap between the first side a1-1 and the connecting portion 2112. At least one edge of the connecting portion 2112 can be curved, for example, the edge of the connecting portion 2112 that is curved away from the third side c1-1 in the X direction. A straight line connecting any point on the first side a1-1 of the main body portion 2111 to any point on the edge of the connecting portion 2112 that extends along the Z direction and is away from the third side c1-1 in the X direction, together with the main body portion 2111 and the connecting portion 2112, forms a notch region 2113.

[0130] For example, such as Figure 2B and Figure 4 As shown, the pixel electrode 231 of the third color sub-pixel 230 includes an interconnected main body portion 2311 and a connecting portion 2312. The main body portion 2311 and the connecting portion 2312 are an integral structure. The main body portion 2311 includes a first side a3-1, a second side b3-1, and a third side c3-1 connected in sequence, wherein the third side c3-1 extends along the Z direction, the second side b3-1 is connected to the connecting portion 2312, and there is a gap between the first side a3-1 and the connecting portion 2312. At least one edge of the connecting portion 2312 can be curved, for example, the edge of the connecting portion 2312 away from the third side c3-1 in the X direction is curved. A straight line connecting any point on the first side b3-1 of the main body portion 2311 to any point on the edge of the connecting portion 2312 extending along the Z direction and away from the third side c3-1 in the X direction, together with the main body portion 2311 and the connecting portion 2312, forms a notch region 2313.

[0131] Therefore, by setting a notch area 2113 in the first color sub-pixel 210 and a notch area 2313 in the third color sub-pixel 230, the light transmittance of the display substrate 10 can be further improved.

[0132] In addition, such as Figure 2BAs shown, in each subpixel group 200, the connecting portion 2112 in the first color subpixel 210 is located on the side of its main body 2111 closer to the second color subpixel pair 220. The anode areas of the first subpixel 22-1 and the second subpixel 22-2 in the second color subpixel pair 220 are different. The connecting portions 221-12 and 221-22 in the second color subpixel pair 220 are respectively located on the side of their main body away from the first color subpixel 210. For example, the projections of the connecting portion and the main body of at least one of the first subpixels 22-1 and 22-2 on a straight line extending along the first direction do not overlap at least partially. The orthographic projection of the connecting portion 2312 in the third color subpixel 230 on a straight line extending along the first direction lies within the orthographic projection of its main body 2311 on the same straight line. For example, the center line of the third effective light-emitting area 2300 of the third color subpixel 230 along the second direction passes through its main body 2311 and the connecting portion 2312.

[0133] In each sub-pixel group 200, the shape of the main body of the pixel electrode of each sub-pixel is approximately the same as the shape of the corresponding effective light-emitting area, and the orthographic projection area of ​​the main body of the pixel electrode of each sub-pixel on the substrate 100 is larger than the orthographic projection area of ​​the corresponding effective light-emitting area on the substrate 100. For example, the geometric center of the main body of the pixel electrode of each sub-pixel approximately coincides with the geometric center of the corresponding effective light-emitting area. For example, the main body 2111 of the pixel electrode 211 of the first color sub-pixel 210 and the main body 2311 of the pixel electrode 231 of the third color sub-pixel 230 are approximately hexagonal or elliptical, and the main body of the pixel electrode of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are approximately pentagonal, circular, or teardrop-shaped.

[0134] In some embodiments, multiple pixel circuits 0221 are arranged in a row along a first direction and in a column along a second direction. Each transistor in the pixel circuit 0221 employs a top-gate structure, and some transistors may also be dual-gate structures, such as compensation transistor T3 and first reset transistor T6. However, this is not the only limitation. The following uses this as an example to illustrate the layer structure of the display substrate 10. When other transistor structures are used, the layer structure of the display substrate 10 can be adaptively adjusted accordingly.

[0135] Figure 5 This is a schematic diagram of the top view structure of multiple sub-pixels in some embodiments of this disclosure. Figures 6A to 6IThis is a schematic diagram of the top-down structure of some layers during the sub-pixel fabrication process. It takes four adjacent pixel circuits corresponding to the first color sub-pixel 210, the second sub-pixel 22-2 in the second color sub-pixel pair 220, the third color sub-pixel 230, and the first sub-pixel 22-1 in another second color sub-pixel pair 220 that are adjacent and staggered as an example. The position of each transistor in the pixel circuit 0221 included in a sub-pixel is shown. The components included in the pixel circuit 0221 in other sub-pixels are roughly in the same position as the transistors included in the sub-pixel.

[0136] Furthermore, the display substrate 10 typically includes multiple layers located between the substrate 100 and the pixel electrode, wherein the multiple layers include at least one metal layer and at least one insulating layer. For the structure of each layer in the display substrate 10, please refer to... Figures 7A to 7G The layer structure shown is illustrated in cross-sectional view. This disclosure provides a schematic embodiment of the layer structure of a display substrate 10, but is not limited thereto. Depending on the pixel circuit structure, the layer structure of the display substrate 10 can be adapted.

[0137] As shown in Figure 5, the pixel circuit 0221 includes the following: Figure 4 The diagram shows a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a capacitor C; wherein the capacitor C overlaps with the driving transistor T1, but is not marked.

[0138] Figure 6A The diagram shows a top view of a semiconductor patterned layer 310 in a display substrate 10. The semiconductor patterned layer 310 can be formed by patterning a semiconductor material. The semiconductor patterned layer 310 can be used to fabricate the active layers of the aforementioned driving transistor T1, data writing transistor T2, compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7. The semiconductor patterned layer 310 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of each transistor in each sub-pixel, and the active layer pattern and doped region pattern of each transistor in the same pixel circuit are integrally formed.

[0139] It should be noted that the active layer may include an integrally formed low-temperature polycrystalline silicon layer, whose source and drain regions can be conductive through doping or other methods. Thus, the active layer of each transistor in each sub-pixel is a monolithic pattern formed from p-silicon. Each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern, with the active layers of different transistors separated by doped structures.

[0140] For example, the semiconductor pattern layer 310 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0141] For example, the active semiconductor layers in the pixel circuits of sub-pixels of different colors arranged along the first direction are not connected and are disconnected from each other. The active semiconductor layers in the pixel circuits of sub-pixels arranged along the second direction can be integrally formed or disconnected from each other.

[0142] Figure 6B The diagram shows a top view of a first gate metal layer 320 in a display substrate 10. The first gate metal layer 320 is a patterned metal thin film. A gate insulating layer 160 is formed on a semiconductor patterned layer 310. The first gate metal layer 320 is located on the gate insulating layer 160 and is insulated from the semiconductor patterned layer 310.

[0143] For example, the first gate metal layer 320 is used to fabricate the gate of each of the above-mentioned driving transistor T1, data writing transistor T2, compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6 and second reset transistor T7, as well as the first terminal CC1 of capacitor C.

[0144] Here, the scan signal lines Ga (including the first gate scan signal line Ga1 and the second gate scan signal line Ga2), reset control signal lines Rst (including the first reset control signal line Rst1 and the second reset control signal line Rst2), and light emission control signal lines EM (including the first light emission control signal line EM1 and the second light emission control signal line EM2) that are coupled to the gates of each transistor in the pixel circuit 0221 can also be formed by the first gate metal layer 320.

[0145] In some examples, the first gate scan signal line Ga1 and the second gate scan signal line Ga2 are the same signal line Ga, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line Rst, and the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same signal line EM, but not limited to these.

[0146] For example, the display substrate 10 further includes a plurality of signal lines extending along a first direction. The orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 onto the substrate overlaps with the orthographic projections of at least three signal lines located on the same layer onto the substrate 100. For example, a reset control signal line, a gate scan signal line, and a light emission control signal line are disposed on the same layer, all extending along the first direction and arranged along a second direction. The orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 onto the substrate overlaps with the orthographic projections of a reset control signal line, a gate scan signal line, and a light emission control signal line onto the substrate 100.

[0147] For example, such as Figure 6B As shown in the dashed boxes, the gate of the data writing transistor T2 can be the portion where the scan signal line Ga overlaps with the semiconductor pattern layer 310. The gate of the first light-emitting control transistor T4 can be the first portion where the light-emitting control signal line EM overlaps with the semiconductor pattern layer 310, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line EM overlaps with the semiconductor pattern layer 310. The gate of the first reset transistor T6 is the first portion where the reset control signal line Rst overlaps with the semiconductor pattern layer 310. The gate of the second reset transistor T7 is the second portion where the reset control signal line Rst overlaps with the semiconductor pattern layer 310. The threshold compensation transistor T3 can be a dual-gate thin-film transistor. The first gate of the threshold compensation transistor T3 can be the portion where the scan signal line Ga overlaps with the semiconductor pattern layer 310, and the second gate of the threshold compensation transistor T3 can be the portion where the protruding structure P protruding from the scan signal line Ga overlaps with the semiconductor pattern layer 310. Figure 3 As can be understood, the gate of the driving transistor T1 can be the first terminal CC1 of the capacitor C.

[0148] It should be noted that the portion of the semiconductor pattern layer 310 that is directly opposite the gate of the transistor is the channel of the transistor. The semiconductor pattern portions on both sides of each channel are conductive through processes such as ion doping, and can serve as the first and second electrodes of the corresponding transistor.

[0149] In addition, for example Figure 6BAs shown, the scan signal line Ga, reset control signal line Rst, and light emission control signal line EM are arranged along a first direction (X direction). The scan signal line Ga is located between the reset control signal line Rst and the light emission control signal line EM. Thus, for each pixel circuit 0221, in a second direction, the first terminal CC1 of capacitor C (i.e., the gate of driving transistor T1) is located between the scan signal line Ga and the light emission control signal line EM. The protruding structure P protruding from the scan signal line Ga is located on the side of the scan signal line Ga away from the light emission control signal line EM. The gates of data writing transistor T2, threshold compensation transistor T3, first reset transistor T6, and second reset transistor T7 are all located on the first side of the gate of driving transistor T1. The gates of first light emission control transistor T4 and second light emission control transistor T5 are both located on the second side of the gate of driving transistor T1.

[0150] Here, the first side and the second side of the gate of driving transistor T1 are two opposing sides of the gate of driving transistor T1 in the second direction. For example, in the XZ plane, the first side of the gate of driving transistor T1 can be the upper side of the gate of driving transistor T1, and the second side of the gate of driving transistor T1 can be the lower side of the gate of driving transistor T1. Optionally, the side of the display substrate used for bonding the IC is the lower side of the display substrate, and the lower side of the gate of driving transistor T1 is the side closer to the IC. The upper side of the gate of driving transistor T1 is the opposite side of its lower side, for example, the side of the gate of driving transistor T1 further away from the IC.

[0151] For each pixel circuit 0221, in the first direction, the gate of the data writing transistor T2 and the gate of the first light-emitting control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second light-emitting control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. Here, the third and fourth sides of the gate of the driving transistor T1 are two opposite sides of the gate of the driving transistor T1 in the first direction X. For example, in Figure 6B In the XZ plane shown, the third side of the gate of the driving transistor T1 can be the left side of the gate of the driving transistor T1, and the fourth side of the gate of the driving transistor T1 can be the right side of the gate of the driving transistor T1.

[0152] It should be added that the structure of pixel circuit 0221 can be... Figure 6B The mirror structure shown, i.e., the layer structure of pixel circuit 0221, is based on the channel region of driving transistor T1, with the left and right sides of the structure flipped. Therefore, the relationship between the left and right sides of the gate can be reversed.

[0153] Figure 6C The diagram shows a top view of a second gate metal layer 330 in the display substrate 10. The second gate metal layer 330 is a patterned metal thin film. A first interlayer insulating layer 150 is formed on the aforementioned first gate metal layer 320. The second gate metal layer 330 is located on the first interlayer insulating layer 150 and is insulated from the first gate metal layer 320.

[0154] For example, the second gate metal layer 330 is used to fabricate the second electrode CC2 of capacitor C, the reset power signal line Init, and the light-shielding portion S. The second electrode CC2 of capacitor C and the orthographic projection of the first electrode CC1 of capacitor C on the substrate 100 at least partially overlap to form capacitor C. Optionally, the second electrode CC2 of capacitor C has an opening, the orthographic projection of which on the substrate 100 lies within the orthographic projection of the first electrode CC1 of capacitor C on the substrate 100; the orthographic projection of the portion of the second electrode CC2 of capacitor C other than the opening on the substrate 100 overlaps with the portion of the orthographic projection of the first electrode CC1 of capacitor C on the substrate 100.

[0155] In addition, for example, such as Figure 6C As shown, the second terminal CC2 of capacitor C is formed by the second gate metal layer 330. In this way, by interconnecting the second terminals CC2 of each capacitor C in the same row of pixel circuits 0221, the resistance of the corresponding metal interconnects in the second gate metal layer 330 can be reduced, thereby reducing the voltage drop (IR DROP) of the power supply voltage.

[0156] Furthermore, in some examples, the compensation transistor T3 employs a dual-gate transistor. The semiconductor pattern portion between its two channels is in a floating state when the compensation transistor T3 is off, making it susceptible to voltage fluctuations from surrounding lines. This can affect the leakage current of the compensation transistor T3, thereby impacting its luminous brightness. To maintain voltage stability in the semiconductor pattern portion between the two channels of the compensation transistor T3, a light-shielding portion S is designed to form a capacitor with the semiconductor pattern portion between the two channels of the compensation transistor T3. Connecting the light-shielding portion S to a second power signal line provides a constant voltage, ensuring that the voltage of the floating semiconductor pattern portion remains stable. The overlapping of the orthographic projection of the light-shielding portion S onto the substrate 100 with the orthographic projection of the semiconductor pattern portion between the two channels of the compensation transistor T3 onto the substrate 100 further prevents changes in the electrical characteristics of the semiconductor pattern portion due to illumination.

[0157] For example, a second interlayer insulating layer 140 and a first metal layer are sequentially stacked on the second gate metal layer 330 in a direction away from the substrate 100. Figure 6D The diagram shows a top view of a first metal layer 340 in the display substrate 10. Figure 6E The distribution of multiple vias required to achieve electrical connection between the first metal layer 340 and the semiconductor pattern layer 310, the first gate metal layer 320, and the second gate metal layer 330 is shown. Figure 6E' The first metal layer 340 and are shown. Figure 6E The relative positions of the vias are defined. The first metal layer 340 is a patterned metal thin film. The first metal layer 340 can be used to fabricate the data line Vd, the second power signal line 500, the first adapter electrode 341, the second adapter electrode 342, and the driving electrode 343. The data line Vd and the second power signal line 500 both extend along the second direction, and there is a gap between the data line Vd and the second power signal line 500 corresponding to the same pixel circuit 0221.

[0158] like Figure 6D , Figure 6E and Figure 6E' As shown, the data line Vd is electrically connected to the second terminal T2-2 of the data writing transistor T2 through a via 381 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140. The second power signal line 500 is electrically connected to the first terminal T4-1 of the first light-emitting control transistor T4 through a via 382 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140. The second power signal line 500 and the data line Vd are alternately arranged along a first direction. The second power signal line 500 is electrically connected to the second terminal CC2 of the capacitor C through a via 3831 penetrating the second interlayer insulating layer 140. The second power signal line 500 is electrically connected to the light-shielding part S through a via 3832 penetrating the second interlayer insulating layer 140 to provide a constant voltage to the light-shielding part S. One end of the first transition electrode 341 is electrically connected to the second electrode of the compensation transistor T3 through a via 384 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140. The other end of the first transition electrode 341 is electrically connected to the gate of the driving transistor T1 (i.e., the first electrode CC1 of the capacitor C) through a via 385 penetrating the first interlayer insulating layer 150 and the second interlayer insulating layer 140. One end of the second transition electrode 342 is electrically connected to the reset power signal line Init through a via 386 penetrating the second interlayer insulating layer 140. The other end of the second transition electrode 342 is electrically connected to the first electrode of the second reset transistor T7 through a via 387 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140. The driving electrode 343 is electrically connected to the second electrode of the second light-emitting control transistor T5 through a via 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140.

[0159] In some examples, such as Figure 6E'As shown, the data line Vd includes a body 610 extending along a second direction and a protrusion 620 protruding towards the corresponding pixel circuit 0221 in a first direction. Optionally, the overlapping area of ​​the orthographic projection of the via 381 on the substrate 100 and the orthographic projection of the protrusion 620 on the substrate 100 can be 70% to 100% of the orthographic projection area of ​​the via 381 on the substrate 100, for example, 70%, 80%, or 100%. That is to say, the electrical connection between the data line Vd and the pixel circuit 0221 is mainly achieved through the electrical connection between its protrusion 620 and the pixel circuit 0221. In this way, even when the line width of the data line Vd body 610 is relatively narrow, the protrusion 620 can be used to ensure a good electrical connection between the data line Vd and the pixel circuit 0221.

[0160] For example, a passivation layer 123 and a first planarization layer 122 may be sequentially stacked on the first metal layer 340 in a direction away from the substrate 100 to provide insulating protection for the first metal layer 340. However, this is not a limitation. For example, the positions of the passivation layer 123 and the first planarization layer 122 may be interchanged; or, the side of the first metal layer 340 away from the substrate 100 may only have the first planarization layer 122, without the passivation layer 123.

[0161] The following description takes the example of a passivation layer 123 and a first planarization layer 122 stacked on the first metal layer 340, with the first planarization layer 122 located on the side of the passivation layer 123 away from the substrate 100.

[0162] For example, a second metal layer is formed on the first planarization layer 122. Figure 6F The diagram shows a top view of a second metal layer 350 in the display substrate 10. Figure 6G The distribution of the plurality of vias required to achieve electrical connection between the second metal layer 350 and the first metal layer 340 is shown. Figure 6G' The second metal layer 350 and are shown. Figure 6G The relative positions of the vias are defined. The second metal layer 350 is a patterned metal thin film. The second metal layer 350 can be used to fabricate the first power signal line 400 and the connection electrode 450. The connection electrode 450 is disposed in a one-to-one correspondence with the drive electrode 343 in the first metal layer 340, and the connection electrode 450 is electrically connected to the drive electrode 343 through the vias 352 penetrating the first planarization layer 122 and the passivation layer 123.

[0163] For example, a second planarization layer 121 and a pixel electrode layer 360 are sequentially stacked on the second metal layer 350 in a direction away from the substrate 100. Figure 6H The distribution of multiple vias in the second planarization layer 121 is shown. Figure 6H'The relative positions between the vias in the second metal layer 350 and the second planarization layer 121 are shown. Figure 6I The distribution of each pixel electrode in the pixel electrode layer 360 is shown. Figure 6I' The positional relationship between the pixel electrode layer 360, the second metal layer 350, and the first via H1 and the second via H2 is shown. Here, the first via H1 is a via 1210 penetrating the second planarization layer 121. The second via H2 is a via 352 penetrating the first planarization layer 122 and the passivation layer 123. The pixel electrode layer 360 is a patterned metal thin film. The pixel electrode layer 360 can be used to fabricate the pixel electrode in each sub-pixel. According to the arrangement of each sub-pixel in the aforementioned sub-pixel group 200, the structure of the pixel electrode in each sub-pixel is as described above. The pixel electrode is electrically connected to the connecting electrode 450 through the via 1210 penetrating the second planarization layer 121.

[0164] In some embodiments, please combine Figure 2A and Figure 6I' Understanding that the orthographic projections of the first vias H1 corresponding to multiple pixel circuits located in the same row along the first direction on the substrate 100 extend along the first straight line L1. The orthographic projections of the multiple second vias H2 corresponding to multiple pixel circuits located in the same row along the first direction on the substrate 100 extend along the second straight line L2. The effective light-emitting area 2201 of the first sub-pixel 22-1 and the effective light-emitting area 2202 of the second sub-pixel 22-2 corresponding to multiple pixel circuits located in the same row along the first direction are respectively located on both sides of the first straight line L1. There is a gap D2 between the orthographic projections of the first vias H1 and the second vias H2 corresponding to the same connecting electrode 450 on the substrate. Thus, during the fabrication of the second via H2, the connecting electrode 450, and the first via H1, problems such as the overlapping of the orthographic projections of the first via H1 and the second via H2 on the substrate 100 can be avoided. For example, the second metal layer 350 may be recessed at the second via H2, the second planarization layer 121 may not be completely etched, and the pixel electrode layer 360 may be recessed at the first via H1. This helps to ensure the flatness of the pixel electrode in the pixel electrode layer 360 and the electrical connection performance between the pixel electrode and the connecting electrode 450, thereby improving the display effect of the display substrate.

[0165] It should be added that the passivation layer 123 and the first planarization layer 122 are sequentially stacked on the surface of each transistor away from the substrate. The second via H2 penetrates the first planarization layer 122 and the passivation layer 123, and has a certain depth. After the second metal layer 350 is formed, the second metal layer 350 is prone to depression at the second via H2. The second planarization layer 121 is formed on the surface of the second metal layer 350 away from the substrate 100, and the second planarization layer 121 is usually difficult to completely fill the depression of the second metal layer 350 at the second via H2. Therefore, if the orthographic projections of the first via H1 and the second via H2 formed in the second planarization layer 121 on the substrate 100 overlap, it can easily lead to a relatively serious sinking problem of the pixel electrode in the subsequent pixel electrode layer 360 at the first via H1. The embodiments of this disclosure can effectively improve the above problem by setting a gap D2 between the orthographic projections of the first via H1 and the second via H2 on the substrate.

[0166] In addition, such as Figure 2A and Figure 6I' As shown, optionally, the orthographic projections of the first vias H1 corresponding to multiple pixel circuits located in the same column along the second direction on the substrate 100 are arranged along the third straight line L3. Optionally, the orthographic projections of the first vias H1 and the second vias H2 corresponding to the same connecting electrode 450 on the substrate 100 are arranged along the third straight line L3. Thus, the first vias H1 and the second vias H2 are distributed in an array in the display substrate 10, which facilitates fabrication and simplifies the layout design of the corresponding mask.

[0167] Understandably, in some examples, the orthographic projection of the first via H1 onto the substrate 100 and the orthographic projection of the second via H2 onto the substrate 100 have approximately the same shape and area. Here, the shapes of the first via H1 and the second via H2 can be regular rectangles or circles, which facilitates determining the overlap area between the connecting electrode 450 and the pixel electrode, and between the connecting electrode 450 and the driving electrode 343, so as to ensure that the connection lines between the pixel electrode and the pixel circuit (e.g., the connecting electrode 450 and the driving electrode 343) have a small resistance value.

[0168] In some embodiments, the orthographic projections of the connecting electrode 450 and the driving electrode 343 on the substrate 100 have approximately the same shape. Optionally, the area of ​​the orthographic projection of the connecting electrode 450 on the substrate 100 is larger than the area of ​​the orthographic projection of the driving electrode 343 on the substrate 100. For example, the orthographic projection of the driving electrode 343 on the substrate 100 lies within the corresponding orthographic projection of the connecting electrode 450 on the substrate 100, and a portion of their orthographic projection boundaries overlap or substantially overlap. For example, the orthographic projections of the connecting electrode 450 and the driving electrode 343 on the substrate 100 have a non-overlapping portion, and the orthographic projection of the first via H1 on the substrate 100 overlaps with the non-overlapping portion. This facilitates the arrangement of the first via H1 and the second via H2 along a straight line in the first and second directions, reasonably improving the space utilization of the display substrate, so that the display substrate has a high light transmittance.

[0169] In some embodiments, please combine Figure 6I' and Figure 8 Understanding that the driving electrode 343 is electrically connected to the second electrode of the second light-emitting control transistor T5 through a via 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140. Taking this via 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 as the third via H3, the second via H2, and the first via H1 corresponding to the same driving electrode 343, there is a gap between each pair of their three orthogonal projections on the substrate 100.

[0170] Optionally, the distance B1 between the orthographic projection of either the first via H1 or the second via H2 onto the substrate 100 and the effective light-emitting area of ​​the corresponding sub-pixel is greater than 2 μm, and its value range is, for example, 2 μm to 20 μm. For example,... Figure 8 As shown, the distance B1 between the orthogonal projection of either the first via H1 or the second via H2 onto the substrate 100 and the effective light-emitting area K of the corresponding sub-pixel is greater than or equal to 2.5 μm.

[0171] Optionally, the minimum interval between the orthographic projection of at least one of the first via H1 and the second via H2 onto the substrate 100 and the orthographic projection of the corresponding third via H3 onto the substrate 100 is greater than 0.8 μm, and its value range is, for example, 0.8 μm to 10 μm. The minimum interval between the orthographic projections of the first via H1 and the second via H2 onto the substrate 100 is greater than 1 μm, and its value range is, for example, 1 μm to 10 μm. For example, as... Figure 8As shown, the minimum interval B2 between the orthographic projection of the first via H1 on the substrate 100 and the orthographic projection of the corresponding second via H2 on the substrate 100 is 1.2 μm; the minimum interval B3 between the orthographic projection of the second via H2 on the substrate 100 and the orthographic projection of the corresponding third via H3 on the substrate 100 is 0.9 μm. The first via H1 and the second via H2 are arranged along a straight line in the second direction, and the minimum interval between the orthographic projection of the first via H1 on the substrate 100 and the orthographic projection of the corresponding third via H3 on the substrate 100 is 2.1 μm (0.9 μm + 1.2 μm).

[0172] During the fabrication of the third via H3, the driving electrode 343, and the second via H2, problems such as the overlapping of the orthographic projections of the second via H2 and the third via H3 on the substrate 100 can be avoided. For example, the first metal layer 340 may be recessed at the third via H3, the passivation layer 123 and the first planarization layer 122 may not be completely etched, and the connecting electrode 450 may be recessed at the second via H2. This helps to ensure the flatness of the connecting electrode 450 and the electrical connection performance between the connecting electrode 450 and the driving electrode 343, thereby improving the display effect of the display substrate.

[0173] Alternatively, the orthographic projection shape of the third via H3 on the substrate 100 can be approximately the same as the shapes of the first via H1 and the second via H2. For example, the shape of the third via H3 can be a regular rectangle or a circle.

[0174] Optionally, the orthographic projections of the third vias H3 corresponding to multiple pixel circuits located in the same column along the second direction on the substrate 100 extend along the same straight line.

[0175] Optionally, the orthographic projections of the third vias H3 corresponding to multiple pixel circuits located in the same row along the first direction on the substrate 100 extend along the same straight line.

[0176] Thus, in some embodiments, multiple third vias H3 are arranged in an array in the display substrate 10, which not only facilitates manufacturing but also makes it easier to design the relative distribution positions between them and the second vias H2 and the first vias H1, so as to reasonably improve the space utilization of the display substrate and make the display substrate have high light transmittance.

[0177] Furthermore, in some embodiments, a via 381 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 is designated as the fourth via H4. The orthographic projections of the fourth via H4 corresponding to multiple pixel circuits located in the same column along the second direction onto the substrate 100 can extend and be arranged along the same straight line to facilitate fabrication and reasonably improve the space utilization of the display substrate, thereby enabling the display substrate to have higher light transmittance.

[0178] In some embodiments, such as Figure 6G' As shown, the first power signal line 400 includes multiple first sub-power signal lines 410 extending along a first direction and multiple second sub-power signal lines 420 extending along a second direction. The first sub-power signal lines 410 and the second sub-power signal lines 420 are interconnected. That is, the first power signal lines 400 are distributed in a grid pattern.

[0179] Please combine Figure 5 and Figure 6G' It is understood that within the same second color sub-pixel pair 220, there is a gap between the effective light-emitting area of ​​the first sub-pixel 22-1 and the effective light-emitting area of ​​the second sub-pixel 22-2. The orthographic projection of the first sub-power signal line 410 onto the substrate 100 passes through the gap between the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2. This means that within the same second color sub-pixel pair 220, the orthographic projection of the gap between the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 onto a straight line extending along the second direction does not overlap with the orthographic projection of the effective light-emitting areas in the second color sub-pixel pair onto the same straight line.

[0180] In some examples, the center of the orthographic projection of at least one of the first effective light-emitting area 2100 of the first color sub-pixel 210 and the third effective light-emitting area 2300 of the third color sub-pixel 230 onto the substrate 100 is located within the orthographic projection of the first sub-power signal line 410 onto the substrate 100. That is, the first sub-power signal line 410 can serve as the center of symmetry between the first effective light-emitting area 2100 and the third effective light-emitting area 2300, so that the portions of the first effective light-emitting area 2100 and the third effective light-emitting area 2300 located on both sides of the first sub-power signal line 410 have a consistent application environment, thereby ensuring that the light intensity emitted from the first effective light-emitting area 2100 and the third effective light-emitting area 2300 is uniform, thus improving color shift.

[0181] In some examples, the ratio of the two distances between the orthographic projections of the two effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the substrate and the orthographic projection of the corresponding first sub-power signal line 410 on the substrate 100 in the same second color sub-pixel pair 220 ranges from 0.9 to 1.1. That is, in the same second color sub-pixel pair 220, the distances from the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 to the same first sub-power signal line 410 are approximately the same. For example, the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 are symmetrically arranged with the first sub-power signal line 410 as the center. In this way, the two effective light-emitting areas in the second color sub-pixel pair 220 not only have the same light-emitting area, but also have a consistent application environment relative to the first sub-power signal line 410, so as to improve color shift.

[0182] At least one second sub-power signal line 420 has a break 421, meaning the second sub-power signal line 420 is not a continuous signal line. The second sub-power signal line 420 comprises multiple signal segments that are disconnected from each other, and the interval between any two adjacent signal segments along its extension direction is the aforementioned break 421. The effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220, and their interval, are located at this break 421. For example, the orthographic projection of the second sub-power signal line 420 on the substrate 100, the orthographic projection of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2, and their interval, which do not penetrate the first sub-pixel 22-1 and the second sub-pixel 22-2, on the substrate 100. The orthographic projection of the virtual connection between the two endpoints of the break 421 in the second direction on the substrate 100, and the orthographic projection of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2, and their interval, on the substrate 100.

[0183] Optionally, the second sub-power signal line 420 with the break 421 does not overlap with the orthographic projection of the two effective light-emitting areas and their interval in the corresponding second color sub-pixel pair on the substrate.

[0184] Optionally, the orthographic projection of the first power signal line 400 onto the substrate 100 does not overlap with the orthographic projection of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 onto the substrate 100. That is, the orthographic projection of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 onto the substrate 100 may overlap with the orthographic projection of the corresponding break 421 in the second sub-power signal line 420 onto the substrate 100, but it does not overlap with the orthographic projections of the solid portions of the first sub-power signal line 410 and the second sub-power signal line 420 onto the substrate 100. This helps improve the flatness of the film layer located within the effective light-emitting area and on the side of the pixel electrode away from the substrate 100 in the second color sub-pixel pair 220, thereby minimizing color shift during display of the second color sub-pixel pair 220.

[0185] Furthermore, the second sub-power signal line 420 and the second power signal line 500 extend in the same direction. The second sub-power signal line 420 is electrically connected to the second power signal line 500 through a via 352 penetrating the first planarization layer 122 and the passivation layer 123. This allows the second power signal line 500 to be connected in parallel with the first power signal line 400, thereby reducing the resistance of the metal interconnects in the second metal layer 350 and thus reducing the voltage drop (IR DROP) of the power supply voltage.

[0186] Optionally, the orthographic projections of the second power signal line 500 and the second sub-power signal line 420 coupled thereto on the substrate 100 at least partially overlap. The orthographic projection of the second power signal line 500 on the substrate 100 partially overlaps with the orthographic projections of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the substrate 100. For example, the orthographic projection of the second sub-power signal line 420 on the substrate 100 lies within the orthographic projection of the second power signal line 500 on the substrate 100. For example, the second power signal line 500 may substantially coincide with the portion of the second sub-power signal line 420 except for the break 421, but the linewidth of the second sub-power signal line 420 is partially adjusted and does not completely coincide with the second power signal line 500. For example, the area of ​​the overlapping portion of the second power signal line 500 and the second sub-power signal line 420 accounts for more than 70% of the orthographic projection area of ​​the second power signal line 500 on the substrate 100.

[0187] Optionally, the width of the second sub-power signal line 420 in the first direction may vary slightly at different positions along its extension direction. For example, the width of the second sub-power signal line 420 may decrease at positions corresponding to certain color sub-pixels. Similarly, the width of the second power signal line 500 along the first direction may vary slightly at different positions along its extension direction.

[0188] In some examples, the wider portion of the second power signal line 500 and the second sub-power signal line 420 are identical. Please refer to... Figure 6G' It is understood that, with the via 352 penetrating the first planarization layer 122 and the passivation layer 123 as the fifth via H5, the orthogonal projections of multiple fifth vias H5 located in the same row along the first direction onto the substrate 100 can be arranged along the fourth straight line L4. Furthermore, the distance from the orthogonal projection of the fifth via H5 onto the substrate 100 to the orthogonal projection of any effective light-emitting area onto the substrate 100 is greater than 2.5 μm.

[0189] In some embodiments, two second sub-power signal lines 420 located on either side of and adjacent to the first effective light-emitting area 2100 of the first color sub-pixel 210 are not equidistant from the center line extending along the second direction of the first effective light-emitting area 2100. For example, the distance between a second sub-power signal line 420 adjacent to the first effective light-emitting area 2100 in the first direction and the center line extending along the second direction of the first effective light-emitting area 2100 is greater than that of another second sub-power signal line 420 adjacent to the first effective light-emitting area 2100 in the first direction.

[0190] Based on this, the display substrate 10 also includes a plurality of pads 430 disposed on the same layer as the first power signal line 400, and a plurality of support portions 440 disposed on the same layer as the pads 430. The aforementioned second metal layer 350 can also be used to fabricate the pads 430 and the support portions 440. The pads 430 extend along the second direction and are correspondingly coupled to the first sub-power signal line 410. The pads 430 are located between the first effective light-emitting area 2100 and the second sub-power signal line 420. The pads 430 can adopt a long strip structure extending along the second direction. The two ends of the pads 430 along the second direction are respectively coupled to the second sub-power signal line through the support portions 440, forming a closed ring structure. Optionally, the center of the orthographic projection of the pads 430 on the substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the substrate 100. That is, the first sub-power signal line 410 can be the center of symmetry of the pads 430. The distance from the first effective light-emitting area 2100 to the pad 430 and the second sub-power signal line 420 located on both sides of it in the first direction is approximately the same. For example, the ratio of the two distances is in the range of 0.9 to 1.1, which can ensure that the two sides of the first effective light-emitting area 2100 have a relatively consistent application environment and the light intensity emitted from the first effective light-emitting area 2100 is uniform, which is beneficial to improving color deviation.

[0191] In addition, the pad 430 is electrically connected to the first power signal line 400, which can prevent the pad 430 from being in a floating state, thereby affecting the normal operation of the light-emitting device 0220.

[0192] Optionally, the orthographic projection of the pad 430 on the substrate 100 does not overlap with the orthographic projection of the first effective light-emitting area 2100 on the substrate, which can prevent the pad 430 from affecting the display of the first color sub-pixel 210.

[0193] Optionally, the orthographic projections of the pad 430 and the pixel electrode 211 of the first color sub-pixel 210 on the substrate 100 do not overlap, or the overlapping area is very small, which helps to reduce color shift.

[0194] Optionally, the dimension of the pad 430 along the second direction is larger than its dimension along the first direction. The dimension of the pad 430 along the second direction is smaller than the dimension of the first effective light-emitting area 2100 along the same direction. When the display substrate in this embodiment is used for under-display fingerprint detection, the dimension of the pad 430 along the second direction can be designed to be smaller than the dimension of the first effective light-emitting area in the same direction to improve the light transmittance of the display substrate.

[0195] In some embodiments, in each film layer from the substrate 100 to the pixel electrode layer 360 along a direction perpendicular to the substrate 100, at least a portion of the notch region of the pixel electrode does not overlap with the metal pattern in each metal layer, such that the light transmittance of this portion of the region is greater than 60%.

[0196] Optionally, in each film layer from the substrate 100 to the pixel electrode layer 360 along a direction perpendicular to the substrate 100, at least a portion of the notch region does not overlap with the metal pattern in each metal layer or the semiconductor pattern in each semiconductor pattern layer, so that the light transmittance of this portion of the region is greater than 70%.

[0197] Thus, when the display substrate 10 is used for optical under-display fingerprint detection, the light-transmitting portion of the notch area can be used to reflect light, thereby facilitating the detection of fingerprint patterns. It should be noted that the display substrate 10 may also contain other light-transmitting areas, such as any area along a direction perpendicular to the substrate 100 that does not overlap with any of the metal layers of the display substrate 10. This will not be described in detail in the embodiments disclosed herein.

[0198] Optical under-display fingerprint detection technology typically uses light emitted from the display substrate 10 as a light source. The fingerprint sensor is usually located on the non-display side of the display substrate, for example, on the side of the light-emitting device 0220 close to the substrate 100, in order to realize the under-display fingerprint detection function.

[0199] For example, the light emitted by each sub-pixel can be used for display and as light for under-display fingerprint detection. A top film layer for placing a finger can also be provided on the side of the sub-pixel away from the substrate 100. A fingerprint sensor for acquiring fingerprint images can be disposed on the same side of the display substrate 10 as each sub-pixel, and the fingerprint sensor is disposed on the side of the light-emitting device 0220 in each sub-pixel closest to the substrate 100, for detecting reflected light from the fingerprint on the surface of the top film layer. The fingerprint sensor can include multiple detection units arranged in an array. To achieve under-display fingerprint detection, at least a portion of the aforementioned top film and substrate layers are transparent, and a light-transmitting area is provided between adjacent sub-pixels so that reflected light from the fingerprint on the surface of the top film can be incident on the fingerprint sensor to acquire a fingerprint image. Since the anode of the light-emitting device in each sub-pixel easily affects light transmittance, thus affecting the sensitivity of fingerprint detection, a notch is provided in the pixel electrode of the light-emitting device to effectively improve the light transmittance in the display substrate.

[0200] It should be added that, in some embodiments, in the two pixel circuits of the first sub-pixel 22-1 and the second sub-pixel 22-2, the metal with the same potential as the control electrode of the driving transistor T1 includes: the first electrode CC1 of the capacitor C located in the first gate metal layer 320, and the first transition electrode 341 located in the first metal layer 340. Taking the orthographic projection of the first electrode CC1 of the capacitor C and the first transition electrode 341 in each pixel circuit onto the substrate 100 as the first projection, the overlapping projection area of ​​the orthographic projection of the pixel electrode of the first sub-pixel 22-1 onto the substrate 100 and the first projection as the first area, and the overlapping projection area of ​​the orthographic projection of the pixel electrode of the second sub-pixel 22-2 onto the substrate 100 and the first projection as the second area, the area ratio of the first area and the second area can range from 0.8 to 1.2. That is, the first area and the second area are approximately the same. This helps ensure that the loads of the two pixel circuits of the first sub-pixel 22-1 and the second sub-pixel 22-2 are consistent, thereby avoiding the problem of uneven light output brightness of the first sub-pixel 22-1 and the second sub-pixel 22-2.

[0201] Since the orthographic projections of the first electrode CC1 of capacitor C on the substrate 100 and the orthographic projections of the first transfer electrode 341 on the substrate 100 partially overlap in each pixel circuit, and the shapes of the two pixel electrodes in the first sub-pixel 22-1 and the second sub-pixel 22-2 are different, optionally, the area of ​​the overlapping orthographic projections of the pixel electrode 221-1 of the first sub-pixel 22-1 and the first electrode CC1 of capacitor C on the substrate 100 is smaller than the area of ​​the overlapping orthographic projections of the pixel electrode 221-2 of the second sub-pixel 22-2 and the first electrode CC1 of capacitor C on the substrate 100; and the area of ​​the overlapping orthographic projections of the pixel electrode 221-1 of the first sub-pixel 22-1 and the first transfer electrode 341 on the substrate 100 is larger than the area of ​​the overlapping orthographic projections of the pixel electrode 221-2 of the second sub-pixel 22-2 and the first transfer electrode 341 on the substrate 100.

[0202] Furthermore, in some embodiments, such as Figure 9As shown, the compensation portion 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 includes: a first compensation portion 2-21 electrically connected to the bent portion 2-1, and a second compensation portion 2-22 located on the side of the first compensation portion 2-21 away from the bent portion 2-1 and electrically connected to the first compensation portion 2-21. The first compensation portion 2-21 and the second compensation portion 2-22 can adopt an elongated strip structure extending along a second direction. The orthographic projection of the second compensation portion 2-22 on the substrate 100 does not overlap with the orthographic projection of the first electrode CC1 of the capacitor C on the substrate 100. The size of the second compensation portion 2-22 in the first direction is smaller than the size of the first compensation portion 2-21 in the same direction, which is beneficial to obtaining more light-transmitting area in the display substrate 10 to improve the light transmittance of the display substrate 10.

[0203] In addition, such as Figure 9 As shown, in some examples, the compensation portion 2-2 of pixel electrode 221-1 in the first sub-pixel 22-1 is located between the pixel electrode 231 of the adjacent third color sub-pixel 230 and the pixel electrode 211 of the first color sub-pixel 210. The first distance W1 of the second compensation portion 2-22 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction can be approximately the same as its second distance W2 to the pixel electrode 211 of the first color sub-pixel 210 in the first direction. The third distance W3 of the first compensation portion 2-21 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction can be approximately the same as its fourth distance W4 to the pixel electrode 211 of the first color sub-pixel 210 in the first direction. The first distance W1 is greater than the third distance W3, and the second distance W2 is greater than the fourth distance W4. For example, the ratio of the second distance W2 to the first distance W1 ranges from 0.9 to 1.1. For example, the first distance W1 ranges from 4.5 μm to 6.5 μm, and is, for example, 5.47 μm. The second distance W2 ranges from 4.5 μm to 6.5 μm, and is, for example, 5.73 μm. The ratio of the fourth distance W4 to the third distance W3 ranges from 0.9 to 1.1. For example, the third distance W3 ranges from 2.5 μm to 4.0 μm, and is, for example, 3.0 μm. The second distance W2 ranges from 2.5 μm to 4.0 μm, and is, for example, 3.0 μm.

[0204] The structure of each sub-pixel in the display substrate 10 is as described above. In some embodiments, by reducing the electrode area located outside the effective light-emitting area in each sub-pixel, the area of ​​light occlusion can be reduced, thereby improving the light transmittance of the display substrate. For example, while keeping the area of ​​the effective light-emitting area of ​​each sub-pixel constant, by changing the shape of the portion of the pixel electrode located outside the effective light-emitting area, such as the connecting portion, that is, by increasing the area ratio of the effective light-emitting area to the pixel electrode, the influence of the pixel electrode on light occlusion can be reduced, thereby improving the light transmittance of the display substrate.

[0205] For example, in the first color sub-pixel 210, the area ratio of the first effective light-emitting area 2100 to the pixel electrode 211 ranges from 53% to 55%. In the second color sub-pixel pair 220, the area ratio of the first effective light-emitting area 2201 to the pixel electrode 221-1 ranges from 43.5% to 48%, and the area ratio of the second effective light-emitting area 2202 to the pixel electrode 221-2 ranges from 43.5% to 48%. In the third color sub-pixel 230, the area ratio of the third effective light-emitting area 2300 to the pixel electrode 231 ranges from 67.5% to 69%. For example, in the first color sub-pixel 210, the area ratio of the first effective light-emitting area 2100 to the pixel electrode 211 is 54.9%. In the second color sub-pixel pair 220, the area ratio of the first sub-effective light-emitting area 2201 to the pixel electrode 221-1 is 47%, and the area ratio of the second sub-effective light-emitting area 2202 to the pixel electrode 221-2 is 47%. In the third color sub-pixel 230, the area ratio of the third effective light-emitting area 2300 to the pixel electrode 231 is 68.3%. This ensures that the display substrate 10 as a whole has good light transmittance, thereby improving the sensitivity of fingerprint detection.

[0206] Additionally, optionally, the area ratio of the first effective light-emitting area 2100, the effective light-emitting area of ​​the second color sub-pixel pair 220, and the third effective light-emitting area 2300 is approximately 1:1.27:1.47. The area ratio of the pixel electrode 211 in the first color sub-pixel 210, the pixel electrode in the second color sub-pixel pair 220, and the pixel electrode 231 in the third color sub-pixel 230 is approximately 1:1.48:1.18. Here, "area ratio" refers to the ratio of the areas projected onto the substrate.

[0207] To clearly illustrate the layer structure of the display substrate 10 in some embodiments of this disclosure, please refer to [link to relevant documentation]. Figure 7A Some embodiments of this disclosure also provide cross-sectional examples of multiple local regions in a display substrate 10. Figure 7B for Figure 7A A schematic cross-sectional view of the display substrate 10 along the AA' direction is shown. Figure 7C for Figure 7AA schematic cross-sectional view of the display substrate 10 along the BB' direction is shown. Figure 7D for Figure 7A A schematic cross-sectional view of the display substrate 10 along the CC' direction is shown.

[0208] Figure 7E for Figure 7A A schematic cross-sectional view of the display substrate 10 along the DEFGH direction is shown. Figure 7F for Figure 7A A schematic cross-sectional view of the display substrate 10 along the LMN direction is shown. Figure 7G for Figure 7A The diagram shows a cross-sectional view of the display substrate 10 along the RST direction. Please refer to the following... Figures 6A to 6I ,as well as Figures 7A to 7G understand.

[0209] Here, Figures 7B to 7G The cross-sectional views shown are all schematic diagrams with an example in which a passivation layer 123 and a first planarization layer 122 are formed between the first metal layer 340 and the second metal layer 350, and the first planarization layer 122 is located on the side of the passivation layer 123 away from the substrate 100. However, it is not limited to this.

[0210] Please combine Figures 7B to 7G It is understood that the display substrate 10 also includes a pixel defining layer 130 located on the pixel electrode layer 360. The pixel defining layer 130 has a plurality of openings for defining effective light-emitting areas of sub-pixels. The light-emitting device 0220 includes an anode, a light-emitting layer, and a cathode stacked sequentially. The anode of the light-emitting device 0220 is coupled to the pixel circuit 0221. The openings in the pixel defining layer 130 expose the anode of the light-emitting device 0220. At least a portion of the light-emitting layer of the light-emitting device 0220 is located within the openings, and the cathode is located on the side of the pixel defining layer 130 facing the substrate. When the light-emitting layer of the subsequent light-emitting device 0220 is formed in the openings of the pixel defining layer 130, the portion of the light-emitting layer in contact with the anode can emit light under the voltage drive of the anode and cathode to form an effective light-emitting area.

[0211] Here, "effective light-emitting area" can refer to a two-dimensional planar region parallel to the substrate 100. It should be noted that, due to manufacturing processes, the portion of the opening in the pixel defining layer 130 farther from the substrate 100 is slightly larger than the portion closer to the substrate 100, or its size gradually increases from the side closer to the substrate 100 to the side farther away. Therefore, the size of the effective light-emitting area may differ slightly from the size of different locations of the opening in the pixel defining layer 130, but its overall shape and size are essentially the same. For example, the orthographic projection of the effective light-emitting area onto the substrate 100 roughly coincides with the orthographic projection of the corresponding opening in the pixel defining layer 130 onto the substrate 100. Alternatively, the orthographic projection of the effective light-emitting area onto the substrate 100 may fall entirely within the orthographic projection of the corresponding opening in the pixel defining layer 130 onto the substrate 100, and both projections are similar in shape. However, the area of ​​the orthographic projection of the effective light-emitting area onto the substrate 100 may be slightly smaller than the area of ​​the orthographic projection of the corresponding opening in the pixel defining layer 130 onto the substrate 100.

[0212] like Figure 7A As shown, the second color sub-pixel pair 220 includes a gap between the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202. This "gap" refers to the physical portion of the pixel-defining layer 130 between the two openings defined by the pixel-defining layer 130.

[0213] Furthermore, in the same second color sub-pixel pair 220, the size of the interval between the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 along the second direction is smaller than the size of the first effective light-emitting area 2100 along the second direction, and the size of the interval along the second direction is smaller than the size of the third effective light-emitting area 2300 along the second direction.

[0214] Optionally, along the second direction, the size of the first effective light-emitting region 2100 is larger than the size of the third effective light-emitting region 2300. For example, the size of the first effective light-emitting region 2100 can be 45 to 49 micrometers, for example, 47 micrometers; the size of the third effective light-emitting region 2300 can be 38 to 42 micrometers, for example, 40 micrometers.

[0215] In some examples, such as Figure 7AAs shown, the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 have approximately the same shape. The ratio of the distance between the centers of the orthographic projection of the first sub-power signal line 410 on the substrate 100 and the two orthographic projections of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 on the substrate 100 is 0.9 to 1.1. For example, the distance between the centers of the two orthographic projections of the first sub-power signal line 410 on the substrate 100 and the two orthographic projections of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 on the substrate 100 is approximately equal. Therefore, the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 are symmetrically distributed with respect to the first sub-power signal line 410, which helps to ensure the environmental consistency of the first sub-pixel 22-1 and the second sub-pixel 22-2 included in the second color sub-pixel pair 220. However, this is not the only possibility. For example, the orthographic projection of the first sub-power signal line 410 onto the substrate 100 may be closer to one of the second color sub-pixel pairs 220. Alternatively, the orthographic projection of the first sub-power signal line 410 onto the substrate 100 may not overlap with the orthographic projections of the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 onto the substrate 100.

[0216] The center of the above-mentioned orthographic projection refers to the geometric center of the orthographic projection shape. The shape of the orthographic projection of the effective light-emitting area on the substrate is determined by the shape of the effective light-emitting area. The shape of the effective light-emitting area is approximately the same as the shape of the opening of its corresponding pixel defining layer 130.

[0217] For example, such as Figure 7A As shown, the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 include pentagons, circles, or teardrop shapes. For example, Figure 7A The diagram schematically illustrates that the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are pentagonal in shape. The pentagon includes a set of parallel opposite sides (parallel to the second direction) and a perpendicular side (parallel to the first direction). The perpendicular side is perpendicular to the set of parallel opposite sides. The two perpendicular sides of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 in each second color sub-pixel pair 220 are arranged adjacent to each other. For example, the first sub-power signal line 410 is located between the two perpendicular sides and passes through the midpoint of the shortest line connecting the two perpendicular sides.

[0218] In addition, although Figure 7AThe shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 strictly include the angle formed by two line segments. However, in some embodiments, the intersection shape of the two line segments of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 can both be rounded, such as a circle or a teardrop shape. That is, based on the above-mentioned pentagonal shape, the corners of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are rounded. For example, when forming the opening of the pixel defining layer 130, the corner portion of the opening may be formed into a rounded shape so that the shape of the formed effective light-emitting area may be rounded.

[0219] A local profile of the second color subpixel to 220 is as follows: Figure 7B As shown in the diagram. In the second color sub-pixel pair 220, the light-emitting layer 223 and the cathode layer 222 are sequentially stacked on the surface of the pixel defining layer 130 away from the substrate 100, and are in contact with the pixel electrode 221 exposed by the corresponding opening in the pixel defining layer 130. Some embodiments of this disclosure are described with the example that the light-emitting layers 223 in the first sub-pixel 22-1 and the second sub-pixel 22-2 of the second color sub-pixel pair 220 are integral. For example, the light-emitting layers 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 are a connected integral film layer, that is, the light-emitting layers 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 are a continuous and complete pattern, or the orthogonal projection of the light-emitting layers 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 onto the substrate 100 is continuous and complete. The light-emitting layers 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 can be obtained by fabricating through an opening. However, this is not the only possibility. For example, the light-emitting layers of the first sub-pixel 22-1 and the second sub-pixel 22-2 included in the same second color sub-pixel pair 200 can also be separate.

[0220] A partial profile of the first color subpixel 210, as shown below Figure 7C and Figure 7D As shown in the figure. In the first color sub-pixel 210, the light-emitting layer 213 and the cathode layer 212 are sequentially stacked on the surface of the pixel defining layer 130 away from the substrate 100, and are in contact with the pixel electrode 211 exposed by the corresponding opening in the pixel defining layer 130.

[0221] Another local profile of the first color subpixel 210 is as follows: Figure 7EAs shown in the diagram. In the first color sub-pixel 210, the pixel electrode 211 is electrically connected to the connection electrode 450 through a via 1210 penetrating the second planarization layer 121. The connection electrode 450 is electrically connected to the driving electrode 343 through a via 351 penetrating the first planarization layer 122 and the passivation layer 123. The driving electrode 343 is electrically connected to the second electrode T5-2 of the second light-emitting control transistor through a via 388 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150, and the gate insulating layer 160. The orthographic projections of the vias 1210, 351, and 388 on the substrate 100 do not overlap and are spaced apart from each other.

[0222] A partial cross-section of the third color subpixel 230 is shown below. Figure 7F As shown in the diagram. In the third color sub-pixel 230, the orthographic projection of the pixel electrode 231 onto the substrate 100 partially overlaps with the orthographic projection of the first sub-power signal line 410 onto the substrate 100. The light-emitting layer 233 and the cathode layer 232 are sequentially stacked on the surface of the pixel defining layer 130 away from the substrate 100, and are in contact with the pixel electrode 231 exposed by the corresponding opening in the pixel defining layer 130.

[0223] The local profile of the first sub-pixel 22-1 is as follows Figure 7G As shown in the diagram. In the first sub-pixel 22-1, the pixel electrode 221-1 includes a main body portion 221-11, a bent portion 2-21, and a compensation portion 2-22. A light-emitting layer 223-1 and a cathode layer 222-1 are sequentially stacked on the surface of the pixel defining layer 130 away from the substrate 100, and are in contact with the main body portion 221-11 of the pixel electrode 221-1 exposed by corresponding openings in the pixel defining layer 130. Figure 7A In the cross-section along the RS direction, there are gaps between the main body portion 221-11 and the bent portion 2-21 of the pixel electrode 221-1, and between the bent portion 2-21 and the compensation portion 2-22. The second sub-power signal line 420 in the first power signal line 400 can be electrically connected to the second power signal line 500 through a via 352 penetrating the first planarization layer 122 and the passivation layer 123. The second power signal line 500 can be electrically connected to the first electrode T4-1 of the first light-emitting control transistor through a via 382 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150, and the gate insulating layer 160.

[0224] In some of the above embodiments, the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 140, the passivation layer 123, the first planarization layer 122, and the second planarization layer 121, etc., are multilayer insulating layers used to insulate and protect the corresponding conductive layers, such as metal layers or semiconductor layers. Optionally, the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 140, and the passivation layer 123 are formed using inorganic insulating materials, such as silicon nitride or silicon oxide. The first planarization layer 122 and the second planarization layer 121 are formed using organic insulating materials, such as organic insulating resin.

[0225] Another embodiment of this disclosure provides a display device including any of the above-described display substrates. This display device can minimize color shift, can also utilize fingerprint detection technology, and has high fingerprint detection sensitivity.

[0226] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0227] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, include: Substrate; A plurality of sub-pixels, each sub-pixel including a pixel electrode and an effective light-emitting area; the pixel electrode including interconnected main body portions and connecting portions; the main body portions having the same shape as the effective light-emitting area, and the main body portions coinciding with at least a portion of the boundary of the pixel electrode; the plurality of sub-pixels including at least a first sub-pixel and a second sub-pixel having the same emission color; Wherein, the dimensions of the connection portion of the pixel electrode in the first sub-pixel and the connection portion of the pixel electrode in the second sub-pixel are different in the second direction; the two orthographic projections of the connection portion and the main body portion of at least one of the first and second sub-pixels on a straight line extending along the first direction do not overlap at least partially. The orthographic projection of the pixel electrode of the second sub-pixel onto a straight line extending along the second direction lies within the orthographic projection of the pixel electrode of the first sub-pixel onto the same straight line. The second direction intersects the first direction, and the angle between them ranges from 80° to 100°.

2. The display substrate according to claim 1, characterized in that, The main body includes a first side, a second side, and a third side connected in sequence; the third side extends along the second direction. The connecting portion is connected to the second side and has a gap between it and the first side; A straight line connecting any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, together with the main body and the connecting portion, forms a recessed area.

3. The display substrate according to claim 2, characterized in that, It also includes multiple layers located between the substrate and the pixel electrode; the multiple layers include at least one metal pattern; Wherein, in each layer from the substrate to the pixel electrode along a direction perpendicular to the substrate, at least a portion of the notch region does not overlap with the metal pattern.

4. The display substrate according to claim 2, characterized in that, It also includes multiple layers located between the substrate and the pixel electrode; the multiple layers include a semiconductor pattern and at least one metal pattern; Wherein, in each layer from the substrate to the pixel electrode along a direction perpendicular to the substrate, at least a portion of the notch region does not overlap with the semiconductor pattern or the metal pattern.

5. The display substrate according to claim 2, characterized in that, The connection portion of the pixel electrode in the first sub-pixel includes: a bending portion and a compensation portion connected to the bending portion; The curved portion is connected to the second side; there is a gap between the curved portion and the first side.

6. The display substrate according to claim 5, characterized in that, The maximum dimension of the compensation part along the first direction is greater than the maximum dimension of the bending part along the first direction.

7. The display substrate according to claim 1, characterized in that, Also includes: A first gate metal layer located between the substrate and the pixel electrode, and a first metal layer located between the first gate metal layer and the pixel electrode; The sub-pixel also includes a pixel circuit; The pixel circuit includes a driving transistor; The metal pattern having the same potential as the control electrode of the driving transistor includes: a first electrode of a capacitor located in the first gate metal layer, and a first transition electrode located in the first metal layer; Wherein, the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel and the first electrode of the corresponding capacitor on the substrate is smaller than the area of ​​the orthographic projection of the pixel electrode of the second sub-pixel and the first electrode of the corresponding capacitor on the substrate; and the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel and the first transfer electrode on the substrate is larger than the area of ​​the orthographic projection of the pixel electrode of the second sub-pixel and the first transfer electrode on the substrate.

8. The display substrate according to claim 1, characterized in that, Also includes: Multiple signal lines extending along the first direction; the orthographic projection of the pixel electrode of the first sub-pixel on the substrate overlaps with the orthographic projection of at least three signal lines located on the same layer on the substrate.

9. The display substrate according to any one of claims 1 to 8, characterized in that, Also includes: Multiple pixel circuits, wherein the sub-pixel includes the pixel circuits; The plurality of said pixel circuits are arranged in a row along the first direction and in a column along the second direction; The display substrate further includes: a second planarization layer and a plurality of first vias located on the second planarization layer; the second planarization layer is located between the pixel electrode and the pixel circuit, and the pixel electrode is electrically connected to the pixel circuit through the first vias; In this arrangement, the orthographic projections of the plurality of first vias corresponding to the plurality of pixel circuits in the same row onto the substrate are arranged along a first straight line.

10. The display substrate according to claim 9, characterized in that, Also includes: Passivation layer and multiple driving electrodes; The passivation layer is located between the pixel electrode and the driving electrode, and has multiple vias; The pixel electrode is electrically connected to the driving electrode through the via.

11. The display substrate according to claim 10, characterized in that, The orthographic projection of the driving electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

12. The display substrate according to claim 10, characterized in that, Also includes: Semiconductor patterning layer, gate insulating layer, first interlayer insulating layer and second interlayer insulating layer; The semiconductor patterned layer is located between the substrate and the driving electrode; The gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer are located between the driving electrode and the semiconductor patterning layer; the display substrate further includes a plurality of third vias; the driving electrode is coupled to a corresponding portion of the semiconductor patterning layer through the third vias; Among them, the third through hole, the second through hole and the first through hole corresponding to the same driving electrode are spaced apart from each other in the three orthogonal projections on the substrate.

13. The display substrate according to claim 1, characterized in that, Also includes: Multiple sub-pixel groups; At least one of the sub-pixel groups comprises: a first color sub-pixel, a second color sub-pixel pair, and a third color sub-pixel; The second color sub-pixel pair includes two of the effective light-emitting areas.

14. The display substrate according to claim 1, characterized in that, The main body portions of the two pixel electrodes of the first sub-pixel and the second sub-pixel are approximately the same size.

15. The display substrate according to claim 13, characterized in that, In at least one of the sub-pixel groups, the connecting portion in the first color sub-pixel is located on the side of its main body closer to the second color sub-pixel pair.

16. The display substrate according to claim 13, characterized in that, The connecting portion in the second color sub-pixel pair is located on the side of its main body away from the first color sub-pixel along the axis of symmetry in the second direction.

17. The display substrate according to claim 13, characterized in that, The connecting portion of the third color sub-pixel is misaligned with the first color sub-pixel along the second direction.

18. The display substrate according to claim 13, characterized in that, The main body of the pixel electrode of the first color sub-pixel includes a first side, a second side, and a third side connected in sequence; the third side extends along the second direction; The connecting portion is connected to the second side and has a gap between it and the first side; A straight line connecting any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, together with the main body and the connecting portion, forms a recessed area.

19. The display substrate according to claim 1, characterized in that, The sub-pixel also includes a pixel circuit, which is electrically connected to the pixel electrode, and the pixel circuit includes at least 7 transistors.

20. A display device, characterized in that, The display substrate includes any one of claims 1-19.

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