Display panel and manufacturing method thereof

Abstract

The application relates to a display panel and a manufacturing method thereof. The display panel comprises a substrate, a plurality of light-emitting units, a first encapsulation layer and at least one auxiliary electrode. The plurality of light-emitting units are arranged on the substrate, and the light-emitting unit comprises a first electrode, a light-emitting functional layer and a second electrode which are sequentially arranged in a direction away from the substrate. The first encapsulation layer comprises a first encapsulation sublayer and a second encapsulation sublayer. The first encapsulation sublayer is arranged on a side of the plurality of light-emitting units away from the substrate and covers the plurality of light-emitting units. The second encapsulation sublayer is arranged on a side of the first encapsulation sublayer away from the substrate. The first encapsulation layer comprises a plurality of through holes penetrating through the first encapsulation sublayer and the second encapsulation sublayer. The at least one auxiliary electrode is arranged on a side of the first encapsulation layer away from the substrate and is electrically connected to the second electrode of the plurality of light-emitting units through the plurality of through holes. The display panel of the application can make the current more uniformly distributed on the display panel, improve the brightness uniformity of the display panel and improve the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] Display panels are indispensable components in modern electronic devices, used to display images and text information. Packaging technology is a crucial part of display panel manufacturing. However, current display panel technologies suffer from poor packaging performance.

[0003] In some display panels, auxiliary electrode technology is introduced to effectively improve their performance. Patents CN118742138A, PCT / CN2024 / 107011, and 202411175069.8 describe the relevant content of auxiliary electrode technology for reference. Summary of the Invention

[0004] Based on this, a display panel and its manufacturing method are provided. By introducing auxiliary electrodes, the current is distributed more evenly on the display panel to improve the display effect.

[0005] A display panel, the display panel comprising:

[0006] substrate;

[0007] Multiple light-emitting units are disposed on the substrate, and each light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode that are sequentially stacked along a direction away from the substrate.

[0008] The first encapsulation layer includes a first encapsulation sublayer and a second encapsulation sublayer. The first encapsulation sublayer is disposed on the side of the plurality of light-emitting units away from the substrate and covers the plurality of light-emitting units. The second encapsulation sublayer is disposed on the side of the first encapsulation sublayer away from the substrate. The first encapsulation layer includes a plurality of vias penetrating the first encapsulation sublayer and the second encapsulation sublayer.

[0009] At least one auxiliary electrode is disposed on the side of the first encapsulation layer away from the substrate, and is electrically connected to the second electrode of the plurality of light-emitting units through the plurality of vias.

[0010] In one embodiment, the first encapsulation sublayer has at least one gap, which is filled by the second encapsulation sublayer;

[0011] Optionally, the extension direction of the at least one slit intersects the plane where the substrate is located.

[0012] In one embodiment, the material of the first encapsulation sublayer is the same as the material of the second encapsulation sublayer;

[0013] Optionally, the material of the first encapsulation sublayer includes inorganic materials, and the material of the second encapsulation sublayer includes inorganic materials.

[0014] In one embodiment, the display panel further includes:

[0015] A pixel definition layer is disposed on one side of the substrate, and a plurality of pixel openings are formed on the pixel definition layer, with a portion of the light-emitting unit located within the corresponding pixel opening;

[0016] Optionally, a portion of the first electrode is located between the substrate and the pixel definition layer, and another portion is exposed from the corresponding pixel opening.

[0017] In one embodiment, the display panel further includes:

[0018] The second encapsulation layer is disposed on the side of the first encapsulation layer away from the substrate;

[0019] The third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate;

[0020] Optionally, the material of the second encapsulation layer includes organic materials, and the material of the third encapsulation layer includes inorganic materials;

[0021] Optionally, the material of the third encapsulation layer is the same as that of the first encapsulation layer.

[0022] According to another aspect of this application, a method for manufacturing a display panel is provided, the method comprising:

[0023] Provide a substrate;

[0024] Multiple light-emitting units are formed on the substrate;

[0025] A first encapsulation sublayer is formed on the side of the plurality of light-emitting units away from the substrate;

[0026] Stress relief is performed on the first encapsulation sublayer;

[0027] A second encapsulation sublayer is formed on the side of the first encapsulation sublayer away from the substrate to obtain a first encapsulation layer including the first encapsulation sublayer and the second encapsulation layer;

[0028] Multiple vias are formed on the first encapsulation layer and penetrate the first encapsulation sublayer and the second encapsulation sublayer;

[0029] At least one auxiliary electrode is formed on the side of the first encapsulation layer away from the substrate and fills the plurality of vias. The at least one auxiliary electrode is electrically connected to the second electrode of the plurality of light-emitting units through the plurality of vias.

[0030] In one embodiment, after stress relief of the first encapsulation sublayer, at least one gap is exposed in the first encapsulation sublayer, and the step of forming a second encapsulation sublayer on the side of the first encapsulation sublayer away from the substrate includes:

[0031] A second encapsulation sublayer is formed on the side of the first encapsulation sublayer away from the substrate, such that the material of the second encapsulation sublayer fills the at least one gap.

[0032] In one embodiment, the stress relief step of the first encapsulation sublayer includes:

[0033] The first encapsulation sublayer is cooled.

[0034] In one embodiment, the step of cooling the first encapsulation sublayer includes:

[0035] The first encapsulation sublayer is cooled multiple times, each time from a first temperature to a second temperature, and held at the second temperature for a preset time, wherein the difference between the first temperature and the second temperature is 8°-12°.

[0036] Optionally, the preset time ranges from 1 to 3 minutes.

[0037] In one embodiment, the step of cooling the first encapsulation sublayer includes:

[0038] The temperature of the first encapsulation sublayer is lowered from the third temperature to the fourth temperature;

[0039] The third temperature ranges from 95° to 105°, and the fourth temperature ranges from 25° to 35°.

[0040] The aforementioned display panel has vias on the encapsulation layer. The auxiliary electrode is electrically connected to the light-emitting unit through the vias. By setting the auxiliary electrode, the current is distributed more evenly on the display panel, improving the brightness uniformity of the display panel and thus improving the display effect of the display panel. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a display panel according to one embodiment of this application.

[0042] Figure 2 This is an enlarged view showing a portion of the second encapsulation layer located within the first encapsulation layer according to an embodiment of this application.

[0043] Figure 3 This is a schematic diagram of the structure of a seamless display panel according to an embodiment of this application.

[0044] Figure 4 This is a flowchart illustrating the steps of a method for manufacturing a display panel according to an embodiment of this application.

[0045] Figure 5 This is a flowchart illustrating the steps of stress relief for the first encapsulation sublayer according to one embodiment of this application.

[0046] Explanation of reference numerals in the attached figures:

[0047] 10. Display panel;

[0048] 100. Substrate;

[0049] 200, Light-emitting unit; 210, First electrode; 220, Second electrode; 230, Light-emitting functional layer;

[0050] 310, First encapsulation sublayer; 320, Second encapsulation sublayer; 330, Auxiliary electrode;

[0051] 410, Pixel definition layer; 420, Second encapsulation layer; 430, Third encapsulation layer. Detailed Implementation

[0052] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0053] The upper auxiliary electrode technology can be applied to intelligent pixelation (ViP) technology and fine metal mask (FMM) technology. By controlling the polarization current of the auxiliary electrode, the pixel fabrication process can be optimized, thereby improving the performance of active matrix organic light-emitting diode (AMOLED) products.

[0054] Among them, intelligent pixelation technology is a metal-mask-free RGB self-alignment pixelation technology. It can utilize existing technologies and processes of active-matrix organic light-emitting diodes (AMOLEDs) in the thin-film field-effect transistor (TFT) control backplane section. After anode fabrication, differentiation begins from the pixel definition layer (PDL), forming the isolation pillar structure unique to ViP AMOLED. Subsequently, the entire surface is deposited and patterned using photolithography for pixel fabrication. During this process, the upper auxiliary electrode technology can serve as the anode during cathode studies or the cathode during anode studies. Polarizing current is simultaneously passed through the research electrode and auxiliary electrode to ensure uniform electric field distribution on the research electrode and reduce the cell voltage.

[0055] Fine metal mask technology is used in the core evaporation process of AMOLED displays, directly determining the resolution and display effect of the AMOLED screen. In the FMM (Foil-Mesh Modulation) evaporation process, the upper auxiliary electrode technology can also be applied to ensure the regular deposition of materials during evaporation and to prevent electrode reactions occurring on the upper auxiliary electrode from contaminating the electrolyte solution near the research electrode. In the FMM technology route, because each common layer in the electroluminescent (EL) device simultaneously functions as RGB sub-pixels, independent tuning and optimization of sub-pixel devices cannot be achieved, limiting the performance of the EL device. The upper auxiliary electrode technology can provide more flexible current control in this regard.

[0056] When using the top auxiliary electrode technology, holes need to be drilled above the thin-film encapsulation (TFE) layer. Since these auxiliary electrode holes need to be created above the chemical vapor deposition (CVD) layer, if particles are present below the CCVD layer, poor inorganic layer encapsulation combined with stress can cause cracks near the particles, creating channels for moisture intrusion. This can lead to encapsulation failure and affect device lifespan. For example, particles present in the evaporation chamber cannot be avoided by either the aforementioned intelligent pixelation technology or the fine metal mask technology. Furthermore, the friction between the SPC and FMM generated under the fine metal mask approach will inevitably produce particles. In short, both of these approaches inevitably generate particles, which can cause cracks in the encapsulation layer, leading to encapsulation failure.

[0057] When the display panel uses the upper auxiliary cathode technology, it is easy for cracks to appear in the encapsulation layer, resulting in encapsulation failure. Ultimately, impurities such as moisture can enter the display panel through the cracks, affecting the use of the display panel.

[0058] Based on the above issues, please refer to Figure 1 and Figure 2 As shown, this application provides a display panel 10 and its manufacturing method. By introducing auxiliary electrodes, the current is distributed more evenly on the display panel, thereby improving the display effect. Simultaneously, the display panel 10 of this application has better encapsulation, avoiding the risk of cracking when using upper auxiliary cathode technology.

[0059] The display panel 10 includes a substrate 100, a plurality of light-emitting units 200, and a first encapsulation layer. The plurality of light-emitting units 200 are disposed on the substrate 100 and are used to emit display light. Each light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode, which are sequentially stacked along a direction away from the substrate. The first encapsulation layer includes a first encapsulation sub-layer 310 and a second encapsulation sub-layer 320. The first encapsulation sub-layer 310 is disposed on the side of the light-emitting unit 200 away from the substrate 100 and covers the plurality of light-emitting units 200 to achieve preliminary encapsulation of the plurality of light-emitting units 200.

[0060] The second encapsulation sublayer 320 is disposed on the side of the first encapsulation sublayer 310 away from the substrate 100. The first encapsulation layer includes a plurality of vias penetrating the first and second encapsulation sublayers. At least one auxiliary electrode is disposed on the side of the first encapsulation layer away from the substrate and is electrically connected to the second electrodes of a plurality of light-emitting units through the plurality of vias.

[0061] The aforementioned display panel has vias on the encapsulation layer. The auxiliary electrode is electrically connected to the light-emitting unit through the vias. By setting the auxiliary electrode 330, the current can be distributed more evenly on the display panel 10, improving the brightness uniformity of the display panel 10, and thus improving the display effect of the display panel.

[0062] It is understood that this application has multiple light-emitting units 200, and correspondingly, multiple auxiliary electrodes 330 are also provided, and the multiple auxiliary electrodes 330 correspond one-to-one with the multiple light-emitting units 200.

[0063] In some embodiments, see Figure 1 , Figure 2 and Figure 3 As shown, Figure 3 This is a schematic diagram of a seamless display panel according to one embodiment of this application. The first encapsulation sublayer has at least one gap, and the at least one gap is filled by the second encapsulation sublayer. In some embodiments, the extension direction of the at least one gap intersects with the plane of the substrate. The gap is filled by the second encapsulation sublayer 320 to compensate for the cracks exposed by the first encapsulation sublayer 310 due to stress, thereby improving the stress resistance or encapsulation capability of the display panel 10.

[0064] It is understood that the above-mentioned display panel 10 is coated with a second encapsulation sub-layer 320 to fill the gaps in the first encapsulation sub-layer 310, thereby improving the stress resistance of the display panel 10 and preventing the first encapsulation sub-layer 310 from being affected by stress and unable to fill the gaps when the auxiliary electrode 330 is set, which would cause moisture to enter the gaps and affect the yield of the display panel 10. In other words, the display panel 10 of this application has a better encapsulation effect.

[0065] In some embodiments, the light-emitting functional layer 230 can emit light of at least three colors, three of which are red, blue and green, to achieve the display of full-color images on the display panel 10.

[0066] In some embodiments, the material of the first encapsulation sublayer 310 is the same as the material of the second encapsulation sublayer 320. Optionally, the material of the first encapsulation sublayer 310 includes inorganic materials, and the material of the second encapsulation sublayer 320 includes inorganic materials. The material of the first encapsulation sublayer 310 can be alumina, silicon nitride, silicon oxide, silicon oxynitride, etc., and the material of the second encapsulation sublayer 320 can be alumina, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0067] In some embodiments, continue reading Figure 1 and Figure 2 As shown, the display panel 10 also includes a pixel definition layer 410, which is disposed on one side of the substrate 100. The pixel definition layer 410 has multiple pixel openings, and portions of the light-emitting units are located within corresponding pixel openings. Optionally, a portion of the first electrode is located between the substrate and the pixel definition layer, while another portion is exposed through a corresponding pixel opening. Thus, the pixel openings expose at least a portion of the first electrode 210, and the light-emitting functional layer 230 and the second electrode 220 are stacked on the first electrode 210 along a direction away from the substrate 100. The first electrode 210 is exposed through the pixel definition layer 410 to facilitate the placement of the light-emitting functional layer 230 and the second electrode 220.

[0068] See Figure 1 The display panel 10 further includes a second encapsulation layer 420 and a third encapsulation layer 430 stacked on the side of the first encapsulation sublayer 310 away from the substrate 100 to improve the encapsulation effect of the display panel 10. It is understood that the second encapsulation layer 420 is disposed on the side of the first encapsulation sublayer 310 away from the substrate, and the third encapsulation layer 430 is disposed on the side of the second encapsulation layer 420 away from the substrate. Optionally, the material of the third encapsulation layer 430 is the same as the material of the first encapsulation sublayer 310. Optionally, the material of the second encapsulation layer 420 includes organic materials, and the material of the third encapsulation layer 430 includes inorganic materials. In some embodiments, the second encapsulation layer 420 uses inkjet printing technology to make the display panel 10 flat, and the third encapsulation layer 430 further encapsulates the display panel 10 to improve the encapsulation effect of the display panel 10.

[0069] In some embodiments, continue reading Figure 1 and Figure 2 As shown, the vias include a first via on the first encapsulation sublayer 310 and a second via on the second encapsulation sublayer 320. One end of the first via is electrically connected to the second electrode 220, and the other end of the first via is electrically connected to one end of the second via. The other end of the second via is electrically connected to the auxiliary electrode 330. It can be understood that the first via and the second via, which are interconnected, are provided on the first encapsulation sublayer 310 and the second encapsulation sublayer 320, so that the first via can be located within the first via and the second via can be located within the second via. The two ends of the second via are electrically connected to the auxiliary electrode 330 and the first via, respectively, and the first via is electrically connected to the second electrode 220, thereby achieving an electrical connection between the auxiliary electrode 330 and the second electrode 220.

[0070] See Figure 4 As shown, Figure 4 This is a flowchart illustrating the steps of a method for manufacturing a display panel according to an embodiment of this application.

[0071] This application also provides a method for manufacturing a display panel 10, for use in manufacturing the aforementioned display panel 10, the method comprising:

[0072] S1. A substrate 100 is provided. In some embodiments, the substrate 100 is an array substrate.

[0073] S2. A plurality of light-emitting units 200 are formed on the substrate 100. The plurality of light-emitting units 200 emit light of at least three colors, three of which are red, blue and green, so as to realize the display of full-color images on the display panel 10.

[0074] S3. A first encapsulation sublayer 310 is formed on the side of the light-emitting unit 200 away from the substrate 100. The first encapsulation sublayer 310 can be prepared by atomic layer deposition technology.

[0075] S4. Stress relief is performed on the first encapsulation sublayer 310. The stress of the first encapsulation sublayer 310 is released in advance to prevent cracks from appearing in the first encapsulation sublayer 310 due to stress when the first via is formed on the first encapsulation sublayer 310 later.

[0076] S5. A second encapsulation sublayer 320 is formed on the side of the first encapsulation sublayer 310 away from the substrate 100, so as to obtain a first encapsulation layer including the first encapsulation sublayer 310 and the second encapsulation sublayer 320.

[0077] S6. A plurality of vias are formed on the first encapsulation sublayer 310 and through the first encapsulation sublayer 310 and the second encapsulation sublayer 320.

[0078] S7. At least one auxiliary electrode is formed on the side of the first encapsulation layer away from the substrate and filled with multiple vias. The at least one auxiliary electrode is electrically connected to the second electrodes of multiple light-emitting units through the multiple vias. An auxiliary electrode 330 is formed on the side of the second encapsulation sub-layer 320 away from the first encapsulation sub-layer 310 to ensure that the current is more evenly distributed on the display panel 10, thereby improving the brightness uniformity of the display panel 10 and improving the display effect of the display panel. The auxiliary electrode 330 is electrically connected to the light-emitting unit 200 through the second via structure and the first via structure, or in other words, the auxiliary electrode 330 is electrically connected to the second electrode 220 through the second via structure and the first via structure.

[0079] In some embodiments, such as Figure 1 , Figure 2 and Figure 3As shown, after stress relief of the first encapsulation sub-layer 310 in step S4, at least one gap is exposed on the first encapsulation sub-layer 310. Step S5, the step of forming a second encapsulation sub-layer on the side of the first encapsulation sub-layer away from the substrate, further includes: S50, forming a second encapsulation sub-layer on the side of the first encapsulation sub-layer away from the substrate, so that the material of the second encapsulation sub-layer fills at least one gap, forming a seamless display panel, such as... Figure 3 As shown in the image.

[0080] Thus, by setting a second encapsulation sub-layer 320 to perform a secondary coating, the gaps in the first encapsulation sub-layer 310 are filled, thereby improving the stress resistance of the display panel 10 and preventing the gaps in the first encapsulation sub-layer 310 caused by stress when setting the auxiliary electrode 330 from becoming unrepairable.

[0081] In some embodiments, step S6, forming a plurality of vias disposed on the first encapsulation sublayer 310 and penetrating the first encapsulation sublayer 310 and the second encapsulation sublayer 320, further includes:

[0082] S61. A first via is formed on the first encapsulation sublayer 310, and a second via is formed on the second encapsulation sublayer 320. The second via communicates with the first via so that the first via structure and the second via structure are electrically connected to each other.

[0083] S62. A first via structure is formed in the first via and a second via structure is formed in the second via, and the first via structure and the second via structure are electrically connected to each other. The end of the first via structure away from the second via structure is electrically connected to the second electrode 220, and the end of the second via away from the first via structure is electrically connected to the auxiliary electrode 330.

[0084] In some embodiments, step S4, stress relief of the first encapsulation sublayer 310, specifically includes: step S41, cooling the first encapsulation sublayer 310 to release the stress of the first encapsulation sublayer 310 by cooling.

[0085] In some embodiments, see Figure 5 As shown, Figure 5 This is a flowchart illustrating the stress relief steps for the first encapsulation sublayer according to one embodiment of this application. Step S41, cooling the first encapsulation sublayer 310, includes the following steps in the first embodiment:

[0086] The first encapsulation sublayer 310 is cooled multiple times, each time from a first temperature to a second temperature, and held at the second temperature for a preset time. The difference between the first and second temperatures is 8°C-12°C. That is, the first encapsulation sublayer 310 is cooled in stages, with each temperature drop of 8°C-12°C followed by a preset holding time to facilitate subsequent cooling. Optionally, the preset time is 1-3 minutes. For example, after a single temperature drop of 8°C-12°C to bring the first encapsulation sublayer 310 from the first temperature to the second temperature, the first encapsulation sublayer 310 is held at the second temperature for 1-3 minutes. Preferably, the first encapsulation sublayer 310 is held at the second temperature for approximately 1-3 minutes. When cooling the first encapsulation sublayer 310, the substrate 100, the light-emitting unit 200, and the first encapsulation sublayer 310 can be cooled simultaneously to improve cooling convenience, eliminating the need for separate cooling of the first encapsulation sublayer 310.

[0087] In some embodiments, the time for each cooling of 8°-12° can be maintained at about 1 minute, so as to improve the efficiency of stress release of the first encapsulation sublayer 310 while ensuring that the substrate 100 and the light-emitting unit 200 are not damaged.

[0088] In some embodiments, continue reading Figure 5 As shown, step S41, cooling the first encapsulation sub-layer 310, further includes cooling the temperature of the first encapsulation sub-layer 310 from a third temperature to a fourth temperature, wherein the third temperature ranges from 95°C to 105°C, and the fourth temperature ranges from 25°C to 35°C. It can be understood that after the first encapsulation sub-layer 310 is formed on the substrate 100, the overall temperature, or the temperature of the first encapsulation sub-layer 310, is 95°C-105°C. At this point, the first encapsulation sub-layer 310 is cooled multiple times, ultimately reaching 25°C-35°C, to completely release the stress in the first encapsulation sub-layer 310 and expose the gaps caused by the released stress. When cooling the first encapsulation sub-layer 310, the substrate 100, the light-emitting unit 200, and the first encapsulation sub-layer 310 can be cooled simultaneously to improve cooling convenience, eliminating the need for separate cooling of the first encapsulation sub-layer 310.

[0089] The display panel 10 provided in this application is coated with a second encapsulation sub-layer 320 to fill the gaps in the first encapsulation sub-layer 310, thereby improving the stress resistance of the display panel 10. This avoids the gaps that cannot be filled when the first encapsulation sub-layer 310 is subjected to stress during the setting of the auxiliary electrode 330, which would cause moisture to enter the gaps and affect the yield of the display panel 10. In other words, the display panel 10 of this application has a better encapsulation effect.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a display panel, characterized in that, The manufacturing method comprises: providing a substrate; forming a plurality of light emitting units on the substrate; forming a first encapsulation sub-layer on a side of the plurality of light emitting units away from the substrate; stress releasing the first encapsulation sub-layer; forming a second encapsulation sub-layer on a side of the first encapsulation sub-layer away from the substrate to obtain a first encapsulation layer comprising the first encapsulation sub-layer and the second encapsulation sub-layer; forming a plurality of vias arranged on the first encapsulation layer and penetrating through the first encapsulation sub-layer and the second encapsulation sub-layer; forming at least one auxiliary electrode arranged on a side of the first encapsulation layer away from the substrate and filling the plurality of vias, the at least one auxiliary electrode being electrically connected to second electrodes of the plurality of light emitting units through the plurality of vias; after stress releasing the first encapsulation sub-layer, the first encapsulation sub-layer exposes at least one gap, and the step of forming a second encapsulation sub-layer on a side of the first encapsulation sub-layer away from the substrate comprises: forming a second encapsulation sub-layer on a side of the first encapsulation sub-layer away from the substrate so that a material of the second encapsulation sub-layer fills in the at least one gap.

2. The manufacturing method of a display panel according to claim 1, wherein The step of stress releasing the first encapsulation sub-layer comprises: cooling the first encapsulation sub-layer.

3. The manufacturing method of a display panel according to claim 2, wherein The step of cooling the first encapsulation sub-layer comprises: cooling the first encapsulation sub-layer multiple times, each time from a first temperature to a second temperature, and keeping the second temperature for a preset time, wherein a difference between the first temperature and the second temperature ranges from 8° to 12°.

4. The manufacturing method of a display panel according to claim 3, wherein The preset time ranges from 1 minute to 3 minutes.

5. The manufacturing method of a display panel according to claim 2, wherein The step of cooling the first encapsulation sub-layer comprises: cooling the first encapsulation sub-layer from a third temperature to a fourth temperature; wherein the third temperature ranges from 95° to 105°, and the fourth temperature ranges from 25° to 35°.

6. A display panel, characterized by, The display panel is prepared by the manufacturing method of the display panel according to any one of claims 1-5, and the display panel comprises: a substrate; a plurality of light emitting units arranged on the substrate, the light emitting units comprising first electrodes, light emitting functional layers and second electrodes arranged in a direction away from the substrate in sequence; a first encapsulation layer comprising a first encapsulation sub-layer and a second encapsulation sub-layer, the first encapsulation sub-layer being arranged on a side of the plurality of light emitting units away from the substrate and covering the plurality of light emitting units, the second encapsulation sub-layer being arranged on a side of the first encapsulation sub-layer away from the substrate, the first encapsulation layer comprising a plurality of vias penetrating through the first encapsulation sub-layer and the second encapsulation sub-layer; at least one auxiliary electrode arranged on a side of the first encapsulation layer away from the substrate and electrically connected to the second electrodes of the plurality of light emitting units through the plurality of vias; the first encapsulation sub-layer has at least one gap exposed due to stress, and the at least one gap is filled by the second encapsulation sub-layer.

7. The display panel of claim 6, wherein, An extension direction of the at least one gap intersects a plane where the substrate is located.

8. The display panel of claim 6, wherein, A material of the first encapsulation sub-layer is the same as a material of the second encapsulation sub-layer.

9. The display panel of claim 8, wherein, The material of the first encapsulation sub-layer comprises inorganic material, and the material of the second encapsulation sub-layer comprises inorganic material.

10. The display panel of claim 6, wherein, The display panel further comprises: A pixel definition layer is arranged on one side of the substrate, and a plurality of pixel openings are formed in the pixel definition layer, and part of the light emitting unit is located in the corresponding pixel opening.

11. The display panel of claim 10, wherein, Part of the first electrode is located between the substrate and the pixel definition layer, and another part of the first electrode is exposed from the corresponding pixel opening.

12. The display panel of claim 6, wherein, The display panel further comprises: A second encapsulation layer is arranged on the side of the first encapsulation layer away from the substrate. A third encapsulation layer is arranged on the side of the second encapsulation layer away from the substrate.

13. The display panel of claim 12, wherein, The material of the second encapsulation layer comprises organic material, and the material of the third encapsulation layer comprises inorganic material.

14. The display panel of claim 13, wherein, The material of the third encapsulation layer is the same as the material of the first encapsulation layer.

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